This is the part of Gen AI workshop recently we conducted in association with PSNA college and collaborators.

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AI-INSPIRED IOT CHIPLETS AND 3D HETEROGENEOUS INTEGRATION
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2. BroadPak
2.5D/3D Technologies
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OUTLINE
01 • Rapid change in market dynamic
• Change in megatrend priorities
02 • Packaging transformation and the driver
• 3DHI requirement and enablement
03 • Emerging wafer-Level-substrate
• Performance, manufacturing, assembly
04 • Enabling Effective 3DHI integration
• Summary
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FOG COMPUTING
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ADVANCED EDGE COMPUTING, CLOUD
MULTI-DIE, MEMORY-LOGIC
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AUTOMOTIVE POWER DEVICES
SILICON CARBIDE
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5G/6G
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SILICON PHOTONICS
PHOTONIC CHIPLETS, UCIE-OPTICAL I/O
CHANGE IN MEGATREND PATTERN
BASED ON A CORPORATE DESIGN LOAD PERSPECTIVE
Intel
IBM
ee News
Google
Embedded Computing 3
Proprietary & Confidential

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2.5D/3D Technologies
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THE MARKET HAS RAPIDLY CHANGED: ADVANCED EDGE COMPUTING, OPTICS, …)
The modern package demands:
• 3D stacking (multi-material, multi-node, …)
• Higher performance (Electrical, thermal), reliability
• Scalability
• High Density Substrate
• Multi-die, fine bump pitch support
• Test/repair strategy, modular testing
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5. BroadPak
2.5D/3D Technologies
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PACKAGING TRANSFORMATION: SIDE-BY-SIDE 🡪 3DHI
3DHI
2.1D, 2.3D, 2.5D,
silicon Bridge, etc.
Wafer Level Fan-out, PLP
2.5D/3D Silicon interposer
FCBGA
IC
Analog
Controller
MEMS
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6. BroadPak
2.5D/3D Technologies
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The need for near-monolithic integration fueled by rapid change in megatrends
• Memory-logic bandwidth, photonic-CMOS integration, …
3DHI is on the horizon
Emerging substrate technology is enabling near-monolithic integration, both 2D and 3DHI
• Cost competitive
• Sub 1/1um L/S
• Pad less vias, via size the same as line width
• Fine bump pitch support
• Same CTE as the device
• Large body size support with a rigid core
• Thermally conductive
• Superior electrical (RF) performance
• Facilitate modular testing
WHAT'S DRIVING THE PACKAGE TRANSFORMATION?
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7. BroadPak
2.5D/3D Technologies
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◎ Multi-Everything
◉ Multi-discipline
◉ Multi-fab
◉ Multi-requirement
◉ Multi-functionality
◉ Multi-material
◉ Multi-interface
◉ Multi-scale
◉ Multi-…
3DHI IS A DIFFERENT BEAST (MULTI-EVERYTHING IN 3D)
E
n
e
r
g
y
P
o
w
e
r
S
o
u
r
c
e
Processor
Memory
Stack
MEMS,
Imager
Chemical
&
Bio
Sensor
Complex Failure Mode, Domino Effect
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8. BroadPak
2.5D/3D Technologies
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3DHI REQUIREMENTS, MULTI-SIDED SWORD, NO REMORSE!!
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Performance,
Bandwidth,
Density
Thermal
CTE, reliability
Co-existence of multiple technologies
Test
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9. BroadPak
2.5D/3D Technologies
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3D MULTICORE PROCESSOR EXAMPLE
Memory layer
Memory layer
Memory layer
Processor layer
Processor layer
Processor layer
Test & Repair layer
Substrate
16 nm node
5 nm node
• Optimization within Strata
• Optimization within stacks
3D requires two
level optimizations

10. BroadPak
2.5D/3D Technologies
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OPTIMIZE CONNECTIVITY WITHIN STRATA
System Bus
IP IP IP
System Bus
IP IP IP
System Bus
IP IP IP
System Bus
IP IP IP
System TSV Bus
Memory TSV Bus Test TSV Bus
Strata 0
Strata 1
Strata 2
Strata 3

11. BroadPak
2.5D/3D Technologies
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OPTIMIZE CONNECTIVITY WITHIN STACKS
TSV for I/O Buffer
Power and Ground
CORE
PLL
Shared Memory TSV
Bus
Peripherals
System TSV
Bus
Two Stage Optimization
• Horizontal
• Vertical

12. BroadPak
2.5D/3D Technologies
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DARPA 3DHI ROADMAP
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13. BroadPak
2.5D/3D Technologies
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PACKAGE CONVERSION: LAYER REDUCTION
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
PANEL LEVEL:
4-2-4 (10 layers) construction
Through-core vias
M1
M2
M3
M4
Through-core vias
WAFER LEVEL:
Converted to 4-layers
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14. BroadPak
2.5D/3D Technologies
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CONVERGING TO A COMMON PLATFORM FOR 3DHI
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SOC
Organic Substrate, RDL
SOC
FCBGA 2.1D, 2.3D, 2.5D, silicon Bridge, etc.
IC
Fan-out
3DHI
Wafer Level substrate

15. BroadPak
2.5D/3D Technologies
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®
Summary
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16. BroadPak
2.5D/3D Technologies
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®
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Ultra low power processor cores are required for emerging IOT applications
2.5D/3D heterogeneous chiplet integration are required for emerging IOT
applications
Wafer-Level-Substrate demonstrate solid RF performance
Wafer-Level-Substrate demonstrates sub 1um L/S capability, pad less vias and
active/passive embedding capabilities
Wafer-Level-Substrate enables multi-die/chiplet, silicon photonic packaging
3DHI stacking using high bandwidth substrate enables modular testing and
provides effective thermal management
SUMMARY

17. BroadPak
2.5D/3D Technologies
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Thank You
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