The document discusses data transfer instructions in 8085 microprocessor. It describes the LHLD and SHLD instructions. LHLD loads the contents of two consecutive memory locations pointed by a 16-bit address into the HL register pair. SHLD stores the contents of HL register pair into two consecutive memory locations pointed by a 16-bit address. Both instructions use 3 bytes and take 5 machine cycles (16 clock cycles) to execute, with LHLD performing read cycles and SHLD performing write cycles in the last two machine cycles.

1. COMPUTER
ORGANISATION
• TOPIC:DATA TRANSFER
INSTRUCTIONS
• Group:- G2 BATCH:-B3
• MADE BY:15CP032-SIDDHAPURA ROMIL
15CP018-AHALPARA KEVAL
15CP033-KAVAIYA HIREN
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2. 8085 Microprocessor
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• The microprocessor is a
programmable integrated
device that has computing and
decision making capability
similar to that CPU of a
computer.
• It is a multi-purpose,clock-
driven, register-based
electronic device.

3. LET’S BEGIN WITH MAIN DATA
TRANSFER INSTRUCTIONS
• One of the primarily functions of microprocessor is
copying data from source register to destination register.
• This copying function is labeled as data transfer
instructions.
• In fact, contents of the source are not transferred but are
copied into destination without modyfying the content of
source.
• The previous contents of destination are replaced by the
contents by the contents of the source.
• Several instruction are used to copy data which are
listed below:-
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4. LIST OF DATA TRANSFER
INSTRUCTION
• MOV Rd,Rs:- Copies data from source register Rs to
destination register Rd.
• MVI R,8-bit:- Loads the 8-bit of the second byte into
the register specified.
• OUT 8-bit port address:- Sends the contents of the
accumulator (A) to the output port specified
in the second byte.
• IN 8-bit port address:-Accepts the data from the input
port specified in second byte ,and loads
into the accumulator.
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5. “LHLD” INSTRUCTION
• LHLD stands for Load H and L Registers Direct .
• This instruction copies the contents of the memory
location pointed by the 16-bit address in register L and
copies the contents of the next memory location in
register H. The contents of source memory locations are
not altered.
• Flags:- The execution of LHLD instruction can not affect
the flags.
• Example:- Assume memory allocation 1050H contains
30H and 1051H contains 32H.This instruction transfer
memory contents to register pair HL.
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6. • For above example Instruction :- LHLD 1050H
Hex code :- 2A 50 10
• Memory contents before instruction:-
• Registers contents after instruction:-
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1050 30
1051 32
H 32
L 30

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LHLD timing diagram

8. • In 1st Machine cycles, the 8085 microprocessor places
the address of memory loaction on the address bus and
fetches the opcode of LHLD instruction.
• The second machine cycle is read. In this machine cycle
processor places the address of next incremented
memory location and gets the low-order byte.
• The third machine cycle is also read. This machine cycle
also perform the same as second machine cycle and
gets the high-order byte instead of low-order byte.
• In the fourth machine cycle, contents of the memory
location pointed out by 16-bit address copies into
register L.
• In the fifth machine cycle, contents of the next memory
location copies into register H.
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9. Number of bytes used in instruction:- 3
bytes
Total no. of machine cycles:- 5(F,R,R,R,R)
Total no. of clock cycles:-16
Addressing modes:-Register direct
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10. “SHLD” INSTRUCTION
• SHLD stands for store H and L Registers Direct.
• The contents of register L are stored in the memory
location specified by the 16- bit address in the operand,
and the contents of H registers are stored in the next
memory location by incrementing the operand.
• Remember, the contents of the HL pair register are not
altered.
• This is also a 3-byte instruction. The second byte
specifies the low-order address and the third byte
specifies the high-order address.
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11. • Flags:- No flags are affected.
• Example:-Assume the H and L registers contain 01H and
FFH, respectively at memory location 1050H and 1051H.
• Instruction:- SHLD 1050H Hex code:- 22 50 10
• Register contents before instruction:-
• Register and memory contents before instruction:-
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H 01
L FF
1050 FF
1051 01
H 01
L FF

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SHLD timing diagram

13. • In SHLD instruction, first 3 cycle is same as in described
in LHLD instruction.
• In SHLD instruction, 4th and 5th cycle will be write cycle.
• So, in 4th cycle, contents of the register L are stored in
the memory pointed by the address in operand, and
during 5th machine cycle,contents of the register H are
stored in next memory location.
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14. Number of bytes used in instruction:- 3
bytes
Total no. of machine cycles:- 5
(F,R,R,W,W)
Total no. of clock cycles:-16
Addressing modes:-Register direct
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