A 128 bit comparator is designed with conventional digital cmos gates that make use of parallel
prefix tree structure. The comparison is performed bit wise proceeding from most significant bit to least
significant bit. The comparison of lower bits is carried only when the most significant bits are equal which
decreases the power dissipation in the circuit. To make the circuit regular the design is made using only cmos
logic gates. The transmission gates used in the existing design are replaced with the simple AND gates so that
the entire circuit can be designed in gate level. This 128 bit comparator is designed in cadence environment
using tsmc 0.18μm technology with a power dissipation of 0.28mw and with a delay of 0.09ms.
DESIGN AND VHDL IMPLEMENTATION OF 64-POINT FFT USING TWO STRUCTURE 8-POINT FF...Journal For Research
In this paper, we present a novel fixed-point 32-bit word-width Radix-2 64-point FFT processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). FFT blocks are complex to implement and it consumes more resources. So, a efficient technique used here in which FFT is implemented in such a way that it consumes very less resources. This module of 64-point FFT is designed using VHDL programming language. In this work, a pure VHDL design, integrated with some intellectual property (IP) blocks and simulation, synthesis and implementation XILINX ISE 13.2 software is used.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced E...ijceronline
This paper presents a high speed, FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) in which the different steps of AES is applied in a parallel manner. This implementation can reduce the latency in which the process of implementation is reduced in a drastic manner. The paper deals with a comparison of the normal implementation of steps of AES and the parallel implementation. Inorder to increase the throughput of the AES encryption process the latency of the AES process should be reduced. Among Add Round Key, Sub Bytes, Shift Rows and Mix Columns, Sub Bytes and Mix Columns produce more latency. The execution delay of Mix Columns results in 60 percent of the total latency. Therefore Parallel Mix Columns is used inorder to reduce the latency. In this the block computes one column at a time such that the four columns are executed at the same time rather than each byte executing at a time. In Parallel Sub Bytes, four columns are executed at the same time rather than each byte executing at a time, this reduces the latency. Encryption is the process of encoding information so it cannot be read by hackers. The information is encrypted using algorithms and is converted into unreadable form, called cipher text. The authorized person will decode the information using decryption algorithms. The cryptography algorithms are of three types -symmetric cryptography (using 1 key for encryption/decryption), asymmetric cryptography (using 2 different keys for encryption/decryption), and cryptographic hash functions using no keys (the key is not a separate input but is mixed with the data).
Synthesized report on the comparison of lut and splitting method for decrypti...eSAT Journals
Abstract Any encryption or decryption method will have certain key based on which the encoding and decoding will be performed. This is done to avoid access of data by unauthorized personal. Without the decoding key, encoded data is junk. Similarly, Federal Information Processing Standard (FIPS) developed Advanced Encryption Standard, which was used for saving digital data especially in magnetic tape like debit cards and credit cards, so that it provides security for the details and also this can be used in security of PDA’s which need to work very efficiently with high speed encoding and decoding and also need to consume less area as possible. It can be built using purely hardware or purely software i.e. using programming language such as Verilog. Decryption and Encryption has main part, Mix Columns and Inverse Mix columns, on which the whole AES operation depends. Here synthesis is performed for the decryption unit of the AES, which can be performed in two methods i.e. Look-up Table and Splitting method. Comparison of two methods is done by synthesizing the program in Spartan -3E of Xilinx ISE 14.1 Suite. Keywords: Encryption, Decryption, FIPS, Mix Columns, Inverse Mix Columns.
You will learn about linear data structures like stack and Queue. and also implementation by using array and linked list. at last, we will discuss the various applications of stack and queue and other varients of queues.
DESIGN AND VHDL IMPLEMENTATION OF 64-POINT FFT USING TWO STRUCTURE 8-POINT FF...Journal For Research
In this paper, we present a novel fixed-point 32-bit word-width Radix-2 64-point FFT processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). FFT blocks are complex to implement and it consumes more resources. So, a efficient technique used here in which FFT is implemented in such a way that it consumes very less resources. This module of 64-point FFT is designed using VHDL programming language. In this work, a pure VHDL design, integrated with some intellectual property (IP) blocks and simulation, synthesis and implementation XILINX ISE 13.2 software is used.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced E...ijceronline
This paper presents a high speed, FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) in which the different steps of AES is applied in a parallel manner. This implementation can reduce the latency in which the process of implementation is reduced in a drastic manner. The paper deals with a comparison of the normal implementation of steps of AES and the parallel implementation. Inorder to increase the throughput of the AES encryption process the latency of the AES process should be reduced. Among Add Round Key, Sub Bytes, Shift Rows and Mix Columns, Sub Bytes and Mix Columns produce more latency. The execution delay of Mix Columns results in 60 percent of the total latency. Therefore Parallel Mix Columns is used inorder to reduce the latency. In this the block computes one column at a time such that the four columns are executed at the same time rather than each byte executing at a time. In Parallel Sub Bytes, four columns are executed at the same time rather than each byte executing at a time, this reduces the latency. Encryption is the process of encoding information so it cannot be read by hackers. The information is encrypted using algorithms and is converted into unreadable form, called cipher text. The authorized person will decode the information using decryption algorithms. The cryptography algorithms are of three types -symmetric cryptography (using 1 key for encryption/decryption), asymmetric cryptography (using 2 different keys for encryption/decryption), and cryptographic hash functions using no keys (the key is not a separate input but is mixed with the data).
Synthesized report on the comparison of lut and splitting method for decrypti...eSAT Journals
Abstract Any encryption or decryption method will have certain key based on which the encoding and decoding will be performed. This is done to avoid access of data by unauthorized personal. Without the decoding key, encoded data is junk. Similarly, Federal Information Processing Standard (FIPS) developed Advanced Encryption Standard, which was used for saving digital data especially in magnetic tape like debit cards and credit cards, so that it provides security for the details and also this can be used in security of PDA’s which need to work very efficiently with high speed encoding and decoding and also need to consume less area as possible. It can be built using purely hardware or purely software i.e. using programming language such as Verilog. Decryption and Encryption has main part, Mix Columns and Inverse Mix columns, on which the whole AES operation depends. Here synthesis is performed for the decryption unit of the AES, which can be performed in two methods i.e. Look-up Table and Splitting method. Comparison of two methods is done by synthesizing the program in Spartan -3E of Xilinx ISE 14.1 Suite. Keywords: Encryption, Decryption, FIPS, Mix Columns, Inverse Mix Columns.
You will learn about linear data structures like stack and Queue. and also implementation by using array and linked list. at last, we will discuss the various applications of stack and queue and other varients of queues.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
Information and network security 20 data encryption standard desVaibhav Khanna
The Data Encryption Standard is a symmetric-key algorithm for the encryption of digital data. Although its short key length of 56 bits makes it too insecure for applications, it has been highly influential in the advancement of cryptography.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High Speed Area Efficient 8-point FFT using Vedic MultiplierIJERA Editor
A high speed fast fourier transform (FFT) design by using three algorithm is presented in this paper. In algorithm 3, 4-bit Vedic multiplier based technique are used in FFT. In this technique used in three 4-bit ripple carry adder and four 2*2 Vedic multiplier. The main parameter of this paper is number of slice, 4-input LUTS and maximum combinational path delay were calculate.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywords— advanced computing, Reversible logic circuits, reversible logic gates and comparator
AN EFFICIENT BASE-4 LEADING ZERO DETECTOR DESIGNEEIJ journal
A base-4 leading zero detector (LZD) design is proposed in this paper. The design is similar to the
approach originally proposed by V.G. Oklobdzija with a different technique. The circuit modules used in
the base-4 LZD approach are designed and several N-bit LZD circuits are implemented with a standardcell
realization in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.65um CMOS process.
The performance and layout area of the base-4 LZD realization is compared for implementations that
contain only 4-to-1 and 2-to-1 multiplexers.
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
Information and network security 20 data encryption standard desVaibhav Khanna
The Data Encryption Standard is a symmetric-key algorithm for the encryption of digital data. Although its short key length of 56 bits makes it too insecure for applications, it has been highly influential in the advancement of cryptography.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High Speed Area Efficient 8-point FFT using Vedic MultiplierIJERA Editor
A high speed fast fourier transform (FFT) design by using three algorithm is presented in this paper. In algorithm 3, 4-bit Vedic multiplier based technique are used in FFT. In this technique used in three 4-bit ripple carry adder and four 2*2 Vedic multiplier. The main parameter of this paper is number of slice, 4-input LUTS and maximum combinational path delay were calculate.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywords— advanced computing, Reversible logic circuits, reversible logic gates and comparator
AN EFFICIENT BASE-4 LEADING ZERO DETECTOR DESIGNEEIJ journal
A base-4 leading zero detector (LZD) design is proposed in this paper. The design is similar to the
approach originally proposed by V.G. Oklobdzija with a different technique. The circuit modules used in
the base-4 LZD approach are designed and several N-bit LZD circuits are implemented with a standardcell
realization in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.65um CMOS process.
The performance and layout area of the base-4 LZD realization is compared for implementations that
contain only 4-to-1 and 2-to-1 multiplexers.
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High speed tree-based 64-bit cmos binary comparatoreSAT Journals
Abstract A high-speed tree-based 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means some modifications are done in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool. Index Terms: Binary comparator, digital arithmetic, high-speed
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
A 8-bit high speed ADC using Intel μP 8085IJERD Editor
An 8-bit ADC Architecture of is proposed, it uses 16 comparators and produces 8-bit digital code in half the time as that of successive approximation technique. In this approach, the analog input range is partitioned into 16 quantization cells, separated by 15 boundary points. A 4-bit binary code 0000 to 1111 is assigned to each cell. The results show that the ADC exhibits a maximum DNL of 0.49LSB and a maximum INL of 0.51LSB.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitch. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. Here the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision are considered. In this multiple constant multiplication/accumulation (MCMA) is used to reduce the area, which reduces the cost and power dissipation and hardware resources also reduced. The MCMA module is realized by accumulating all the partial products (PPs) where unnecessary PP bits (PPBs) are removed without affecting the final precision of the outputs. The bit widths of all the filter coefficients are minimized using non uniform quantization with unequal word lengths in order to reduce the hardware cost while still satisfying the specification of the frequency response.
High Speed Low Power Veterbi Decoder Design for TCM Decodersijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Exploratory study on the use of crushed cockle shell as partial sand replacem...IJRES Journal
The increasing demand for natural river sand supply for the use in construction industry along
with the issue of environmental problem posed by the dumping of cockle shell, a by-product from cockle
business have initiated research towards producing a more environmental friendly concrete. This research
explores the potential use of cockle shell as partial sand replacement in concrete production. Cockle shell used
in this experimental work were crushed to smaller size almost similar to sand before mixed in concrete. A total
of six concrete mixtures were prepared with varying the percentages of cockle shell viz. 0%, 5%, 10%, 15%,
20% and 25%. All the specimens were subjected to continuous water curing. The compressive strength test was
conducted at 28 days in accordance to BS EN 12390. Finding shows that integration of suitable content of
crushed cockle shell of 10% as partial sand replacement able to enhance the compressive strength of concrete.
Adopting crushed cockle shell as partial sand replacement in concrete would reduce natural river sand
consumption as well as reducing the amount of cockle shell disposed as waste.
Congenital Malaria: Correlation of Umbilical Cord Plasmodium falciparum Paras...IJRES Journal
The vertical (trans-placental) transmission of the parasite Plasmodium falciparum from
pregnant mother to fetus during gestational period was investigated in a clinical research involving 43 full term
pregnant women in selected Hospitals in Jimeta Yola, Adamawa State Nigeria. During the observational study,
parasitemia was determined by light microscopic examination of umbilical and maternal peripheral blood film
for the presence of the trophozoites of Plasmodium falciparum. Correlational analysis was then carried on the
result obtained at p<0.05.><0.05) was established between maternal peripheral blood and umbilical cord
blood parasitemia with Pearson’s correlation coefficient of 0.762. Thus, in a malaria endemic area like Yola,
Adamawa State, Nigeria, with a stable transmission of parasite, there is a high probability of vertical
transmission of Plasmodium falciparum parasite from mother to fetus during gestation that can be followed by
the presentation of the symptoms of malaria by the newborn and other malaria related complications. Families
are advised to consistently sleep under appropriately treated insecticide mosquito net to avoid mosquito bite and
subsequent infestation.
Review: Nonlinear Techniques for Analysis of Heart Rate VariabilityIJRES Journal
Heart rate variability (HRV) is a measure of the balance between sympathetic mediators of heart
rate that is the effect of epinephrine and norepinephrine released from sympathetic nerve fibres acting on the
sino-atrial and atrio-ventricular nodes which increase the rate of cardiac contraction and facilitate conduction at
the atrio-ventricular node and parasympathetic mediators of heart rate that is the influence of acetylcholine
released by the parasympathetic nerve fibres acting on the sino-atrial and atrio-ventricular nodes leading to a
decrease in the heart rate and a slowing of conduction at the atrio-ventricular node. Sympathetic mediators
appear to exert their influence over longer time periods and are reflected in the low frequency power(LFP) of
the HRV spectrum (between 0.04Hz and 0.15 Hz).Vagal mediators exert their influence more quickly on the
heart and principally affect the high frequency power (HFP) of the HRV spectrum (between 0.15Hz and 0.4
Hz). Thus at any point in time the LFP:HFP ratio is a proxy for the sympatho- vagal balance. Thus HRV is a
valuable tool to investigate the sympathetic and parasympathetic function of the autonomic nervous system.
Study of HRV enhance our understanding of physiological phenomenon, the actions of medications and disease
mechanisms but large scale prospective studies are needed to determine the sensitivity, specificity and predictive
values of heart rate variability regarding death or morbidity in cardiac and non-cardiac patients. This paper
presents the linear and nonlinear to analysis the HRV.
Dynamic Modeling for Gas Phase Propylene Copolymerization in a Fluidized Bed ...IJRES Journal
A two-phase model is proposed for describing the dynamics of a fluidized bed reactor used for
polypropylene production. In the proposed model, the fluidized bed is divided into an emulsion and bubble
phase where the flow of gas is considered to be plug flow through the bubbles and perfectly mixed through the
emulsion phase. Similar previous models, consider the reaction in the emulsion phase only. In this work the
contribution of reaction in the bubble phase is considered and its effect on the overall polypropylene production
is investigated the kinetic model is combined with hydrodynamic model in order to develop a comprehensive
model for gas-phase propylene copolymerization reactor. Simulation profiles of the proposed model were
compared with those of well mixed model for the emulsion phase temperature. The simulated temperature
profile showed a lower rate of change compared to the previously reported models due to lower polymerization
rate. Model simulation showed that about 13% of the produced polymer comes from the bubble phase and this
considerable amount of polymerization in the bubbles should not be neglected in any modeling attempt.
Study and evaluation for different types of Sudanese crude oil propertiesIJRES Journal
Sudanese crude oil is regarded as one of the sweet types of crude in the world, Sulphur containing
compounds are un desirable in petroleum because they de activate the catalyst during the refining processes and
are the main source of acid rains and environmental pollution.(Mark Cullen 2001),Since it contains considerable
amount of salts and acids, it negatively impact the production facilities and transportation lines with corrosive
materials. However it suffers other problems in flow properties represented by the high viscosity and high
percentage of wax. Samples were collected after the initial and final treatment at CPF, and tested for
physical and chemical properties.wax content is in the range 23-31 weight % while asphalting content is about
0.1 weight% . Resin content is 13-7 weight % and deposits are 0.01 weight%. The carbon number distribution in
the crude is in the range 7-35 carbon atoms. The pour point vary between 39°C-42°C and the boiling point is in
the range 70 °C - 533 °C.
A Short Report on Different Wavelets and Their StructuresIJRES Journal
This article consists of basics of wavelet analysis required for understanding of and use of wavelet
theory. In this article we briefly discuss about HAAR wavelet transform their space and structures.
A Case Study on Academic Services Application Using Agile Methodology for Mob...IJRES Journal
Recently, Mobile Cloud Computing reveals many modern development areas in the Information
Technology industry. Several software engineering frameworks and methodologies have been developed to
provide solutions for deploying cloud computing resources on mobile application development. Agile
methodology is one of the most commonly used methodologies in the field. This paper presents the MCCAS a
Web and Mobile application that provide feature for the Palestinian higher education/academic institutions. An
Agile methodology was used in the development of the MCCAS but in parallel with emphasis on Cloud
computing resources deployment. Also many related issues is discussed such as how software engineering
modern methodologies (advances) influenced the development process.
Wear Analysis on Cylindrical Cam with Flexible RodIJRES Journal
Firstly, the kinetic equation of spatial cylindrical cam with flexible rod has been established. Then, an
accurate cylindrical cam mechanism model has been established based on the spatial modeling software
Solidworks. The dynamic effect of flexible rod on mechanical system was studied in detail based on the
mechanical system dynamics analytical software Adams, and Archard wear model is used to predict the wear of
the cam. We used Ansys to create finite element model of the cam link, extracted the first five order mode to
export into Adams. The simulation results show that the dynamic characteristics of spatial cylindrical cam
mechanical system with flexible rod is closed to ideal mechanism. During the cam rotate one cycle, the collision
in the linkage with a clearance occurs in some special location, others still keep a continuous contact, and the
prediction of wear loss is smaller than rigid body.
DDOS Attacks-A Stealthy Way of Implementation and DetectionIJRES Journal
Cloud Computing is a new paradigm provides various host service [paas, saas, Iaas over the internet.
According to a self-service,on-demand and pay as you use business model,the customers will obtain the cloud
resources and services.It is a virtual shared service.Cloud Computing has three basic abstraction layers System
layer(Virtual Machine abstraction of a server),Platform layer(A virtualized operating system, database and
webserver of a server and Application layer(It includes Web Applications).Denial of Service attack is an attempt
to make a machine or network resource unavailable to the intended user. In DOS a user or organization is
deprived of the services of a resource they would normally expect to have.A Successful DOS attack is a highly
noticeable event impacting the entire online user base.DOS attack is found by First Mathematical Metrical
Method (Rate Controlling,Timing Window,Worst Case and Pattern Matching)DOS attack not only affect the
Quality of the service and also affect the performance of the server. DDOS attacks are launched from Botnet-A
large Cluster of Connected device(cellphone,pc or router) infected with malware that allow remote control by an
attacker. Intruder using SIPDAS in DDOS to perform attack.SIPDAS attack strategies are detected using Heap
Space Monitoring Algorithm.
An improved fading Kalman filter in the application of BDS dynamic positioningIJRES Journal
Aiming at the poor dynamic performance and low navigation precision of traditional fading
Kalman filter in BDS dynamic positioning, an improved fading Kalman filter based on fading factor vector is
proposed. The fading factor is extended to a fading factor vector, and each element of the vector corresponds to
each state component. Based on the difference between the actual observed quantity and the predicted one, the
value of the vector is changed automatically. The memory length of different channel is changed in real time
according to the dynamic property of the corresponding state component. The actual observation data of BDS is
used to test the algorithm. The experimental results show that compared with the traditional fading Kalman filter
and the method of the third references, the positioning precision of the algorithm is improved by 46.3% and
23.6% respectively.
Positioning Error Analysis and Compensation of Differential Precision WorkbenchIJRES Journal
Positioning error is a widely problem exists in mechanism, the important factors affecting machining
precision. In order to reduce the error caused by positioning problem processing, based on the differential
workbench as the research object, using the method of theoretical analysis and experimental verification, the
analysis of positioning error mechanism and source of complete differential precision workbench error
compensation, improve the accuracy of the device, provides a method for the application of modern machine
tools. table.
Status of Heavy metal pollution in Mithi river: Then and NowIJRES Journal
The Mithi River runs through the heart of suburban Mumbai. Its path of flow has been severely
damaged due to industrialization and urbanization. The quality of water has been deteriorating ever since. The
Municipal and industrial effluents are discharged in unchecked amounts. The municipal discharge comprises
untreated domestic and sewage wastes whereas the industries are majorly discharge chemicals and other toxic
effluents which are responsible in increasing the metal load of the river. In the current study, the water is
analysed for heavy metals- Copper, Cadmium, Chromium, Lead and Nickel. It also includes a brief
understanding on the fluctuations that have occurred in the heavy metal pollution, through the compilation of
studies carried out in the area previously.
The Low-Temperature Radiant Floor Heating System Design and Experimental Stud...IJRES Journal
In order to analyze the temperature distribution of the low-temperature radiant floor heating system
that uses the condensing wall-hung boiler as the heat source, the heating system is designed according to a typical
house facing south in Shanghai. The experiments are carried out to study the effects of the supply water
temperature on the thermal comfort of the system. Eventually, the supply water temperature that makes people in
the room feel more comfortable is obtained. The result shows that in the condition of that the outside temperature
is 8~15℃ and the relative humidity is 30~70%RH, the temperature distribution in the room is from high to low
when the height is from bottom to top. The floor surface temperature is highest, but its uniformity is very poor.
When the heating system reaches the steady state, the air temperature of the room is uniform. When the supply
water temperature is 63℃ The room is relatively comfortable at the above experimental condition.
Experimental study on critical closing pressure of mudstone fractured reservoirsIJRES Journal
In the process of oil and gas exploitation of mudstone-fractured reservoir in Daqing oilfield, the
permeability of fracture is easily affected by the influence of stress change, which is shown by the sensitivity of
the permeability to the stress. With the extension of time mining in the fractured mudstone reservoir, fracture
stress sensitivity is obvious in vast decline of production and great influence on reduced yields. In order to
reasonably determine the way of developing method, working system and the exploitation rate of the reservoir,
correspondingly protecting reservoir productivity, improve ultimate recovery. On the basis of the previous
research on the stress sensitivity of fractured mudstone, this essay studied the critical closing pressure of the
simulated underground fractured mudstone under the laboratory condition.
Correlation Analysis of Tool Wear and Cutting Sound SignalIJRES Journal
With the classic signal analysis and processing method, the cutting of the audio signal in time
domain and frequency domain analysis. We reached the following conclusions: in the time domain analysis,
cutting audio signals mean and the variance associated with tool wear state change occurred did not change
significantly, and tool wear is not high degree of correlation, and the mean-square value of the audio signal
changes in the size and tool wear the state has a good relationship.
Reduce Resources for Privacy in Mobile Cloud Computing Using Blowfish and DSA...IJRES Journal
Mobile cloud computing in light of the increasing popularity among users of mobile smart
technology which is the next indispensable that enables users to take advantage of the storage cloud computing
services. However, mobile cloud computing, the migration of information on the cloud is reliable their privacy
and security issues. Moreover, mobile cloud computing has limitations in resources such as power energy,
processor, Memory and storage. In this paper, we propose a solution to the problem of privacy with saving and
reducing resources power energy, processor and Memory. This is done through data encryption in the mobile
cloud computing by symmetric algorithm and sent to the private cloud and then the data is encrypted again and
sent to the public cloud through Asymmetric algorithm. The experimental results showed after a comparison
between encryption algorithms less time and less time to decryption are as follows: Blowfish algorithm for
symmetric and the DSA algorithm for Asymmetric. The analysis results showed a significant improvement in
reducing the resources in the period of time and power energy consumption and processor.
Resistance of Dryland Rice to Stem Borer (Scirpophaga incertulas Wlk.) Using ...IJRES Journal
Rice stem borer is one of the important pests that attack plants so as to reduce production. One way
to control pests is to use organic fertilizers that make the plant stronger and healthier. This study was conducted
to determine the effects of organic fertilizers with various doses without the use of pesticides in controlling stem
borer, Scirpophaga incertulas. Methods using split-split plot design which consists of two levels of the whole
plot factor (solid and liquid organic fertilizers), two levels of the subplot factor (conventional and industry,
Tiens and Mitraflora), and four levels of the sub-subplot factor of conventional and industry (5, 10, 15, 20
tonnes/ha), and one level of the sub-subplot factor of Tiens and Mitraflora (each 2 ml/l). Based on the results
Statistical analysis there were no significant differences among treatments and this shows that the use of organic
fertilizers that only a dose of 5 tonnes/ha is sufficient available nutrients that make plants more robust and
resistant to control stem borer, besides that can reduce production costs and friendly to the environment when
compared with using inorganic fertilizers.
A novel high-precision curvature-compensated CMOS bandgap reference without u...IJRES Journal
A novel high-precision curvature-compensated bandgap reference (BGR) without using op-amp
is presented in this paper. It is based on second-order curvature correction principle, which is a weighted sum of
two voltage curves which have opposite curvature characteristic. One voltage curve is achieved by first-order
curvature-compensated bandgap reference (FCBGR) without using op-amp and the other found by using W
function is achieved by utilizing a positive temperature coefficient (TC) exponential current and a linear
negative TC current to flow a linear resistor. The exponential current is gained by using anegative TC voltage to
control a MOSFET in sub-threshold region. In the temperature ranging from -40℃ to 125℃, experimental
results implemented with SMIC 0.18μm CMOS process demonstrate that the presented BGR can achieve a TC
as low as 2.2 ppm/℃ and power-supply rejection ratio(PSRR)is -69 dB without any filtering capacitor at 2.0 V.
While the range of the supply voltage is from 1.7 to 3.0 V, the output voltage line regulation is about1 mV/ V
and the maximum TC is 3.4 ppm/℃.
Structural aspect on carbon dioxide capture in nanotubesIJRES Journal
In this work we reported the carbon dioxide adsorption (CO2) in six different nanostructures in order
to investigate the capturing capacity of the materials at nanoscale. Here we have considered the three different
nanotubes including zinc oxide nanotube (ZnONT), silicon carbide nanotube (SiCNT) and single walled carbon
nanotube (SWCNT). Three different chiralities such as zigzag (9,0), armchair (5,5) and chiral (6,4) having
approximately same diameter are analyzed. The adsorption binding energy values under various cases are
estimated with density functional theory (DFT). We observed CO2 molecule chemisorbed on ZnONT and
SiCNT’s whereas the physisorption is predominant in CNT. To investigate the structural aspect, the tubes with
defects are studied and compared with defect free tubes. We have also analyzed the electrical properties of tubes
from HOMO, LUMO energies. Our results reveal the defected structure enhance the CO2 capture and is
predicted to be a potential candidate for environmental applications.
Thesummaryabout fuzzy control parameters selected based on brake driver inten...IJRES Journal
In this paper, the brake driving intention identification parameters based on the fuzzy control are
summarized and analyzed, the necessary parameters based on the fuzzy control of the brake driving intention
recognition are found out, and I pointed out the commonly corrupt parameters, and through the relevant
parameters , I establish the corresponding driving intention model.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
An Approach to Detecting Writing Styles Based on Clustering Techniquesambekarshweta25
An Approach to Detecting Writing Styles Based on Clustering Techniques
Authors:
-Devkinandan Jagtap
-Shweta Ambekar
-Harshit Singh
-Nakul Sharma (Assistant Professor)
Institution:
VIIT Pune, India
Abstract:
This paper proposes a system to differentiate between human-generated and AI-generated texts using stylometric analysis. The system analyzes text files and classifies writing styles by employing various clustering algorithms, such as k-means, k-means++, hierarchical, and DBSCAN. The effectiveness of these algorithms is measured using silhouette scores. The system successfully identifies distinct writing styles within documents, demonstrating its potential for plagiarism detection.
Introduction:
Stylometry, the study of linguistic and structural features in texts, is used for tasks like plagiarism detection, genre separation, and author verification. This paper leverages stylometric analysis to identify different writing styles and improve plagiarism detection methods.
Methodology:
The system includes data collection, preprocessing, feature extraction, dimensional reduction, machine learning models for clustering, and performance comparison using silhouette scores. Feature extraction focuses on lexical features, vocabulary richness, and readability scores. The study uses a small dataset of texts from various authors and employs algorithms like k-means, k-means++, hierarchical clustering, and DBSCAN for clustering.
Results:
Experiments show that the system effectively identifies writing styles, with silhouette scores indicating reasonable to strong clustering when k=2. As the number of clusters increases, the silhouette scores decrease, indicating a drop in accuracy. K-means and k-means++ perform similarly, while hierarchical clustering is less optimized.
Conclusion and Future Work:
The system works well for distinguishing writing styles with two clusters but becomes less accurate as the number of clusters increases. Future research could focus on adding more parameters and optimizing the methodology to improve accuracy with higher cluster values. This system can enhance existing plagiarism detection tools, especially in academic settings.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Heap Sort (SS).ppt FOR ENGINEERING GRADUATES, BCA, MCA, MTECH, BSC STUDENTS
128 Bit Parallel Prefix Tree Structure Comparator
1. International Journal of Research in Engineering and Science (IJRES)
ISSN (Online): 2320-9364, ISSN (Print): 2320-9356
www.ijres.org Volume 3 Issue 10 ǁ October. 2015 ǁ PP.43-51
www.ijres.org 43 | Page
128 Bit Parallel Prefix Tree Structure Comparator
S. ChandraSekhar1
, J. Lakshmi Prasanna2
1
Assistant Professor, Department of Electronics and Communication Engineering, Dhanekula institute of
engineering and technology, Vijayawada, India.
2
PG scholar, Dhanekula institute of engineering and technology, Vijayawada, India.
Abstract- A 128 bit comparator is designed with conventional digital cmos gates that make use of parallel
prefix tree structure. The comparison is performed bit wise proceeding from most significant bit to least
significant bit. The comparison of lower bits is carried only when the most significant bits are equal which
decreases the power dissipation in the circuit. To make the circuit regular the design is made using only cmos
logic gates. The transmission gates used in the existing design are replaced with the simple AND gates so that
the entire circuit can be designed in gate level. This 128 bit comparator is designed in cadence environment
using tsmc 0.18µm technology with a power dissipation of 0.28mw and with a delay of 0.09ms.
I. INTRODUCTION
Comparator is a logic circuit that is used to compare the magnitude of two given numbers. Comparators are
key design elements in many mathematical and scientific applications. It is used in wide range of applications to
support scientific computations, signature analysis and test circuits etc. Some of the comparators are designed
using adder architectures. These types of architectures are slow and occupy more area even though we
implement fast adders. Some of the comparators are designed using multiplexer architectures. These
architectures divide the n bit input into 2 n/2 bits and the result of two n/2 comparators is given to the
multiplexer but the power consumption of the circuit becomes very high. Some of the comparators are designed
using all N transistor (ANT) circuits. But all the nmos transistors connected in series enter into saturation mode
during operation which leads to overall increase in conductive resistance.
Some of the comparators use priority encoder architectures. These architectures divide the n bit input into 2
n/2 bits and the result of two n/2 comparators is given to the priority encoder so that it considers the msb priority
first. Here in our project we use parallel prefix architecture. In this architecture the n bit inputs are divided into
n/4 modules each module compares individual 4 bits. The comparison is carried from the most significant bit to
the least significant bit. The comparison is carried out only when the most significant bits are equal. If at all a
decision can be taken in the initial modules then the next modules will not perform comparison operation
thereby saving the power. The details about this architecture can be studied from the following chapter.
Figure1: Block diagram of 128 bit comparator architecture with comparison module and decision module
The comparator comparison module is a parallel prefix structure that performs bitwise comparison of 128
bit operands. The input operands A and B are denoted as A128,A127,A126………A2,A1,A0 and
B128,B127,B126…….. B2, B1, B0. The comparator resolution module performs bit wise comparison from MSB to
2. 128 Bit Parallel Prefix Tree Structure Comparator
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LSB such that the comparison is triggered only when the higher order of bits are equal. The comparison
resolution module encodes the comparison bits into two buses that is left bus and right bus such that each bus
stores the partial comparison result as each bit is compared such that
If An > Bn then left n = 1 and right n = 0
An> Bn then left n = 0 and right n = 1
An = Bn then left n = 0 and right n = 0
The decision module uses or-network to make a final comparison decision based on the bits of left bus and
rights bus.
If
lr =00 then A = B
lr = 01 then A < B
lr = 10 then A > B
II. COMPARATOR ARCHITECTURE
Figure2: 128 Bit Comparator Architecture
The comparator architecture consists of comparison module and the decision module. The comparison
module performs the comparison of the give input bits. As we are designing a 128 bit comparator the 128 bits
are grouped into 4 bits and each four bits are compared in a single module and we have 32 modules each
comparing 4 bits. Each 4 bit comparator module takes two 4 bit input operands one enable signal from the
previous comparator module. This enable signal helps in triggering the present module for comparison. Each 4
bit comparator module has 4 outputs that are associated with the decision module and one enable output that
acts as enable input for the next comparator module for comparison. The decision module gets its input from the
comparison module. Each comparison module gives 4 outputs for 4 input bits. In this way we get a total of 128
outputs from the comparison module each single output for 128 inputs. Each four inputs are combined to get a
single output. This procedure is followed until we get our final 3 outputs which are A greater than B (A>B), A
less than B (A<B), A equal to B (A=B). Each 4 bit comparator module of the comparison module is again
divided into five hierarchical set elements that perform the comparison operation in a serial manner. We
partition the comparator resolution module structure into five hierarchal prefixing sets.
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Figure3: Tree structure of comparison module
III. COMPARATOR DESIGN
The comparison module performs bitwise comparison using a tree structure. In the comparison module we
use five Sets of elements. Each set performs an individual operation of comparison. Set -1 performs comparison
of two individual bits of A and B. The output of set-1 acts as the input of set-2 .set-2 combines the output of four
set-1 outputs. The output of set-2 acts as input to set-3. The output of set-3 acts as enable input to set-4
elements. The output of set-4 element acts as enable input to set-5 element. The output of set-5 element forms
right and left bus bits. The right and left bus bits from the comparison module are given to the decision module
which performs or-operation and decides whether A is greater than B or A is less than B or A is equal to B.
Set 1 compares the N-bit operands A and B bit-by-bit, using a single level of set 1type cells. The set_1type cells
provide a termination flag Di to cells in sets 2 and 4, indicating whether the computation should terminate or to
proceed. These cells compute XOR operation.
Set 2 consists of set _2 type cells, which combine the termination flags for each of the four cells from set 1
(each _2-type cell combines the termination flags of one 4-b partition) using NOR-logic to limit the fan-in and
fan-out to a maximum of four. The set _2type cells either continue the comparison for bits of lesser significance
if all four inputs are 0s, or terminate the comparison if a final decision can be made. For 0 ≤ m ≤ N/4–1, there is
a total of N/4 _2-type cells, all functioning in parallel
Set 3 consists of set_3-type cells, which are similar to set _2 type cells, but can have more logic levels,
different inputs, and carry different triggering points. Set_3 type cells provide no comparison functionality. The
cell’s sole purpose is to limit the fan-in and fan-out regardless of operand bit width. To limit the set _3-type
cell’s, the number of levels in set 3 increases if the fan-in exceeds four. Set 3 provides functionality similar to
set 2 using the AND logic to continue or terminate the bitwise comparison activity. If the comparison is
terminated, set 3 signals set 4 to set the left bus and right bus bits to 0 for all bits of lower significance. For 0 ≤
m ≤ N/4 − 1, there is a total of N/4 set _3 type cells per level. From left to right, the first four set_3 type cells in
set 3 combine the 4-b partition comparison outcomes from the one, two, three, and four 4-b partitions of set 2.
Since the fourth set_3 type cell has a fan-in of four, the number of levels in set 3 increases and set 3’s fifth cell
combines the comparison outcomes of the first 16 MSBs with a fan-in of only two and a fan-out of one.
S3,m =S2,m-1.S2,m
Where m indicates the module number
S2,m indicates the output from present module set-2
S2,m-1 indicates the set-2 output from previous module
Set 4 consists of cells, whose outputs control the select inputs of set_5 type cells in set 5, which in turn drive
both the left bus and the right bus. For an set 5-type cell and the 4-b partition to which the cell belongs, bitwise
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comparison outcomes from set 1 provide information about the more significant bits. The number of inputs in
the set 4 type cells increases from left to right in each partition, ending with a fan-in of five. Thus, set 4
determine whether set 5 propagates the bitwise comparison codes or not.
Set 5 performs the functionality of a multiplexer that is it shows whether the bit from the input A is greater
or vice versa set_5 gives 2 bit output. The select control input is based on the set_4 type cell output from set 4.
We define the 2-b as the left-bit code li and the right-bit code ri where all left-bit codes and all right-bit codes
combine to form the left bus and the right bus, respectively. The output F denotes the ―greater-than,‖ ―less-
than,‖ or ―equal to‖ final comparison decision
S5iai = s4i(ai)
S5ibi = s4i(bi)
F =S5iai S5ibi
00, for Ai = Bi
01, for Ai < Bi
10, for Ai > Bi .
Essentially, the 2-b code F can be realized by OR-ing all left bits and all right bits separately, in the decision
module using an OR-gate network.
Figure4: Design of a single module (4-bit) comparator
IV. IMPLEMENTING 128 BIT COMPARATOR IN A SORTER
Sorting is a fundamental operation in which the given sequence of elements is arranged in a specific order.
We see many applications of sorting in our daily life. If we consider a database of students in a college they are
arranged in a sequence either in alphabetical order or roll number wise or date of admission etc., not only in
colleges we can also see the applications of sorting in various scientific fields. The basic element in the sorting
circuit is comparison element. We use a magnitude comparator as a key element in the sorting circuit. The
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comparator compares two elements and produces three outputs greater than, less than and equal to. Based on
these outputs the sorting circuit uses a swapping module so that the elements in the given sequence are sorted in
a desired order.
Figure5: Basic sorting I.O architecture
Figure6: Basic sorting D.O architecture
Bitonic sequence is a sequence that has one monotonic increasing sequence and one monotonic decreasing
sequence. Because of the two monotonic sequences it is called bitonic sequence. Bitonic sorting divides the
given n numbered sequence into two n/2 sequences out of which one is sorted in ascending order and the second
n/2 sequence is sorted in descending order. Whether the increasing order sorting has to be performed first or
decreasing order sorting has to be performed first depends on our sorting order. If at all we have to perform
sorting in an increasing order then the first n/2 sequence is sorted in increasing order and the second n/2
sequence is sorted in the decreasing order. All the elements in the first n/2 sequence will be less than or equal to
the elements in the second n/2 sequence. If at all we have to perform sorting in a decreasing order then the first
n/2 sequence is sorted in decreasing order and the second n/2 sequence is sorted in the increasing order. All the
elements in the first n/2 sequence will be greater than or equal to the elements in the second n/2 sequence. Then
the two n/2 sequences are sorted using merge sort. The bitonic sorting network consists of two key elements.
One is comparator element and the other is swapping element. The comparator compares two elements and
produces three outputs greater than, less than and equal to. Based on these outputs the sorting circuit uses a
swapping module so that the elements in the given sequence are sorted in a desired order.
Figure7: General bitonic sorting module for increasing order sorting
Figure8: General bitonic sorting module for decreasing order sorting
6. 128 Bit Parallel Prefix Tree Structure Comparator
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The general bitonic sorting to sort the elements in increasing order is performed as below
Figure9: Example for ascending order bitonic sorting
The general comparator module used in the sorting is replaced by the 1128 bit parallel prefix tree structure
comparator and is as shown in the figure 10
Figure10: Implementation of comparator in 16 numbered sequence bitonic sorter
V. RESULTS
Figure11: output of the comparator showing all the results a>b, a=b & a<b
7. 128 Bit Parallel Prefix Tree Structure Comparator
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Figure12: RTL for 4 stages of comparator (16 bit)
Figure13: Layout for 128 bit comparator
Figure14: simulation results for bitonic sorter performing 4 types of sorting orders
VI. POWER ANALYSIS
No of bits Leakage
power(µw)
Dynamic
power(mw)
16 0.05 0.03
32 0.1 0.07
48 0.16 0.11
64 0.22 0.14
80 0.27 0.17
96 0.33 0.21
112 0.38 0.25
128 0.44 0.28
Table: 1 power dissipation for various bit comparators
8. 128 Bit Parallel Prefix Tree Structure Comparator
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As the number of bits increases the power dissipated by the comparator architecture increases. The Power
dissipated for various bits of comparators are shown below.
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
16
bit
48
bit
80
bit
112
bit
Leakage power(µw)
Dynamic power(mw)
Figure15: power dissipation for various bits of comparator
VII. CONCLUSION
We have designed 128 bit comparator using parallel prefix tree architecture. This architecture consists of
parallel structure which helps in replicating the design which supports VLSI reconfigurable topology. All the
cells used in this architecture are logic gates which makes use of cmos logic. The comparator dissipates a power
of 0.2mw and has a delay of 0.5ms. By using this 128 bit comparator we designed a sorter that sorts 16 numbers
in four different sorting orders using bitonic sorting method.
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