Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced E...ijceronline
This paper presents an optimized parallel implementation of the MixColumns and SubBytes steps of the Advanced Encryption Standard (AES) algorithm to improve throughput and reduce latency on FPGAs. Specifically, the paper parallelizes the MixColumns operation to process each column simultaneously rather than sequentially, and parallelizes the SubBytes operation to process four bytes simultaneously rather than one byte at a time. The parallel implementations reduce the execution time of the MixColumns and SubBytes steps by 60% and 35% respectively, improving overall throughput compared to the standard serial implementation of AES. Performance comparisons show the parallel designs have higher throughput, lower delay, and moderately higher area usage compared to traditional AES implementations.
Area Efficient and Reduced Pin Count MultipliersCSCJournals
Fully serial multipliers can play an important role in the implementation of DSP algorithms in resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin count and moderate throughput rates. In this paper two structures that implement the fully serial multiplication operation are presented. One significant aspect of the new designs is that they are systolic and require near communication links only. They are superior in speed and area usage to similar architectures in the literature. The paper also present a new fully serial multiplier optimized for area-time2 efficiency with better performance than available architectures in the open literature.
The document proposes a hardware sharing architecture for programmable memory built-in self-test (P-MBIST) to reduce area overhead. A single address generator is used to test multiple memory instances by controlling chip selects. The controller can test different memory types that have the same read/write cycle. Two pipeline stages are added to the address generator to improve test speed. An automation flow generates the P-MBIST design from a user-defined configuration file. The proposed architecture significantly reduces area compared to an individual BIST circuit for each memory type.
An efficient model for design of 64-bit High Speed Parallel Prefix VLSI adderIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced E...ijceronline
This paper presents an optimized parallel implementation of the MixColumns and SubBytes steps of the Advanced Encryption Standard (AES) algorithm to improve throughput and reduce latency on FPGAs. Specifically, the paper parallelizes the MixColumns operation to process each column simultaneously rather than sequentially, and parallelizes the SubBytes operation to process four bytes simultaneously rather than one byte at a time. The parallel implementations reduce the execution time of the MixColumns and SubBytes steps by 60% and 35% respectively, improving overall throughput compared to the standard serial implementation of AES. Performance comparisons show the parallel designs have higher throughput, lower delay, and moderately higher area usage compared to traditional AES implementations.
Area Efficient and Reduced Pin Count MultipliersCSCJournals
Fully serial multipliers can play an important role in the implementation of DSP algorithms in resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin count and moderate throughput rates. In this paper two structures that implement the fully serial multiplication operation are presented. One significant aspect of the new designs is that they are systolic and require near communication links only. They are superior in speed and area usage to similar architectures in the literature. The paper also present a new fully serial multiplier optimized for area-time2 efficiency with better performance than available architectures in the open literature.
The document proposes a hardware sharing architecture for programmable memory built-in self-test (P-MBIST) to reduce area overhead. A single address generator is used to test multiple memory instances by controlling chip selects. The controller can test different memory types that have the same read/write cycle. Two pipeline stages are added to the address generator to improve test speed. An automation flow generates the P-MBIST design from a user-defined configuration file. The proposed architecture significantly reduces area compared to an individual BIST circuit for each memory type.
An efficient model for design of 64-bit High Speed Parallel Prefix VLSI adderIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A high performance fir filter architecture for fixed and reconfigurable appli...Ieee Xpert
A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications
COUPLED FPGA/ASIC IMPLEMENTATION OF ELLIPTIC CURVE CRYPTO-PROCESSORIJNSA Journal
In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
Lec7 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Kar...Hsien-Hsin Sean Lee, Ph.D.
This document provides an overview of Karnaugh maps and their use in simplifying Boolean functions. It defines key concepts like Hamming distance, unit-distance codes, Gray codes, implicants, prime implicants, essential and non-essential prime implicants. Examples are given to show how to identify implicants on a K-map and use them to find a minimum sum-of-products or product-of-sums expression. The use of don't care conditions to simplify expressions is also demonstrated. Finally, it discusses extending K-maps to multiple variables using stacked or composite maps.
Chapter 02 instructions language of the computerBảo Hoang
Here are the steps to translate the MIPS assembly language into machine language:
1. lw $t0,300($t1) # Load A[300] into register $t0
Opcode: 35 (load word)
rs: 13 ($t1)
rt: 8 ($t0)
offset: 300
2. add $t2,$s2,$t0 # Calculate h + A[300] and put in $t2
Opcode: 0 (add)
rs: 17 ($s2)
rt: 8 ($t0)
rd: 9 ($t2)
3. sw $t2,300($t1) # Store result back into
In this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
This paper presents 16 software implementations of the Advanced Encryption Standard (AES) cipher mapped to a fine-grained many-core processor array. The implementations explore different levels of data and task parallelism. The smallest design uses 6 cores for offline key expansion and 8 cores for online expansion, while the largest uses 107 and 137 cores respectively. Compared to other software platforms, the designs achieve 3.5-15.6 times higher throughput per chip area and 8.2-18.1 times higher energy efficiency.
B-splines are polynomial curves used for modeling curves and surfaces. They consist of curve segments whose polynomial coefficients depend on a few control points, allowing for local control of the shape. B-splines provide smooth joins between segments and have higher continuity than other curves like Bezier or Hermite curves. The shape of a B-spline is constrained within the convex hull of its control points. Knots divide the curve into segments and affect the smoothness. Uniform and non-uniform B-splines as well as manipulating knots and control points to control the shape are discussed.
This document discusses various techniques for multi-level and multi-transition line coding as well as block coding. It describes several line coding schemes including mBnL, 2B1Q, 8B6T, and 4D-PAM5 that encode digital data into multi-level signals. It also explains multi-transition coding like MLT-3. Block coding techniques such as 4B/5B, 5B/6B, and 8B/10B are presented which map binary data blocks to larger coded blocks. Scrambling methods including B8ZS and HDB3 are also summarized.
Principles of Combinational Logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions (Don‘t care terms) Simplifying Max term equations
This document summarizes a presentation on fault detection in the Advanced Encryption Standard (AES) algorithm. It begins with an introduction to AES, which is a symmetric key algorithm that operates on 128-bit blocks using 128, 192, or 256-bit keys. It then discusses related work on improving AES performance and fault detection. The proposed system describes the AES algorithm and its transformations in more detail. A fault detection scheme is proposed that calculates parities of blocks in the AES S-box and inverse S-box. Implementation results show the proposed scheme achieves high error coverage for single and multiple faults with low area and delay costs.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
This document discusses a proposed design for secure military communications using AES encryption with Vedic mathematics, OFDM modulation, and QPSK. Specifically, it proposes using AES to encrypt data, applying Vedic math techniques to improve efficiency during the MixColumns step. The encrypted data would then be modulated using OFDM and QPSK to provide high throughput communication. Key aspects of the design include AES encryption/decryption, OFDM using QPSK and an IFFT/FFT, and applying Vedic math during AES encryption to reduce complexity and power consumption for military applications.
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
This document discusses the implementation of AES encryption and decryption using a multiplexer look-up table (MLUT) based substitution box (S-box) on an FPGA to reduce power consumption and increase resistance to side channel attacks. The proposed MLUT S-box uses a 256-byte to 1-byte multiplexer with a 256-byte memory to select pre-computed S-box outputs, making it simpler and lower power than conventional implementations. Simulation results show the MLUT S-box design encrypting and decrypting data correctly while consuming 0.55W of power, three times lower than a conventional S-box. Power analysis also found the MLUT S-box has highly uniform power dissipation for different inputs
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A high performance fir filter architecture for fixed and reconfigurable appli...Ieee Xpert
A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications
COUPLED FPGA/ASIC IMPLEMENTATION OF ELLIPTIC CURVE CRYPTO-PROCESSORIJNSA Journal
In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.
Design and Implementation of High Speed Area Efficient Double Precision Float...IOSR Journals
The document describes the design and implementation of a high-speed, area-efficient double precision floating point arithmetic unit. It includes modules for addition, subtraction, multiplication, and division. The unit operates on 64-bit operands adhering to the IEEE 754 double precision format. It was designed using Verilog, simulated using Questa Sim, and implemented on a Xilinx Vertex-5 FPGA. Synthesis results showed it utilized 16% slice registers and 22% LUTs, operating at a maximum frequency of 262.006MHz. Simulation showed addition and subtraction took 57.3ns while multiplication took 57.3ns and division took 259.76ns to complete.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
This document summarizes research on improving the performance of multiplier and accumulator (MAC) circuits used in digital signal processing. It presents four architectures for carry-select adders (CSLA) that can be used in MACs: 1) a regular CSLA, 2) a CSLA that replaces full adders with binary-to-excess converters (BEC) to reduce area, 3) a CSLA that uses D-latches to store intermediate values and reduce the number of adders, and 4) a modified CSLA architecture. The document analyzes the delay and area of each group of bits for the different CSLA architectures. It finds that BEC and D-latch based C
Lec7 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Kar...Hsien-Hsin Sean Lee, Ph.D.
This document provides an overview of Karnaugh maps and their use in simplifying Boolean functions. It defines key concepts like Hamming distance, unit-distance codes, Gray codes, implicants, prime implicants, essential and non-essential prime implicants. Examples are given to show how to identify implicants on a K-map and use them to find a minimum sum-of-products or product-of-sums expression. The use of don't care conditions to simplify expressions is also demonstrated. Finally, it discusses extending K-maps to multiple variables using stacked or composite maps.
Chapter 02 instructions language of the computerBảo Hoang
Here are the steps to translate the MIPS assembly language into machine language:
1. lw $t0,300($t1) # Load A[300] into register $t0
Opcode: 35 (load word)
rs: 13 ($t1)
rt: 8 ($t0)
offset: 300
2. add $t2,$s2,$t0 # Calculate h + A[300] and put in $t2
Opcode: 0 (add)
rs: 17 ($s2)
rt: 8 ($t0)
rd: 9 ($t2)
3. sw $t2,300($t1) # Store result back into
In this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV.
The document presents a new reversible logic gate called BBCDC (Binary to BCD conversion) and a more effective realization of a BCD adder circuit using the proposed BBCDC gate. The BBCDC is a 5x5 reversible gate that converts binary numbers to BCD format. The proposed BCD adder uses DKFG reversible gates for addition and the BBCDC gate for binary to BCD conversion. A comparison shows the proposed design uses fewer gates and garbage outputs than existing BCD adder designs. The efficient design of the BCD adder depends on the reversible ripple carry adder and the reversible binary to BCD converter used.
This paper presents 16 software implementations of the Advanced Encryption Standard (AES) cipher mapped to a fine-grained many-core processor array. The implementations explore different levels of data and task parallelism. The smallest design uses 6 cores for offline key expansion and 8 cores for online expansion, while the largest uses 107 and 137 cores respectively. Compared to other software platforms, the designs achieve 3.5-15.6 times higher throughput per chip area and 8.2-18.1 times higher energy efficiency.
B-splines are polynomial curves used for modeling curves and surfaces. They consist of curve segments whose polynomial coefficients depend on a few control points, allowing for local control of the shape. B-splines provide smooth joins between segments and have higher continuity than other curves like Bezier or Hermite curves. The shape of a B-spline is constrained within the convex hull of its control points. Knots divide the curve into segments and affect the smoothness. Uniform and non-uniform B-splines as well as manipulating knots and control points to control the shape are discussed.
This document discusses various techniques for multi-level and multi-transition line coding as well as block coding. It describes several line coding schemes including mBnL, 2B1Q, 8B6T, and 4D-PAM5 that encode digital data into multi-level signals. It also explains multi-transition coding like MLT-3. Block coding techniques such as 4B/5B, 5B/6B, and 8B/10B are presented which map binary data blocks to larger coded blocks. Scrambling methods including B8ZS and HDB3 are also summarized.
Principles of Combinational Logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions (Don‘t care terms) Simplifying Max term equations
This document summarizes a presentation on fault detection in the Advanced Encryption Standard (AES) algorithm. It begins with an introduction to AES, which is a symmetric key algorithm that operates on 128-bit blocks using 128, 192, or 256-bit keys. It then discusses related work on improving AES performance and fault detection. The proposed system describes the AES algorithm and its transformations in more detail. A fault detection scheme is proposed that calculates parities of blocks in the AES S-box and inverse S-box. Implementation results show the proposed scheme achieves high error coverage for single and multiple faults with low area and delay costs.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
This document discusses a proposed design for secure military communications using AES encryption with Vedic mathematics, OFDM modulation, and QPSK. Specifically, it proposes using AES to encrypt data, applying Vedic math techniques to improve efficiency during the MixColumns step. The encrypted data would then be modulated using OFDM and QPSK to provide high throughput communication. Key aspects of the design include AES encryption/decryption, OFDM using QPSK and an IFFT/FFT, and applying Vedic math during AES encryption to reduce complexity and power consumption for military applications.
Low cost high-performance vlsi architecture for montgomery modular multiplica...Ratnakar Varun
This document discusses VLSI implementation of Montgomery modular multiplication for cryptographic applications. It proposes a configurable carry-save adder architecture to reduce the number of clock cycles needed for Montgomery multiplication. The architecture can perform either one three-input carry-save addition or two serial two-input carry-save additions. It also discusses the Advanced Encryption Standard (AES) algorithm for encryption and decryption. AES is based on substitution-permutation networks and involves key expansion, initial/final rounds, and intermediate rounds of sub bytes, shift rows, mix columns and add round key transformations.
Implementation and Design of AES S-Box on FPGAIJRES Journal
The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Xilinx Design Suite 14.5 software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions is simulated using an iterative design approach in order to minimize the hardware consumption. Virtex 6 Family devices are utilized for hardware evaluation. Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. Theoretically, the design reduces the overall delay and efficiently for applications with high-speed performance. This approach is suitable for FPGA implementation in term of gate area. The hardware, total area and delay are presented.
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
This document summarizes a research paper that proposes implementing the Advanced Encryption Standard (AES) cryptographic algorithm using Verilog HDL for hardware implementation on FPGAs. The paper describes the AES algorithm, its encryption and decryption processes, and a hardware design for AES that was tested on a Xilinx FPGA. The results showed the hardware implementation utilized less resources and had lower power consumption compared to other AES FPGA designs.
This document proposes and evaluates several designs for implementing the AES encryption algorithm in hardware. It presents new composite field constructions for the AES S-box that improve on prior work in terms of implementation area and speed. It also introduces a novel fault-tolerant AES model that incorporates Hamming error correction codes to detect and correct single event upsets, making it suitable for use in space-based applications. The designs are implemented on an FPGA and evaluation shows improvements in area requirements, timing, and power consumption compared to previous implementations.
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
FPGA Implementation of an Area Optimized Architecture for 128 bit AES AlgorithmIJERA Editor
This paper aims at FPGA Implementation of an Area Optimized Architecture for 128 bit AES Algorithm. The
conventional designs use a separate module for 32 bit byte substitution and 128 bit byte substitution. The 32 bit
byte substitution is used in round key generation and the 128 bit byte substitution is used in the rounds. This
report presents a modified architecture of 128 bit byte substitution module using a single 32 bit byte substitution
module to reduce area.The AES encryption and decryption algorithm were designed using Verilog HDL. The
functionality of the modules were checked using ModelSim. The simulations were carried out in ModelSim and
Quartus II. The algorithm was implemented in FPGA and achieved a 2% reduction in the total logic element
utilization
Aes encryption engine for many core processor arrays for enhanced securityIAEME Publication
This document describes two implementations of an Advanced Encryption Standard (AES) cipher with online key expansion mapped to a fine-grained many-core system. The first implementation, called "One Task One Processor", maps each step of the AES algorithm to a separate processor. The second implementation unrolls the AES algorithm loop nine times to break data dependencies and process multiple data blocks in parallel using about 60 cores. Evaluation on an FPGA shows the unrolled implementation achieves a throughput of 85.15 Gbps compared to 1.98 Gbps for the single-task implementation. The document also proposes a masked S-box technique to protect AES implementations from differential power analysis attacks.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
DUAL FIELD DUAL CORE SECURE CRYPTOPROCESSOR ON FPGA PLATFORMVLSICS Design
This paper is devoted to the design of dual core crypto processor for executing both Prime field and binary field instructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform. Combination of two different field (prime field GF(p) and Binary field GF(2m)) instructions execution is analysed.The design is implemented in Spartan 3E and virtex5. Both the performance results are compared. The implementation result shows the execution of parallelism using dual field instructions
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial
applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.
Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural
properties. The AES architecture with the enhanced mix column to be proposed with reduced number of
transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES
Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS
technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding
the VLSI design environment. The simulation results of the proposed structure are performed with the
minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS
technology based AES Algorithm is integrated into the backend based chip technology.
VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document summarizes a lecture on the Advanced Encryption Standard (AES). It describes the origins and requirements for AES as the successor to the Data Encryption Standard (DES). The Rijndael cipher was selected as AES in 2000. Rijndael has four stages in each round: Substitute Bytes, Shift Rows, Mix Columns, and Add Round Key. Substitute Bytes uses a lookup table, Shift Rows shifts bytes within rows, Mix Columns mixes bytes mathematically, and Add Round Key XORs the state with the round key. The cipher has 10 rounds for 128-bit keys and security.
This document provides an overview of the Advanced Encryption Standard (AES). It discusses the origins and requirements for AES, the evaluation criteria used in selecting Rijndael as the cipher, and the structure and key components of the Rijndael cipher. The Rijndael cipher operates on data in rounds that include byte substitution, shifting rows, mixing columns, and adding a round key. The cipher text is produced after 9 to 13 rounds depending on the key size.
The document summarizes a lecture on the Advanced Encryption Standard (AES). AES was selected by the National Institute of Standards and Technology (NIST) in 2001 to replace the Data Encryption Standard (DES). AES is a symmetric block cipher that uses 128-bit blocks and 128/192/256-bit keys. The AES algorithm is based on Rijndael, designed by Joan Daemen and Vincent Rijmen. Rijndael uses a series of transformations including byte substitution, shifting rows of the state array, mixing data within columns, and combining the state array with the round key. These transformations are repeated over 10-14 rounds depending on the key size. The algorithm was chosen for its security, performance,
Similar to CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES (20)
This document summarizes a research paper that proposes using an artificial neural network tuned by a simulated annealing algorithm for real-time credit card fraud detection. The paper describes how simulated annealing can be used to train the weights of a neural network model to classify credit card transactions as fraudulent or non-fraudulent based on attributes of past transactions. The algorithm is tested on a real-world credit card transaction dataset and is found to effectively classify most transactions correctly, though some misclassifications still occur.
Wireless sensor networks (WSN) have been widely used in various applications.
In these networks nodes collect data from the attached sensors and send their data to a base
station. However, nodes in WSN have limited power supply in form of battery so the nodes
are expected to minimize energy consumption in order to maximize the lifetime of WSN. A
number of techniques have been proposed in the literature to reduce the energy
consumption significantly. In this paper, we propose a new clustering based technique
which is a modification of the popular LEACH algorithm. In this technique, first cluster
heads are elected using the improved LEACH algorithm as usual, and then a cluster of
nodes is formed based on the distance between node and cluster head. Finally, data from
node is transferred to cluster head. Cluster heads forward data, after applying aggregation,
to the cluster head that is closer to it than sink in forward direction or directly to the sink.
This reduction in distance travelled improves the performance over LEACH algorithm
significantly.
This document provides an overview of vertical handover decision strategies in heterogeneous wireless networks. It begins with an introduction to always best connectivity requirements in next generation networks that allow users to move between different network technologies. It then discusses the key aspects of handover management, including the three phases of initiation, decision, and execution. Various criteria for the handover decision process are described, such as received signal strength, network connection time, available bandwidth, power consumption, cost, security, and user preferences. Different types of handover decision strategies are categorized, including those based on network conditions, user preferences, multiple attributes, fuzzy logic/neural networks, and context awareness. The strategies are analyzed and their advantages/disadvantages compared.
This paper presents the design and performance comparison of a two stage
operational amplifier topology using CMOS and BiCMOS technology. This conventional op
amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and
0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated,
analyzed and performance parameters are compared. The performance parameters such as
gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally,
we conclude the suitability of CMOS technology over BiCMOS technology for low power
RF design.
In Cognitive Radio Networks (CRN), Cooperative Spectrum Sensing (CSS) is
used to improve performance of spectrum sensing techniques used for detection of licensed
(Primary) user’s signal. In CSS, the spectrum sensing information from multiple unlicensed
(Secondary) users are combined to take final decision about presence of primary signal. The
mixing techniques used to generate final decision about presence of PU’s signal are also
called as Fusion techniques / rules. The fusion techniques are further classified as data
fusion and decision fusion techniques. In data fusion technique all the secondary users
(SUs) share their raw information of spectrum detection like detected energy or other
statistical information, while in decision fusion technique all the SUs take their local
decisions and share the decision by sending ‘0’ or ‘1’ corresponding to absence and presence
of PU’s signal respectively. The rules used in decision fusion techniques are OR rule, AND
rule and K-out-of-N rule. The CSS is further classified as distributed CSS and centralized
CSS. In distributed CSS all the SUs share the spectrum detection information with each
other and by mixing the shared information; all the SUs take final decision individually. In
centralized CSS all the SUs send their detected information to a secondary base station /
central unit which combines the shared information and takes final decision. The secondary
base station shares the final decision with all the SUs in the CRN. This paper covers
overview of information fusion methods used for CSS and analysis of decision fusion rules
with simulation results.
This paper analyzes the impact of network scalability on various physical attributes of Zigbee networks. Simulations were conducted using Qualnet to evaluate the performance of the Zigbee physical layer based on energy consumption and throughput. Energy consumption was analyzed for different modulation schemes (ASK, BPSK, OQPSK), network sizes (2-50 nodes), and clear channel assessment modes. The results showed that OQPSK and ASK had lower energy consumption than BPSK. Throughput was highest for OQPSK. While carrier sense had slightly higher throughput than other CCA modes, the energy consumption differences between CCA modes were minor.
This paper gives a brief idea of the moving objects tracking and its application.
In sport it is challenging to track and detect motion of players in video frames. Task
represents optical flow analysis to do motion detection and particle filter to track players
and taking consideration of regions with movement of players in sports video. Optical flow
vector calculation gives motion of players in video frame. This paper presents improved
Luacs Kanade algorithm explained for optical flow computation for large displacement and
more accuracy in motion estimation.
A rapid progress is seen in the field of robotics both in educational and industrial
automation sectors. The Robotics education in particular is gaining technological advances
and providing more learning opportunities. In automotive sector, there is a necessity and
demand to automate daily human activities by robot. With such an advancement and
demand for robotics, the realization of a popular computer game will help students to learn
and acquire skills in the field of robotics. The computer game such as Pacman offers
challenges on both software and hardware fronts. In software, it provides challenges in
developing algorithms for a robot to escape from the pool of attacking robots and to develop
algorithms for multiple ghost robots to attack the Pacman. On the hardware front, it
provides a challenge to integrate various systems to realize the game. This project aims to
demonstrate the pacman game in real world as well as in simulation. For simulation
purpose Player/Stage is used to develop single-client and multi-client architectures. The
multi- client architecture in player/stage uses one global simulation proxy to which all the
robot models are connected. This reduces the overhead to manage multiple robots proxy.
The single-client architecture enables only two robot models to connect to the simulation
proxy. Multi-client approach offers flexibility to add sensors to each port which will be used
distinctly by the client attached to the respective robot. The robots are named as Pacman
and Ghosts, which try to escape and attack respectively. Use of Network Camera has been
done to detect the global positions of the robots and data is shared through inter-process
communication.
In Content-Based Image Retrieval (CBIR) systems, the visual contents of the
images in the database are took out and represented by multi-dimensional characteristic
vectors. A well known CBIR system that retrieves images by unsupervised method known
as cluster based image retrieval system. For enhancing the performance and retrieval rate
of CBIR system, we fuse the visual contents of an image. Recently, we developed two
cluster-based CBIR systems by fusing the scores of two visual contents of an image. In this
paper, we analyzed the performance of the two recommended CBIR systems at different
levels of precision using images of varying sizes and resolutions. We also compared the
performance of the recommended systems with that of the other two existing CBIR systems
namely UFM and CLUE. Experimentally, we find that the recommended systems
outperform the other two existing systems and one recommended system also comparatively
performed better in every resolution of image.
Information Systems and Networks are subjected to electronic attacks. When
network attacks hit, organizations are thrown into crisis mode. From the IT department to
call centers, to the board room and beyond, all are fraught with danger until the situation is
under control. Traditional methods which are used to overcome these threats (e.g. firewall,
antivirus software, password protection etc.) do not provide complete security to the system.
This encourages the researchers to develop an Intrusion Detection System which is capable
of detecting and responding to such events. This review paper presents a comprehensive
study of Genetic Algorithm (GA) based Intrusion Detection System (IDS). It provides a
brief overview of rule-based IDS, elaborates the implementation issues of Genetic Algorithm
and also presents a comparative analysis of existing studies.
Step by step operations by which we make a group of objects in which attributes
of all the objects are nearly similar, known as clustering. So, a cluster is a collection of
objects that acquire nearly same attribute values. The property of an object in a cluster is
similar to other objects in same cluster but different with objects of other clusters.
Clustering is used in wide range of applications like pattern recognition, image processing,
data analysis, machine learning etc. Nowadays, more attention has been put on categorical
data rather than numerical data. Where, the range of numerical attributes organizes in a
class like small, medium, high, and so on. There is wide range of algorithm that used to
make clusters of given categorical data. Our approach is to enhance the working on well-
known clustering algorithm k-modes to improve accuracy of algorithm. We proposed a new
approach named “High Accuracy Clustering Algorithm for Categorical datasets”.
Brain tumor is a malformed growth of cells within brain which may be
cancerous or non-cancerous. The term ‘malformed’ indicates the existence of tumor. The
tumor may be benign or malignant and it needs medical support for further classification.
Brain tumor must be detected, diagnosed and evaluated in earliest stage. The medical
problems become grave if tumor is detected at the later stage. Out of various technologies
available for diagnosis of brain tumor, MRI is the preferred technology which enables the
diagnosis and evaluation of brain tumor. The current work presents various clustering
techniques that are employed to detect brain tumor. The classification involves classification
of images into normal and malformed (if detected the tumor). The algorithm deals with
steps such as preprocessing, segmentation, feature extraction and classification of MR brain
images. Finally, the confirmatory step is specifying the tumor area by technique called
region of interest.
A Proxy signature scheme enables a proxy signer to sign a message on behalf of
the original signer. In this paper, we propose ECDLP based solution for chen et. al [1]
scheme. We describe efficient and secure Proxy multi signature scheme that satisfy all the
proxy requirements and require only elliptic curve multiplication and elliptic curve addition
which needs less computation overhead compared to modular exponentiations also our
scheme is withstand against original signer forgery and public key substitution attack.
This document proposes a digital watermarking technique using LSB replacement with secret key insertion for enhanced data security. The technique works by inserting a watermark into the least significant bits of pixels in an image. A secret key is also inserted during transmission for additional security. The watermarked image is generated without noticeably impacting image quality. The proposed method was tested on sample images and successfully embedded watermarks while maintaining visual quality. The technique aims to provide copyright protection and authentication of digital images and documents.
Today among various medium of data transmission or storage our sensitive data
are not secured with a third-party, that we used to take help of. Cryptography plays an
important role in securing our data from malicious attack. This paper present a partial
image encryption based on bit-planes permutation using Peter De Jong chaotic map for
secure image transmission and storage. The proposed partial image encryption is a raw data
encryption method where bits of some bit-planes are shuffled among other bit-planes based
on chaotic maps proposed by Peter De Jong. By using the chaotic behavior of the Peter De
Jong map the position of all the bit-planes are permuted. The result of the several
experimental, correlation analysis and sensitivity test shows that the proposed image
encryption scheme provides an efficient and secure way for real-time image encryption and
decryption.
This paper presents a survey of Dependency Analysis of Service Oriented
Architecture (SOA) based systems. SOA presents newer aspects of dependency analysis due
to its different architectural style and programming paradigm. This paper surveys the
previous work taken on dependency analysis of service oriented systems. This study shows
the strengths and weaknesses of current approaches and tools available for dependency
analysis task in context of SOA. The main motivation of this work is to summarize the
recent approaches in this field of research, identify major issue and challenges in
dependency analysis of SOA based systems and motivate further research on this topic.
In this paper, proposed a novel implementation of a Soft-Core system using
micro-blaze processor with virtex-5 FPGA. Till now Hard-Core processors are used in
FPGA processor cores. Hard cores are a fixed gate-level IP functions within the FPGA
fabrics. Now the proposed processor is Soft-Core Processor, this is a microprocessor fully
described in software, usually in an HDL. This can be implemented by using EDK tool. In
this paper, developed a system which is having a micro-blaze processor is the combination
of both hardware & Software. By using this system, user can control and communicate all
the peripherals which are in the supported board by using Xilinx platform to develop an
embedded system. Implementing of Soft-Core process system with different peripherals like
UART interface, SPA flash interface, SRAM interface has to be designed using Xilinx
Embedded Development Kit (EDK) tools.
The article presents a simple algorithm to construct minimum spanning tree and
to find shortest path between pair of vertices in a graph. Our illustration includes the proof
of termination. The complexity analysis and simulation results have also been included.
Wimax technology has reshaped the framework of broadband wireless internet
service. It provides the internet service to unconnected or detached areas such as east South
Africa, rural areas of America and Asia region. Full duplex helpers employed with one of
the relay stations selection and indexing method that is Randomized Distributed Space Time
are used to expand the coverage area of primary Wimax station. The basic problem was
identified at cell edge due to weather conditions (rain, fog), insertion of destruction because
of multiple paths in the same communication channel and due to interference created by
other users in that communication. It is impractical task for the receiver station to decode
the transmitted signal successfully at the cell edges, which increases the high packet loss and
retransmissions. But Wimax is a outstanding technology which is used for improving the
quality of internet service and also it offers various services like Voice over Internet
Protocol, Video conferencing and Multimedia broadcast etc where a little delay in packet
transmission can cause a big loss in the communication. Even setup and initialization of
another Wimax station nearer to each other is not a good alternate, where any mobile
station can easily handover to another base station if it gets a strong signal from other one.
But in rural areas, for few numbers of customers, installation of base station nearer to each
other is costlier task. In this review article, we present a scheme using R-DSTC technique to
choose and select helpers (relay nodes) randomly to expand the coverage area and help to
mobile station as a helper to provide secure communication with base station. In this work,
we use full duplex helpers for better utilization of bandwidth.
Radio Frequency identification (RFID) technology has become emerging
technique for tracking and items identification. Depend upon the function; various RFID
technologies could be used. Drawback of passive RFID technology, associated to the range
of reading tags and assurance in difficult environmental condition, puts boundaries on
performance in the real life situation [1]. To improve the range of reading tags and
assurance, we consider implementing active backscattering tag technology. For making
mobiles of multiple radio standards in 4G network; the Software Defined Radio (SDR)
technology is used. Restrictions in Existing RFID technologies and SDR technology, can be
eliminated by the development and implementation of the Software Defined Radio (SDR)
active backscattering tag compatible with the EPC global UHF Class 1 Generation 2 (Gen2)
RFID standard. Such technology can be used for many of applications and services.
Leveraging Generative AI to Drive Nonprofit InnovationTechSoup
In this webinar, participants learned how to utilize Generative AI to streamline operations and elevate member engagement. Amazon Web Service experts provided a customer specific use cases and dived into low/no-code tools that are quick and easy to deploy through Amazon Web Service (AWS.)
How Barcodes Can Be Leveraged Within Odoo 17Celine George
In this presentation, we will explore how barcodes can be leveraged within Odoo 17 to streamline our manufacturing processes. We will cover the configuration steps, how to utilize barcodes in different manufacturing scenarios, and the overall benefits of implementing this technology.
Level 3 NCEA - NZ: A Nation In the Making 1872 - 1900 SML.pptHenry Hollis
The History of NZ 1870-1900.
Making of a Nation.
From the NZ Wars to Liberals,
Richard Seddon, George Grey,
Social Laboratory, New Zealand,
Confiscations, Kotahitanga, Kingitanga, Parliament, Suffrage, Repudiation, Economic Change, Agriculture, Gold Mining, Timber, Flax, Sheep, Dairying,
Gender and Mental Health - Counselling and Family Therapy Applications and In...PsychoTech Services
A proprietary approach developed by bringing together the best of learning theories from Psychology, design principles from the world of visualization, and pedagogical methods from over a decade of training experience, that enables you to: Learn better, faster!
2. (FPGA), which utilized an 8-bit data path for AES. The schemes in [5-8] present suitable structure of CFA
for the S-box and inverse S-box implementation In this paper, an area efficient, low power AES design using
8-bit data path is explained for the implementation of the AES, which provides significant improvements
over the previous AES designs. This design utilizes an 8-bit data path between key and state processing, with
resource sharing of the SubByte operation.
The remainder of this paper is organized as follows. In section II, AES S-box and inverse S-box using CFA
are explained. Section III explains the design of 8 bit data path AES using CFA. The results and discussions
are given in Section IV. The paper ends by drawing some conclusions in Section V.
II. AES S-BOX AND INVERSE S-BOX USING CFA
Generally, Sbox and Inverse Sbox are implemented using LUTs as they are predefined and precomputed
values. But this technique occupies more area. Hence a Composite Field Arithmetic (CFA) based
implementation is used to reduce area.
In this section, we describe the S-box and inverse S-box operations and their composite field realizations.
The S-box and inverse S-box are nonlinear operations which take 8-bit as input and generate 8-bit as outputs.
In the S-box, the irreducible polynomial of P (x) = x8 + x4+x3+x+1 is used to construct the Galois field GF
(28). The S-box consists of the multiplicative inversion, followed by an affine transformation[1]. The inverse
S-box consists of an inverse affine transformation followed by multiplicative inversion. The composite fields
can be represented by using normal basis or polynomial basis. The S-box and inverse S-box for using
composite fields and polynomial basis are shown in Fig 1. The block 1 consists of transformation matrix and
modulo addition operation, block 2 consists of squarer, scaling, modulo multiplication and modulo addition
operations, block 3 consists of multiplicative inversion, block 4 consists of multiplication operations and
block 5 consists of mixed inverse and affine transformations as in Fig 1 [9]. As in figure, for the S-box, the
transformation matrix transforms a field element X in the binary field GF (28) to the corresponding
representation in the composite fields GF (28) or GF (24).
Fig 1 The S-box (the inverse S-box) using composite field arithmetic (CFA) and polynomial basis
Let yl and yh are the field elements in the sub field GF(24). The decomposition can be further applied to
represent GF (24) as a linear polynomial over GF (22) and then the GF (2). The multiplicative inversion
consists of multiplications the modulo-2 additions, squaring and an inversion in the sub-field GF (24) over
GF (2). The implementation of inversion in GF (2 4) is shown below in Fig 2. The Fig 2.(a) shows square
multiply approach and Fig 2.(b) shows multiple decomposition approach. In Fig. 1, the modulo-2 additions,
consisting of four XOR gates, are shown by two concentric circles with a plus inside. Furthermore, the
multiplication operations in GF (24) are shown by rectangles with crosses inside. It is also noted that the
implementation of the multiplicative inversion can be performed using the field represented by GF ((24)) 2 or
the field represented by GF (((22)) 2)2. After calculating the inversion in the composite field, affine
transformation is used to transform the composite field representation to the field element Y [4]. Also the
individual blocks in the S-box architecture is shown in Fig 3.
20
3. III. 8 BIT DATA PATH AES DESIGN
The aim of this design is to minimize the performance dimensions power, area and latency. Such
minimization is achieved by the use of appropriate resource sharing, simple compact memory architecture,
field arithmetic optimization, avoiding unnecessary switching activity, adopting an 8-bit data path width, and
minimizing memory transfer. Typically, CMOS power consumption is usually dominated by the dynamic
power consumption from the switching activity of the device, and the static power is neglected. In previous
AES papers [3] frequently uses generate much unwanted dynamic switching activity due to path length
differences.
Fig 2 Implementation of inversion in GF(24) (a) square multiply approach (b) multiple decomposition approach
In this design, this is checked by the placement of the shift register between the SubBytes and MixColumns
operators together with the clock-gate-style enabled signals to prevent unwanted activity in both Key
Expansion and state-processing parts of the data path.
In this design first the key is fed into the key memory. Next, as the plaintext is supplied, the first AES round
is processed (simply Add Round Key), and the results are stored in the data memory. The middle round
processing proceeds in column order. The final round is same as the middle rounds in AES except that Mix
Columns is bypassed and the result bytes are stored in the output register. In this design, two 16 byte
memories are used for storing 128 bits of data and key. First memory is for the Round Key and the second for
the state.
Fig 3 Implementation of individual blocks in CFA: (a) multiplier in GF (24 ) (b) multiplier in GF (22 ) (c) squarer in GF (24)
(d), (e) constant multiplier
The block diagram of 8-bit data path AES encryption is shown in Fig 4. This involves both key expansion
and Encryption, both are taking place simultaneously. AES defines a 16×16 matrix of byte values, called an
S-box. The S-box and inverse S-box can be implemented using either look up table (LUT) or CFA. Initially
S-box and the inverse S - box is implemented by LUT approach. But this approach may not be preferable for
21
4. high performance AES implementations because, it requires a large number of registers for storing the 256
bytes. Therefore AES has been also implemented by replacing the LUT approach with CFA, which is shown
in Section II. This reduces the number of registers in LUT approach. Shift Rows essentially consist of
shifting the bytes in the row. It is a transposition step on the row of the state where each row of the state is
shifted cyclically by a certain number of steps. The MixColumns takes four bytes as input and output as four
bytes, where each input byte affects all four output bytes. Together with ShiftRows, MixColumn
transformations provides diffusion in the AES cipher. Each column is considered as a polynomial over GF
(28) and is then multiplied modulo x4 + 1 with a fixed polynomial
c(x) = {03} x3 + {01} x2 + {01} x+
{02}. In AddRoundKey transformation, different round keys are added to the state by a simple bit wise XOR
operation. Similarly decryption involves inverse transformations of encryption.
In this 8 bit data path AES design, a low- resource MixColumn circuit in Fig. 5 is used instead of direct
matrix multiplication with a known matrix in normal AES implementations, which reduces the area and
power. At the 8-bit level, MixColumn is challenging as it is mathematically equivalent to 32-bit operation.
This is defined to operate on a column in term of summations of a number of finite-field multiplications. In
8-bit AES design, this operation is
Fig. 4 Block diagram of 8 bit data path AES Encryption
simplified to a series of finite-field doubling f2, tripling f3, and XOR operations as in Fig. 5. As shown in [7],
this can be done using a sequence of 8-bit operations; however, this requires 12 cycles for each 32-bit
MixColumn operation. A compromise [8] is to use a shift register supplied with 8-bit and perform a 32-bit in,
32-bit out version of MixColumn, and cycle the data to provide the 32-bit operation.
IV. RESULTS
The design of 8 bit data path AES encryption, decryption and a Low resource MixColumn is coded in VHDL
Language and simulated using ModelSim 6.5. The 8 bit data path AES provides low power and low area
compared to 128 bit data path AES cipher. Encryption takes 128 bits as input and output with key length of
128 bits, whereas the internal operations taking place as 8 bit data path. After completing the 10 rounds,
cipher text is obtained as the output. AES cipher involves both encryption and decryption. The mode is used
for selecting the encryption and decryption operations. When mode = 1, encryption occurs and ciphertext is
obtained as input. When mode = 0, decryption occurs and plain text is obtained as the output. Fig. 6 shows
22
5. 8 bit data path encryption decryption combined AES Cipher waveform using CFA and low resource
mixcolumn. The device used was Virtex 6.
Fig 5 Low Resource MixColumn Circuit
Fig. 6 8 bit AES cipher waveform using CFA
Next graphs show the FPGA performance comparison between 128 bit and 8 bit data path AES cipher.Fig. 7
shows the area comparison between 128 bit and 8 bit data path AES cipher. The 8-bit data path AES uses less
number of RAMs, Registers, Multiplexers and XORs, thus it reduces the area as compared to 128-bit data
path AES. Fig. 8 shows the clock cycles for both 128-bit and 8-bit data path AES cipher. The number of
clock cycles for 8 bit data path AES encryption and decryption is less compared to 128 bit data path AES
encryption and decryption. Fig 9 gives the area comparison between AES using LUT and AES using CFA
cipher. The AES cipher using CFA reduces the use RAMs in LUT implementation by increasing the XOR
operations.
23
6. Table 1 shows the ASIC performance comparison between 8 bit data path AES architecture using CFA and
low resource mixcoulmn with the existing architectures. SYNOPSYS software was used to determine the
power and area. 90 nm technology was used and compared with the results available in literature.
Fig. 7 Area comparison between 128 and 8 bit data path AES
Fig. 8 Comparison between clock cycles in 128 and
8 bit bit data path AES
Fig.9 Area comparison between 8 bit data path AES using
LUT and CFA
V. Conclusion
This paper presents the FPGA and ASIC implementation of low power and low area for the AES cipher using
8 bit data path. The S-box and inverse S-box can be implemented using either look up table (LUT) or CFA.
Initially S-box and the inverse S - box is implemented by LUT approach. But this approach may not be
preferable for high performance AES implementations because, it requires a large number of registers for
storing the 256 bytes. So the modification has been implemented by replacing the LUT approach with CFA.
This reduces the number of registers in LUT approach. Also a low resource MixColumn circuit is used for
reducing the resources and thus improves performance of 8 bit data path AES. The 8 bit data path Design for
Advanced Encryption Standard (AES) is coded in Very High Speed Integrated Circuit Hardware Description
Language (VHDL). The synthesis is done by Xilinx ISE 13.2i and simulation is performed by ModelSim XE
III 6.3 simulator. The device Virtex 7 XC7V585TL is targeted device for FPGA implementation. The FPGA
implementation of 8 bit data path AES using CFA gives the power consumption of 554 mw for 8 bit data
path AES architecture. The ASIC implementation of the proposed 8 bit data path AES architecture using
CFA achieves power of 693.35 uW and an area of 28276 nm2 using the above area and power reduction
techniques. This proves that the 8 bit data path AES architecture using CFA reduces the power and area than
all existing architectures. Compared to existing designs, this shows the best P-A-L (power, area, latency)
efficiency. It is hoped that this low resource design for AES will open up new opportunities for the AES in
24
7. resource- sensitive applications. This design focuses on power, area and latency and not on the speed. Hence,
the future work can be concentrated on the speed, since the speed is essential for the real time applications.
TABLE 1 ASIC PERFORMANCE COMPARISON OF 8 BIT DATA PATH AES ARCHITECTURE USING CFA WITH THE EXISTING
ARCHITECTURE
AUTHOR
ARCHITECTURE
TECHNOLOGY
POWER
AREA
S.Y. Lin (2007)
NORMAL AES [10]
0.13 um
40.9 mw
86.2 K gates
Al Wen Luo et.al (2011)
PIPELINED AES [11]
0.18 um
14.025mW
52131.166um
square
Alma’aitah. A (2010)
SUBPIPELINED AES [12]
0.18um
84.6mW
-
Choi.H.S (2008)
PARALLEL AES [13]
0.90um
7.56mW
-
This Work
8 BIT DATA PATH AES
USING LUT
0.90um
1628.91uW
70178nm square
This Work
8 BIT DATA PATH AES
USING CFA
0.90um
693.35uW
28276 nm
square
REFERENCES
[1] Nat. Inst. Standards Technol. (NIST), 2001 “Federal Information Processing Standards (FIPS) Publication 197,”
Advanced Encryption Standard, Nov. 2001.
[2] Avi kak “AES: The Advanced Encryption Standard” Lecture Notes on “Computer and Network Security”, Feb 26,
2013.
[3] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijndael hardware architecture with S-box
optimization,” in Proc. ASIACRYPT, Gold Coast, Qld., Australia, Dec. 2001.
[4] H. Kuo, I. Verbauwhede, and P. Schaumont, “A 2.29 Gbits/Sec, 56Mw non-pipelined Rijndael AES encryption IC in
a 1.8 V 0.18 um CMOS technology,” in Proc. CICC, Orlando, FL, pp. 147–150, 2002.
[5] Tim Good and Mohammed Benaissa “692-nW Advanced Encryption Standard (AES) on a 0.13- m CMOS” in IEEE
Transactions on Very Large Scale Integration (VLSI) systems, vol. 18, no. 12, December 2010.
[6] M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, “AES implementation on a grain of sand,” Proc. Inst. Electr. Eng. Inf.
Security, vol. 1, pp. 13–20, 2005.
[7] D. Canright, “A very compact S-box for AES,” in Proc. CHES Edinburgh, U.K. Vol. 3659, LNCS, pp. 441–456,
2005
[8] C. Paar, “Efficient VLSI architectures for bit-parallel computation in Galois fields,,” Ph.D. dissertation, Inst. Exp.
Math., Univ. Essen, Essen, Germany, Jun. 1994.
[9] Xinmiao Zhang, Member, Keshab K. Parhi, “On the Optimum Constructions of Composite Field for the AES
Algorithm”, IEEE Transactions on circuits and systems II: express briefs, vol. 53, no. 10, October 2006.
[10] S.Y. Lin and C.T. Huang, “A high-throughput low-power AES cipher for network applications,” in Proc. ASPDAC, Yokohama, Japan, pp. 595–600, 2007.
[11] Luo. A. W, Qing Ming Yi and Min Shi, “Design and implementation of Area optimized AES based on FPGA”,
International Conference on Business Management and Electronic Information, pp 743-746, 2011.
[12] Alma’aitah. A and Zine-Eddine Abid, “Area Efficient High Throughput subpipelined Design of the AES in CMOS
180 nm”, 5 the International Conference on Design and Test Workshop, pp 31-36, 2010.
[13] Choi.H.S, Joong H.Choi and Jong Tae Kim, “Low Power AES Design using Parallel Architecture”, International
Conference on Convergence and Hybrid Information Technology, pp 413-417, 2008.
25