AN IC THAT CONTAINS LARGE NUMBERS OF GATES, FLIP-FLOPS, ETC. THAT CAN BE CONFIGURED BY THE USER TO PERFORM DIFFERENT FUNCTIONS IS CALLED A PROGRAMMABLE LOGIC DEVICE (PLD). A PROGRAMMABLE LOGIC DEVICE IS AN ELECTRONIC COMPONENT USED TO BUILD RECONFIGURABLE DIGITAL CIRCUITS. UNLIKE INTEGRATED CIRCUITS WHICH CONSIST OF LOGIC GATES AND HAVE A FIXED FUNCTION, A PLD HAS AN UNDEFINED FUNCTION AT THE TIME OF MANUFACTURE. IT PERMITS ELABORATE DIGITAL LOGIC DESIGNS TO BE IMPLEMENTED BY THE USER ON A SINGLE DEVICE. THE INTERNAL LOGIC GATES AND/OR CONNECTIONS OF PLDS CAN BE CHANGED/CONFIGURED BY A PROGRAMMING PROCESS.

1. MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL ELECTRONICS
FACULTY NAME: Mrs. B. Indira Priyadarshini
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2. INTRODUCTION:
AN IC THAT CONTAINS LARGE NUMBERS OF GATES, FLIP-FLOPS, ETC.
THAT CAN BE CONFIGURED BY THE USER TO PERFORM DIFFERENT
FUNCTIONS IS CALLED A PROGRAMMABLE LOGIC DEVICE (PLD). A
PROGRAMMABLE LOGIC DEVICE IS AN ELECTRONIC COMPONENT USED TO
BUILD RECONFIGURABLE DIGITAL CIRCUITS. UNLIKE INTEGRATED CIRCUITS
WHICH CONSIST OF LOGIC GATES AND HAVE A FIXED FUNCTION, A PLD HAS
AN UNDEFINED FUNCTION AT THE TIME OF MANUFACTURE. IT PERMITS
ELABORATE DIGITAL LOGIC DESIGNS TO BE IMPLEMENTED BY THE USER ON
A SINGLE DEVICE. THE INTERNAL LOGIC GATES AND/OR CONNECTIONS OF
PLDS CAN BE CHANGED/CONFIGURED BY A PROGRAMMING PROCESS.
UNIT-III
OUTCOMES:
After successful completion of this Unit students should be able to
understand the architecture of PLDs like PLA,PAL ,CPLD and FPGA.
design combinational circuits using the PLDs .
understand the importance of these PLDs in the system design.
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3. CONTENTS:
PLDS
PLA
PAL
OUTCOMES:
Students will be able to implement such designs using programmable logic
MODULE-I: General structure of a PLDs
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4. Programmable Logic Devices
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•No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macro cells that usually consist of programmable array
logic followed by a flip-flop or latch

5. Programmable Logic Devices
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PLDs are low-density devices which contain 1k – 10 k gates and are available
both in bipolar and CMOS technologies [PLA, PAL, GAL, PROM]
✔ CPLDs or FPGAs - FPGAs combine architecture of gate arrays with
programmability of PLDs.
✔User Configurable
✔ Contain Regular Structures - circuit elements such as AND, OR, NAND/NOR
gates, FFs, Mux, RAMs,
✔Allow Different Programming Technologies
✔ Allow both Matrix and Row-based Architectures

6. Programmable Logic Devices
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Advantages
•Low development cost
•Less space requirement
•Less power requirement
•It is easy to troubleshoot
•Less design time
•High switching speed
•High design security
•High reliability
•Easy circuit testing
Disadvantages
•The high-cost solution in large quantities
•It requires a large area and poor performance
•Lack of security
•Large power requirement
•Not flexible in terms of integrating analog box
•Additional cost, power, space requirements, etc

7. Classification of PLDs
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General Structure of PLD:

8. OR - PLD & AND – PLD Notation
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Programming by blowing fuses.

9. PLA
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PLAs are characterized by three numbers:
•Number of input lines n
•Number of product terms that can be generated p (the number of AND gates)
•Number of output lines m
•n x p x m PLAs
A common way of specifying the connections in a PLA.
3 sections: input section, output section, T/C section.
Each product term is assigned a row in the table.
•Input section indicates connections between inputs to AND-array.
•Output section indicates connections between outputs of AND-array and
inputs to the OR-array.
•T/C section indicates how the exclusive or gates are programmed.
oT—true output is used.
oC—output should be complemented.

10. PLA
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Exclusive-or-gate with a programmable fuse

11. PLA
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Example:
F1’ = AB + AC + BC or F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

12. BCD to Excess-3 code using PLA
E3 = ∑m (5,6,7,8,9) + ∑d (10,11,12,13,14,15)
E2 = ∑m (1,2,3,4,9) + ∑d (10,11,12,13,14,15)
E1 = ∑m (0,3,4,7,8) + ∑d (10,11,12,13,14,15)
E0 = ∑m (0,2,4,6,8) + ∑d (10,11,12,13,14,15)
Combinational circuit Design with PLDs
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13. PLA
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Limitations
PLAs come in various sizes. Typical size is 16 inputs, 32 product terms, 8
outputs
Each AND gate has large fan-in. This limits the number of inputs that can be
provided in a PLA
16 inputs forms 216 possible input combinations; only 32 permitted (since 32
AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates as well: This makes PLAs
slower and slightly more expensive than some alternatives to be discussed
shortly
8 outputs could have shared min-terms, but not required
Applications
used to provide control over datapath.
used as a counter.
used as a decoders.
used as a BUS interface in programmed I/O.

14. PAL
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OR-array is fixed by the manufacturer of the device.
•PAL device is easier to program and less expensive than the PLA.
•Less flexible.
•For our examples:
o4-input, 3-output PAL device
oThree Boolean expressions can be realized in which two expressions
can have at most 3 product terms and one expression can have at
most 2 product terms.

15. PAL
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Example: W(A, B, C, D) = Σm(2, 12, 13)
X(A, B, C, D) = Σm(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y(A, B, C, D) = Σm(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z(A, B, C, D) = Σm(1, 2, 8, 12, 13)
W = ABC’ + A’B’CD’
X = A + BCD
Y = A’B + CD + B’D’
Z = ABC’ + A’B’CD + AC’D’ + A’B’C’D =W +AC’D’ + A’B’C’D

16. PAL
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17. Combinational circuit Design with PLDs
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Example: There are 3 inputs and 2 outputs,
f1 = ∑m(1, 2, 4, 5, 7)
f2 = ∑m(0, 1, 3, 5, 7)
f1= y’z+xy’+xz+x’yz’
f2 = x’y’+z

18. PLDs Package
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A PLCC(plastic –leaded chip carrier) package with socket:
PLDs are available in the DIP packages

19. Comparison: PAL Vs PLA
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PALs have the same limitations as PLAs (small number of allowed AND terms)
plus they have a fixed OR plane i.e., less flexibility than PLAs
PALs are simpler to manufacture, cheaper, and faster (better performance)
PALs also often have extra circuitry connected to the output of each OR gate
The OR gate plus this circuitry is called a macro-cell

20. 1. The inputs in the PLD is given through AND gate.
2. The content of a simple programmable logic device (PLD) consists of
thousands of basic logic gates and advanced sequential logic functions.
3. The basic programmable logic array (PLA) contains a set of NOT gates,
AND gates, and OR gates.
4. The complex programmable logic device contains several PLD blocks and a
global interconnection matrix.
5. Applications of PLAs are Registered PALs, Configurable PALs, and PAL
programming.
Questions & Answers
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ENGINEERING COLLEGE

21. CONTENTS:
STRUCTURE OF CPLD
STRUCTURE OF FPGA
LOOK UP TABLES
OUTCOMES:
Students will be able to experimentation on Hardware / software co-design on
FPGA/CPLD design
MODULE-II: Structure of CPLD and FPGA
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22. Complex Programmable Logic
Devices(CPLD)
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1. Complexity of CPLD is between FPGA and PLD.
2. CPLD feature in common PLD:
Non-volatile configuration memory – does not need an external
configuration PROM.
Routing constraints. Not for large and deeply layered logic.
3. CPLD featured in common FPGA:
Large number of gates available.
Can include complicated feedback path.
Characteristics:
They have a higher input to logic gate ratio.
These devices are denser than SPLDs but have better functional abilities.
CPLDs are based on EPROM or EEPROM technology.
If you require a larger number of macrocells for a given application,
ranging anywhere between 32 to 1000 macrocells, then a Complex
Programmable Logic Device is the solution.

23. Complex Programmable Logic
Devices(CPLD)
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24. Complex Programmable Logic
Devices(CPLD)
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25. CPLD
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Advantages:
Easy of design
Reduced board area.
It is a reliability
Cost of ownership.
More product revenue.
Development cycles are very short and get into the market.
Low development costs.
Quicker generates revenue sooner.
Disadvantages:
More complex programmable logic device that is more complex than SPLD.

26. Applications of CPLD
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Ideal for high performance, critical control applications.
Used in digital designs to perform the functions of boot loader.
Used for loading the configuration data of a field programmable gate array
from non-volatile memory.
Used in small design applications like address decoding.
Frequently used many applications like in cost sensitive, battery operated
portable devices due to its low size and usage of low power.

27. Field-Programmable Gate
Arrays(FPGAs)
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•None of the mask layers are customized.
• There is a method for programming the basic logic cells and the
interconnect.
• The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours.

28. Field-Programmable Gate
Arrays(FPGAs)
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The FPGA consists of 3 main structures:
1.Programmable logic structure
2.Programmable routing structure
3.Programmable Input/Output (I/O)

29. Field-Programmable Gate
Arrays(FPGAs)
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❑Based on Functional Unit/Logic Cell Structure
❖ Transistor Pairs
❖ Basic Logic Gates: NAND/NOR
❖ MUX
❖ Look –up Tables (LUT)
❖ Wide-Fan-In AND-OR Gates
❑ Programming Technology
❖ Anti-Fuse Technology
❖ SRAM Technology
❖ EPROM Technology
❑ Gate Density
❑ Chip Architecture (Routing Style)

30. Look Up Tables
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Two input LUT:
Three input LUT:

31. Applications of FPGA
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Implementation of random logic
•easier changes at system-level (one device is modified)
•can eliminate need for full-custom chips
Prototyping
•ensemble of gate arrays used to emulate a circuit to be manufactured
•get more/better/faster debugging done than possible with simulation
Reconfigurable hardware
•one hardware block used to implement more than one function
•functions must be mutually-exclusive in time
•can greatly reduce cost while enhancing flexibility
•RAM-based only option
Special-purpose computation engines
•hardware dedicated to solving one problem (or class of problems)
•accelerators attached to general-purpose computers

32. CPLDs vs. FPGAs
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CPLD FPGA
• Architecture: PAL-like Gate Array-like
• Density: Low to medium Medium to high
12 22V10s or more up to 1 million gates
• Speed: Fast, predictable Application dependent
• Interconnect: Crossbar Routing
• Power Consumption: High Medium

33. 1. The FPGA refers to Field Programmable Gate Array.
2. Vertical and horizontal directions is separated by a channel in an FPGA.
3. An Antifuse programming technology is predominantly associated with
FPGAs.
4. EPROM, EEPROM, FLASH programming technologies are predominantly
associated with SPLDs and CPLDs.
5. Plastic-Leaded Chip Carrier (PLCC) type of CPLD packaging comprises
pins on all four sides that wrap around the edges of chip.
Questions & Answers
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ENGINEERING COLLEGE

34. CONTENTS:
PROM
OUTCOMES:
Student will able to design programmable read only memory.
MODULE-III: Additional Topic
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35. PROM
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• AND array with buffer/inverter is an n-to-2n
- line decoder.
•OR array is a collection of programmable or-gates.
•Decoder is a min-term generator.
•n-variable min-terms appear on the 2n
lines at the decoder output. These are
also known as word lines.
•n input lines called address lines, m output lines called bit lines.
•2n
X m PROM

36. PROM
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ENGINEERING COLLEGE
Example: There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block.
f = ∑m(0, 1, 7)
g = ∑m(0, 3, 6, 7)
h = ∑m(0, 1, 3, 5, 7)

37. MATRUSRI
ENGINEERING COLLEGE
Full Adder using PROM
Sum = ∑ m (1,2,4,7)
Carry = ∑ m (3,5,6,7)
Combinational circuit Design with PROM

38. Question Bank
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ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 Write the classification of PLDs. L1 CO5
2 Draw simple architecture of CPLD. L1 CO5
3 Draw FPGA architecture. L1 CO5
4 What is look-up table? L2 CO5
5 Realize 1 bit full adder using PLA. L2 CO5
6 Give the applications of FPGA. L1 CO5
7 Mention the applications of CPLD L1 CO5
8 Compare PAL and PLA L2 CO5
9 Differentiate CPLD and FPGA? L1 CO5
10 Write the advantages of PLDs

39. Question Bank
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ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 Realize the function f = ∑m(5, 7, 10, 14, 15) using
PLA.
L2 CO5
2 Realize the half adder using 2- input Look up table
with neat sketch
L1 CO5
3 Write short notes on PLDs L1 CO5
4 Realize the function f = ∑m(4, 5, 7, 9, 13, 15) using
PLA.
L2 CO5
5 Explain the structure of FPGA with neat diagram. L2 CO5
6 Explain the structure of CPLD with neat diagram. L2 CO5
7 Design a PLA to realize the following three functions
and draw programming table F1 = A’B’D’ + B’CD’ +
A’BCDE’, F2 = A’BE + B’CD’E, F3 = A’B’D’ + B’C’D’E’ +
A’BCD.
L5 CO5

40. Assignment Questions
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1. Explain the structure of FPGA with neat diagram.
2. Explain the structure of CPLD with neat diagram.
3. Design a PLA to realize the following three functions and draw
programming table f1 =∑m(4,5,7,10), f2 =∑m(3,5,7,13).
4. Realize the gray to binary code converter using PAL.
5. Realize the full adder using 2- input Look up table with neat sketch