The document discusses VHDL (VHSIC Hardware Description Language), a hardware description language used to model, design, and test digital systems. It provides examples of modeling half adders and full adders in VHDL using different approaches like dataflow, behavioral, and structural modeling. It also compares VHDL with Verilog and provides code examples to implement basic logic gates in both languages. Test benches are demonstrated to verify and test VHDL designs.

1. VHDL
 V-VHSIC- VERY HIGH SPEED INTERGRATED CIRCUIT
 HDL- HARD WARE DISCRIPTION LANGUAGE
*VHDL AND VERILOG HDL FOR DEVELOPMENT AND
DESIGN
SYSTEM VERILOG FOR VERIFICATION
It can be model a digital system at many level of
abstraction ranging from algorithmic level to gate level

2. History of VHDL
 IT WAS FIRST GENRATION 1981
 THREE COMPANIES IBM,TEXAS INS. AND INTERMETRICS.
 DEVELOPED VERSION 7.2 OF VHDL – 1985

3. COMPARSIONOF VHDL AND
VERILOG
VHDL VERILOG HDL
Depends on library function It is independent of library
Body consisted of two parts Entire body defined as module
Case insensitivity ( upper and lower
case)
Case insensitivity
Library need for vhdl Library not need
It is free language Structural language

4. Different b/w Verilog and vhdl
Fuction Vhdl verilog
AND GATE AND &
OR GATE OR !
NAND NAND ~ &
NOR NOR ~ !
XOR XOR ^
XNOR XNOR ~^
NOT NOT ~

5.  Vhdl provides 5 different type of primary constructs called design
units.
 Entity declaration
 Configuration declaration
 Architecture body
 Package declaration
 Package body

6. HARDWARE ABSTRACT DEVICE
DEVICE DEVICE MODELmodel
Digital
systems
External view
Internal view

7. ENTITY
DECLARATION
ARCHITECTURE A
B
Z
VHDL
PROGRA
M

8. MODELS IN VHDL
 STRUCTURAL MODEL
 DATAFLOW MODEL
 BEHAVIERAL MODEL
 HYBRID MODEL
 PHYSICAL MODEL

9. STRUCTURE OF VHDL PROGRAM
 Library declaration
 Entity
 Architecture body

10. BASIC STRUCTURE OF VHDL PROGRAM
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 Entity entity name is
 Port declaration; in type ;( data type)
 port declaration ; out type;
 End entity name;
 Architecture Arc name of entity name is
 Signal declaration;
 variable declaration;
 Constant declaration;
 Package declaration;
 Component declaration;
 Begin
 Statement port
 .
 End Arc name;

11. Half adder
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
HALF ADDER:
LOGIC DIAGRAM: TRUTH TABLE:

12. Dataflow Modeling: for half adder

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity hadd is
 Port ( a : in std_logic;
 b : in std_logic;
 sum : out std_logic;
 carry : out std_logic);
 end hadd;
 architecture dataflow of hadd is
 begin
 sum <= a xor b;
 carry <= a and b;
 end dataflow;

13. Behavioral modeling for half adder
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddbehavioral is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddbehavioral;
architecture Behavioral of haddbehavioral is
begin
p1:process (a,b)
begin
sum<= a xor b;
carry<= a and b;
end process p1;
end Behavioral;

14. Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddstructural is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddstructural;
architecture structural of haddstructural is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
begin
x1: xor2 port map (a,b,sum);
a1: and2 port map (a,b,carry);
end structural;
and2 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;
end dataflow;
xor2 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;

15. Dataflow Modeling:
half adder
Behavioral Modeling:
half adder
Structural Modeling:
half adder
module ha_dataflow(a, b, s, ca);
input a;
input b;
output s;
output ca;
assign#2 s=a^b;
assign#2 ca=a&b;
endmodule
module ha_behv(a, b, s, ca);
input a;
input b;
output s;
output ca;
reg s,ca;
always @ (a or b) begin
s=a^b;
ca=a&b;
end
endmodule
module ha_struct(a, b, s, ca);
input a;
input b;
output s;
output ca;
xor
x1(s,a,b);
and
a1(ca,a,b);
endmodule
VERILOG SOURCE CODE:

16. Gate code for verilog
 VERILOG SOURCE CODE:

 module logicgates1(a, b, c);
 input a;
 input b;
 OUTPUT: [6:0] c;
 assign c[0]= a & b;
 assign c[1]= a | b;
 assign c[2]= ~(a & b);
 assign c[3]= ~(a | b);
 assign c[4]= a ^ b;
 assign c[5]= ~(a ^ b);
 assign c[6]= ~ a;
 endmodule

17. TEST BENCH(VHDL):
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.std_logic_unsigned.all;
 USE ieee.numeric_std.ALL;
 ENTITY test_bench_vhd IS
 END test_bench_vhd;
 ARCHITECTURE behavior OF test_bench_vhd IS

18.  COMPONENT hadd
 PORT(
 a : IN std_logic;
 b : IN std_logic;
 sum : OUT std_logic;
 carry : OUT std_logic
 );
 END COMPONENT;

 --Inputs
 SIGNAL a : std_logic := '0';
 SIGNAL b : std_logic := '0';

 --Outputs
 SIGNAL sum : std_logic;
 SIGNAL carry : std_logic;


19.  BEGIN
 -- Instantiate the Unit Under Test (UUT)
 uut: hadd PORT MAP(
 a => a,
 b => b,
 sum => sum,
 carry => carry
 );

 tb : PROCESS
 BEGIN
 a<='0'; b<='0'; wait for 100 ps;
 a<='0'; b<='1'; wait for 100 ps;
 a<='1'; b<='0'; wait for 100 ps;
 a<='1'; b<='1'; wait for 100 ps;

 END PROCESS;
 END;

20. FULL ADDER:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LOGIC DIAGRAM: TRUTH TABLE:

21.  Dataflow Modeling:
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity fadd_dataflow is
 Port ( a : in std_logic;
 b : in std_logic;
 c : in std_logic;
 sum : out std_logic;
 carry : out std_logic);
 end fadd_dataflow;
 architecture dataflow of fadd_dataflow is
 signal p,q,r,s:std_logic;
 begin
 p<= a xor b;
 q<= a and b;
 r<= b and c;
 s<= c and a;
 sum<= p xor c;
 carry<= q or r or s;
 end dataflow;

22.  Behavioral Modeling:
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity fadd_behv is
 Port ( a : in std_logic;
 b : in std_logic;
 c : in std_logic;
 sum : out std_logic;
 carry : out std_logic);
 end fadd_behv;
 architecture Behavioral of fadd_behv is
 begin
 p1:process(a,b,c)
 variable r,s,t:std_logic;
 begin
 r:= a and b;
 s:= b and c;
 t:= c and a;
 sum<= a xor b xor c;
 carry<= r or s or t;
 end process p1;
 end Behavioral;

23. Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_structural;
architecture structural of fadd_structural is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
component or3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal p,q,r,s:std_logic;
begin
x1: xor2 port map (a,b,p);
x2: xor2 port map (p,c,sum);
a1: and2 port map (a,b,q);
a2: and2 port map (b,c,r);
a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;

24. and2 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;
end dataflow;
or3 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end or3;
architecture dataflow of or3 is
begin
z<= a or b or c;
end dataflow;
xor2 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;