The document discusses VHDL (VHSIC Hardware Description Language) and provides information on various topics related to VHDL such as the design flow, levels of abstraction, types of HDLs, comparing VHDL and Verilog, simulation vs. synthesis, logic simulation, motivation for mixed-signal microelectronics, viewing designs by chip technology, concepts of modules and chips, levels of abstraction, types of VHDL, comparing VHDL and Verilog, choosing an HDL, the IEEE standard 1164, entities, architectures, and data objects in VHDL like constants, signals, and variables.

1. VHDL
Dr. Vandana Malode
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2. Content
• VLSI Design flow
• Level of abstraction
• Types of HDL
• Compare VHDL and Verilog
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4. Simulation Vs Synthesis
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Front End Procedure Back end procedure
Correctness of program(code) Concentration on Chip Design
Functionality of Description
Apply I/P o/p
Ex. Full Adder (2HA+1OR )
Not check
Power,Delay,Performance,Size
Size,Power,Delay , performance
Tools: Modelsim, Questasim,
Front end Mentor graphics
Tools: Xilinx , cadence, Synopsis,
Backend Mentor graphics
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5. Logic Simulation
• A simulator interprets the HDL description and produces a
readable output, such as a timing diagram, that predicts
how the hardware will behave before its is actually
fabricated.
• Simulation allows the detection of functional errors in a
design without having to physically create the circuit.
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6. Motivation
• The benefits of integrating analogue circuitry with digital
logic include:
• Higher performance
• Lower power consumption
• Less mass
• Reduced costs
• Improved reliability
• Greater levels of reusability
• Enhanced system testing and quality
• All of these benefits contribute to the spirit of “Faster,
Better, Cheaper”!
• All of these offer the potential to advance mixed-signal
microelectronics for space applications
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7. View by Chip Technology
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ARTIX7
KINTEX7
VIRTEX7
ZYNQ
SPARTAN-6
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8. Concept of module or chip
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9. 9
Levels of Abstraction
1970 1980 1990 2000+
Abstraction
Circuit Level
Gate Level
RTL
RT Level
(Module)
RTL SW
System Level
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11. Types of VHDL
• VHDL : VHSIC –HDL
VHSIC: Very High Speed Integrated Circuit- Hardware Description
Language.
It is a Hardware Description Language used in electronic design
automation to describe digital and mixed-signal systems.
VHDL is a description and simulation language like ada , panda, pascal
• Verilog HDL: Verilog Hardware Description Language.(like ‘C’
language)
HDL: Designed by IBM, Texas Instruments, and Intermetrics for
united states Air force .VHSIC program launched in 1980.
Standardized by the IEEE in 1987: IEEE 1076-1987
• TOOLS: Xilinx, Atmel, Altera, Mentor Graphics, Cadence
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12. Compare VHDL and VERILOG
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VHDL VERILOG
Entity, Multiple architecture
description
Only Module Declaration
Ada based constructs , not case
sensitive language
C language, case-sensitive
Harder to learn and use Easy to learn and use , Fast simulation
VHDL is strongly type language Verilog is weakly type language
User-defined, physical, enumeration
or pointer types is available and
required 9-valued logic
User-defined, physical, enumeration
or pointer types is not available and
required 4-valued logic
Very good FPGA library support. Better availability of ASIC library
support
Gate level , data flow and Behavioral
modeling
Gate level , data flow and Behavioral
modeling
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13. So Choose language (HDL) based on Trend and area of work
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14. IEEE STANDARD 1164
To use standard logic data types place at top of source file
– LIBRARY ieee; -- library
– USE ieee.std_logic_1164.ALL; -- package
• Provides a standard data type
(std_logic) in VHDL - nine values
– U unitialized(Default value)
– ‘X’ strong drive , unknown logic
value
– ‘0’ strong drive, logic 0
– ‘1’ forcing, logic 1
– Z high impedance ( For tri-state
logic)
– ‘W’ weak unknown logic value
– ‘L’ weak drive, logic 0
– ‘H’ weak drive, logic 1
– ‘-’ don’t care
• Provides a standard data type
(std_logic) in Verilog - Four
values
– X forcing unknown
– 0 forcing logic 0
– 1 forcing logic 1
– Z high impedance
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15. Entity
• The entity defines the external view of the component. It provides
system’s interface specification as seen from the outside.
• PORTS are the communication links between entities or connections to
the device pins
Syntax For Entity
entity EntityName is
port (port list Input and output);
end EntityName;
 Note the use of libraries before entity description
Libray ieee;
USE ieee.std_logic_1164.all;
ENTITY andgate IS
PORT (a, b : IN std_logic;
y : OUT std_logic);
END andgate;
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16. Architecture
• The Architecture defines the function or behavior or structure of
the ENTITY
• Consists of
– concurrent statements
– Sequential statements
• An entity may have several architectures Multiple Architecture
Syntax For Architecture
Architecture ArchitectureName of EntityName is
begin
-- signal declarations
-- concurrent statements
end ArchitectureName;
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Entity
A B C
Architecture behavior OF andgate is
Begin
y <= a and b;
END behavior;
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17. Complete VHDL Code for AND Gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Entity andgate is
Port (a, b : IN std_logic;
y : OUT std_logic);
End andgate;
Architecture behavior OF andgate is
Begin
Y<= a and b;
End behaviour;
• Architecture behavior END behavior;
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18. Entity and Architecture
Example: a 2-input multiplexer
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19. Data objects
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Elements
Identifiers
Data
objects
Constants
(Global)
Signals
(Global)
Variables
(Local)
Data types
Objects are used to represent and store the data in the system being described in VHDL.
Example- SIGNAL COUNT: INTEGER
Class
Object
Data Type
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20. CLASS: Each object belong to one of following class:
 Constant: Hold values that cannot be changed within a
design.
Syntax: Constant constant name: Data Type := Value;
Example: 1] constant width: integer :=8;
2] constant Clk_Period: Time := 15 ns;
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• Constant
• Signals
• Variables
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21. CLASS
• Variable: A variable is an object with single value.
• Values can be change during simulation through the variable
assignment statements.
• A variable declaration include one or more identifiers.
• Variable used in Process not in architecture.
• Internal representation used by programmers; do not exist
physically.
• Syntax: variable identifier_list: type [range_expr] [:=expression];
Example: 1] variable A,B: Std_logic;
2] Variable sum : std_logic-vector( 0 to 7);
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Variable name
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22. CLASS
 Signal: To represent wire connections within circuit.
Signal is an object within past history of values.
Signal have multiple drivers each with a current value and
projected future value. Signal Describing H/W sytsem.
Syntax: Signal identifier_list: type [range_expr] [:=expression];
Example: 1] signal count: STD_LOGIC_VECTOR (3 downto 0);
2] signal Gate-Delay: Time:=10ns;
-- count means 4 wires; they are count(3),count(2), count(1), count(0).
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