IEEE CUSB '19 Electronics directorate

1. VHDL Session 1
Authors : Gamal Saied & Hazem Fathy
10/22/20181

2. Table of contents
Introduction to Digital Design Flow
i. Digital Design
ii. Digital Verification
Introduction to VHDL
i. Basic rules of VHDL
ii. Design basics
iii. Data types
iv. Operators
v. Design rules
2 10/22/2018

3. 10/22/20183
Introduction to Digital Design
HDLs perquisites
– Programming languages
– Digital logic circuits
Make your own hardware!!
Recall your logic courses
a
b
c
y
y a b c  

4. Introduction to Digital Design
FPGA & CPLD
ASICs
Application Specific
Integrated Circuits
Microprocessors
Microcontrollers

5. Industry Pioneers
– Mentor Graphics
– Xilinx
– Synopsys
– Qualcomm
– Altera (INTEL)
Introduction to Digital Design
5

6. 10/22/20186
FPGAs
An integrated circuit that can be
programmed/reprogrammed with a digital logic of
a curtain level.
Started at late 70s and constantly growing
Now available of up to approximately 700K Flip-
Flops in a single chip.
Rare industrial usage
I/O
I/O
Logic
block
Interconnection switches
I/O
I/O

7. Advantages
– Reconfigurable
– Saves board space
– Flexible to changes
– No need for ASIC expensive design and production
– Fast time to market
– Bugs can be fixed easily
– Of the shelf solutions are available
FPGAs

8. 10/22/20188
ASICs
ASIC stands for Application Specified Integrated
circuit
Widely used in industrial applications
More complex than FPGAs

9. 10/22/20189
FPGAs vs ASIC

10. Digital Verification
Digital Manufacture Process
Verification
Design
10 10/22/2018
 Digital Design only presents 30% of
the Manufacturing process!!
 Verification Cycle is more complex
than design cycle.

11. Digital Verification
Verification methods:
– Formal Verification
– Lint Verification
– Clock Domain Checking (CDC)
– Test Benches
11 10/22/2018

12. Design Flow
12 10/22/2018

13. Design Flow
13 10/22/2018
Specification
HDL
(VHDL , Verilog ,C , Simulink)
Simulation
(Modelsim / Quartus)
Synthesis
Convert HDL to FPGA logic
(Quartus / Third party tools)
Place and Route
(Quartus)
Bit-File
(FPGA configuration)
Timing constrains
FPGA
(Debug using Signal TAP logic analyser)
Timing Simulation if needed
(Modelsim / Quartus)
Timing Analyzer
(Quartus)
Timing constrains
Pin-out

14. Introduction to VHDL
VHDL stands for VHSIC(Very high speed integrated circuit)
Hardware Description Language
Used in both Design and Verification processes.
Developed in the early 1980’s by the Pentagon base on ADA
Updated over the last 4 decades (93-95-2002-2008)
We will use IEEE 1076-2002 STD
14 10/22/2018
Remember HDLs are NOT for software
purposes

15. Introduction to VHDL
All names should start with an alphabet character (a-z or A-Z)
Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_)
Do not use any punctuation or reserved characters within a name
(!, ?, ., &, +, -, etc.)
Do not use two or more consecutive underscore characters (__)
within a name (e.g., Sel__A is invalid)
All names and labels in a given entity and architecture must be
unique
All names should not be from the reserved words list(IN,OUT,..)
15 10/22/2018

16. Introduction to VHDL
VHDL is not case sensitive (except for rare instances) i.e:
– Signal2
– SIGnal2
– SIGNAL2
– signaL2
– All of the above naming are valid and index the same identifier
16 10/22/2018

17. Introduction to VHDL
Comments are indicated with double dash chars (--) i.e:
1. Entity data ;
2. --Entity data2 ;  Ignored by the compiler
3. End entity ;
No block comments are allowed in VHDL
Double dashing any part of a line is allowed
17 10/22/2018

18. REFRESH
Design an OR gate using 2 NAND gates
18 10/22/2018

19. REFRESH
Design an OR gate using 2 NAND gates
19 10/22/2018

20. Design basics
A design has 3 main parts :
– Package and Library declaration
– Entity declaration
– Architecture
20 10/22/2018

21. Design basics
Libraries are collections of reusable pieces of codes
Most common used library is IEEE
Most used packages are
– Std_logic_1164
– Std_logic_arithmetic
– Std_logic_unsigned
– Std_logic_signed
– Numeric_std
– Numeric_bit
– User defined packages
21 10/22/2018

22. Design basics
Package declaration syntax (section 2.5)
Packages are useful design wise for reusable functions/pieces of
code
.all prefix allows usage of all package elements
22 10/22/2018

23. Design basics
Entity declaration syntax
23 10/22/2018

24. Design basics
24 10/22/2018
Entity is the wrapper of the design module
It describes the interface of the design (input/output ports ,
components,..)
An entity may contain numerous libraries/packages/architectures
Entities may be used in other instances (explained later)

25. Design basics
Port modes variation define the direction of data carried by
an identified port
– IN PORTS : an input to the entity that is ONLY used for assignments
– OUT PORTS : an output of the entity that is assigned to
– INOUT/BUFFER PORTS : combination of both modes ( Not practical)
25 10/22/2018

26. Design basics
Architecture Body
26 10/22/2018

27. Design basics
Declarative part of Architecture may contain local signal and
variable declarations
An entity may contain multiple architectures
Architectures statements must
be in begin-end scope
27 10/22/2018

28. Design basics
SCOPE RULES*
– Global scope
 INCLUDED PACKAGE/LIBRARY
 ENTITY PORTS
– Local scope
 ARCHITECTURES DECLARATIVE PART
 BEGIN-END STATEMENTS
 CONCURRENT AND SEQUENTIAL STATEMENTS
*Refer to section 10.2
28 10/22/2018

29. Design basics
Signals are wires that interconnect ports and other signals or ports
Signal carry the same types as ports*
Signals are better declared locally
<= assignment operator is used to assign (to) signals.
*Signals do not have direction
29 10/22/2018

30. Data types
VHDL has numerous data types :
– BIT: holds value of (0,1) only
– Predefined types ( integers , strings,
characters,..)
– Std_logic and std_ulogic
STD_LOGIC is the most used type
It may hold 9 values (useful for
simulation)
30 10/22/2018

31. Data types
31 10/22/2018
Only 1,0,Z values are synthesizable
Is included in std_logic_1164
package
May be declared as a vector with
specified range :
– Signal A:std_logic_vector(3 downto 0 )

32. Data types
32 10/22/2018
Std_logic is a resolved data
type
X state indicates multi driven
bit
VHDL is HARD-WRITTEN
language

33. Operators
33 10/22/2018

34. Operators
Operators are used in description of functional assignments
Each group of operators belong to a specific types of operands
(why)?
34 10/22/2018

35. Operators
Concatenation operator --&--
Single quotes are for bit
selects
Double quotes are for bit
vector select
35 10/22/2018

36. Operators
SLL and SRL operators are
used to shift vectors.
These operators DOES NOT
operate on
STD_LOGIC_VECTORS
VHDL 2008 Supports this
feature
36 10/22/2018

37. Operators
ROL and ROR operators
behave the same as shift
operators
You may use concatenation
instead of operators
Value of rotation/shifting
must be integer
37 10/22/2018

38. EX1
Describe the following circuit using VHDL.
38 10/22/2018

39. EX1
39 10/22/2018

40. EX2
Describe the following circuit using VHDL
40 10/22/2018

41. EX2
41 10/22/2018

42. Design rules
Use tabs for every scope generated
Choose a specific naming method i.e ( inputs : i1,i2 , outputs :
o1,o2..)
Comment expression with useful statements (make your code
readable)
Constants are UPPER CASE named i.e( constant CYCLE_D : integer
:= 2 );
File name should be the same as entity name
42 10/22/2018

43. Assignment1
Describe the following circuit using VHDL
43 10/22/2018

44. Assignment1 solution
44 10/22/2018

45. HOMEWORK
Write the truth table of the following circuit and write its equivalent
VHDL code
45 10/22/2018

46. HOMEWORK
Deliverables:
– Compiled .vhd file containing the function code
– READABLE code written w.r.t design rules
Please send your .vhd files to gamal.saiedeece@gmail.com
Good Luck 
46 10/22/2018