VHDL is a hardware description language used to model electronic systems. The document outlines the key structural elements of VHDL including entities, architectures, signals, and data types. It describes different design methodologies in VHDL like behavioral, dataflow, and structural. Behavioral models use boolean equations, dataflow uses concurrent assignments, and structural connects known components. The document provides examples of modeling half adders, full adders, and multiplexers in VHDL using the different methodologies.

1. VHDLPrepared by:Gaurav

2. Outline….. Brief Overview of VHDLStructural elements of VHDLEntityArchitectureSignalsData Types & Operator VHDLDesign MethodologyBehavioral StructuralDataflow

3. Brief Overview of VHDL• VHDL... stands forVeryHighSpeedIntegratedCircuitHardwareDescriptionLanguagecan be translated into an actual hardware implementation

4. allows complex digital circuits to be easily created

5. In VHDL, strong understanding of your code is more important than syntax & style.Structural Elements• Entity • Interface • Example: Ports, I/O• Architecture • Implementation • Behavior •FunctionVhdl model

6. ENTITYprovides a name to the component contains the port definitions in the interface listcan contain some generic definitions which can be used to override default valuesentity identifier is generic interface_list; port interface_list; declarationsbeginstatementsend [entity] [identifier];

7. Example Andacb2 input And gate1. entity and is port (a, b: in bit; c : out bit); end and;2. ENTITY and IS PORT( a, b : IN std_logic; c: OUT std_logic ); END and;

8. Architectureencapsulates the behavior and timing informationcontains a number of concurrent statementsthere can be multiple architecture bodies for a given entity architecture identifier of entity_name isdeclarations beginstatements end [architecture] [identifier];

9. Example Andacb2 input And gatearchitecture and_arch of and is;begin;c<= a and b;end and_arch;

10. SignalsSignals are intermediary ‘ports’ within the architecture

11. represents wires and storage elementsAXorBsumCDAnd Or EAnd Carry F And Circuit diagram of full adder

12. Data TypesData typeScalar TypeComposite Type Access TypeFile TypeRecordIntegerFloatArrayPhysicalEnumeration

13. Typical OperatorsOperators

14. Design Methodology

15. Dataflow Concurrent/ Continuously or Combinational LogicTo give a signal a concurrent assignmentSignalName <= expression;Inputs Outputs Full adderSum (s)ABCarry out (c)Carry( in)

16. Dataflow(cont.)AXorBSum (s)Carry in (c _in)DAnd Or ECarry out (c_out)And F And Circuit diagram of full adder

17. Dataflow(cont.)library ieee;use ieee.std_logic_1164.all;ENTITY fulladder ISPORT ( a, b, c_in : IN BIT; s, c_out : OUT BIT);END fulladder;architecture fulladder_arch of fulladder isbegins<=a xor b xor c;c_out<= (a and b) or (b and c ) or (c and a);end fulladder_arch;

18. Behavioral The circuit is described by means of Boolean equations and a set of sequential instructions.4 x 1abxcds0s1Multiplexer 4 x 1

19. Behavioral (cont.)ENTITY mux ISPORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT;x, : OUT BIT);END mux;ARCHITECTURE sequential OF mux ISProcess (a, b, c, d, s0, s1 )VARIABLE sel : INTEGER;BEGINIF s0 = ‘0’ and s1 = ‘0’ THENsel := 0;ELSIF s0 = ‘1’ and s1 = ‘0’ THENsel := 1;ELSIF s0 = ‘0’ and s1 = ‘0’ THENsel := 2;ELSEsel := 3;END IF;CASE sel ISWHEN 0 =>x <= a;WHEN 1 =>x <= b;WHEN 2 =>x <= c;WHEN OTHERS =>x <= d;END CASE;END PROCESS;END sequential;

20. StructuralThe circuit is described as an interconnection of known components.AxorsumBandcarryHalf adderAHalf Adder 1sumHalf Adder 2B CarryoutOrCarry inFull adder using half adder

21. Structural (cont.)HALF ADDER (USED FOR FULL ADDER)library ieee;use ieee.std_logic_1164.all;entity HA isport(a,b:in std_logic;s,c:out std_logic);end HA;architecture dataflow of HA isbegins<= a xor b;c<= a and b;end dataflow;library ieee;use ieee.std_logic_1164.all;entity OR2 isport(i1,i2:in std_logic; o:out std_logic);end OR2;architecture dataflow of OR2 isbegino<= i1 or i2;end dataflow;

22. Structural (cont.)--STRURAL DESCRIPTION OF FULL ADDERlibrary ieee;use ieee.std_logic_1164.all;entity FA isport(x, y, ci :in std_logic;sum,co:out std_logic);end FA;architecture struct of FA iscomponent HA port(a, b: in std_logic;s, c:out std_logic);end component;component OR2 port(i1,i2:in std_logic;o:out std_logic);end component;signal s1,c1,c2:std_logic;begin HA1:HA port map(x ,y ,s1 ,c1); HA2:HA port map(s1,ci,sum ,c2); ORG:OR2 port map(c1,c2,co);end struct;

23. Advantages of VHDLStandard languageConcurrent & sequential statement processingNo standard methodologyMan machine readable documentationVersatile design support

24. References[1] Douglas L. Perry, VHDL: “programming by example”, McGraw-Hill, New York, 2002, Fourth Edition.[2] Wai-Kai Chen,” The VLSI Handbook “, CRC Press, USA, Second Edition. [3] Dr. Cecil alford tsai chi huang, “Digital design vhdl laboratory notes”, 1996, version 1.01, [4] http://en.wikipedia.org/wiki/Very-large-scale_integration [5] 1076 IEEE Standard VHDL Language Reference Manual

25. Questions?