VHDL is a hardware description language used to model digital systems. It allows modeling at different levels of abstraction like gate level, register transfer level, and behavioral level. In VHDL, an entity declares the interface of a design unit with ports, an architecture describes the internal functionality using different styles like dataflow, behavioral, structural. Components can be instantiated and interconnected in structural modeling. Testbenches are used to check designs by applying test inputs and observing outputs.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
VHDL (VHSIC Hardware Description Language) is becoming increasingly popular as a way to capture complex digital electronic circuits for both simulation and synthesis. Digital circuits captured using VHDL can be easily simulated, are more likely to be synthesizable into multiple target technologies, and can be archived for later modification and reuse.
PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
THIS SLIDE IS FROM RAZAVI,ON FLIP-FLOPS,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS PRESENTED BY BCE 8TH SEMESTER ENGINEERING STUDENTS TO PROF. RAVITESH MISHRA
VHDL (VHSIC Hardware Description Language) is becoming increasingly popular as a way to capture complex digital electronic circuits for both simulation and synthesis. Digital circuits captured using VHDL can be easily simulated, are more likely to be synthesizable into multiple target technologies, and can be archived for later modification and reuse.
PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
THIS SLIDE IS FROM RAZAVI,ON FLIP-FLOPS,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS PRESENTED BY BCE 8TH SEMESTER ENGINEERING STUDENTS TO PROF. RAVITESH MISHRA
THIS PPT CONTAINS Definition,Principal components of a SM chart,ASM chart for combinational circuits,ASM chart in equivalent form,Example of development of ASM chart from Mealy Machine,Example of development of ASM chart from Moore Machine,Advantages of ASM chart
Introduction to C Language - Version 1.0 by Mark John LadoMark John Lado, MIT
The C programming language is a general-purpose, high – level language (generally denoted as structured language). C programming language was at first developed by Dennis M. Ritchie at At&T Bell Labs.
C is one of the most commonly used programming languages. It is simple and efficient therefore it becomes best among all. It is used in all extents of application, mainly in the software development.
Many software's & applications as well as the compilers for the other programming languages are written in C also Operating Systems like Unix, DOS and windows are written in C.
C has many powers, it is simple, stretchy and portable, and it can control system hardware easily. It is also one of the few languages to have an international standard, ANSI C.
VHDL stands for very high speed integrated circuit hardware description language and used to design and simulate basic as well as complex digital circuits.
Observation of Io’s Resurfacing via Plume Deposition Using Ground-based Adapt...Sérgio Sacani
Since volcanic activity was first discovered on Io from Voyager images in 1979, changes
on Io’s surface have been monitored from both spacecraft and ground-based telescopes.
Here, we present the highest spatial resolution images of Io ever obtained from a groundbased telescope. These images, acquired by the SHARK-VIS instrument on the Large
Binocular Telescope, show evidence of a major resurfacing event on Io’s trailing hemisphere. When compared to the most recent spacecraft images, the SHARK-VIS images
show that a plume deposit from a powerful eruption at Pillan Patera has covered part
of the long-lived Pele plume deposit. Although this type of resurfacing event may be common on Io, few have been detected due to the rarity of spacecraft visits and the previously low spatial resolution available from Earth-based telescopes. The SHARK-VIS instrument ushers in a new era of high resolution imaging of Io’s surface using adaptive
optics at visible wavelengths.
Earliest Galaxies in the JADES Origins Field: Luminosity Function and Cosmic ...Sérgio Sacani
We characterize the earliest galaxy population in the JADES Origins Field (JOF), the deepest
imaging field observed with JWST. We make use of the ancillary Hubble optical images (5 filters
spanning 0.4−0.9µm) and novel JWST images with 14 filters spanning 0.8−5µm, including 7 mediumband filters, and reaching total exposure times of up to 46 hours per filter. We combine all our data
at > 2.3µm to construct an ultradeep image, reaching as deep as ≈ 31.4 AB mag in the stack and
30.3-31.0 AB mag (5σ, r = 0.1” circular aperture) in individual filters. We measure photometric
redshifts and use robust selection criteria to identify a sample of eight galaxy candidates at redshifts
z = 11.5 − 15. These objects show compact half-light radii of R1/2 ∼ 50 − 200pc, stellar masses of
M⋆ ∼ 107−108M⊙, and star-formation rates of SFR ∼ 0.1−1 M⊙ yr−1
. Our search finds no candidates
at 15 < z < 20, placing upper limits at these redshifts. We develop a forward modeling approach to
infer the properties of the evolving luminosity function without binning in redshift or luminosity that
marginalizes over the photometric redshift uncertainty of our candidate galaxies and incorporates the
impact of non-detections. We find a z = 12 luminosity function in good agreement with prior results,
and that the luminosity function normalization and UV luminosity density decline by a factor of ∼ 2.5
from z = 12 to z = 14. We discuss the possible implications of our results in the context of theoretical
models for evolution of the dark matter halo mass function.
Slide 1: Title Slide
Extrachromosomal Inheritance
Slide 2: Introduction to Extrachromosomal Inheritance
Definition: Extrachromosomal inheritance refers to the transmission of genetic material that is not found within the nucleus.
Key Components: Involves genes located in mitochondria, chloroplasts, and plasmids.
Slide 3: Mitochondrial Inheritance
Mitochondria: Organelles responsible for energy production.
Mitochondrial DNA (mtDNA): Circular DNA molecule found in mitochondria.
Inheritance Pattern: Maternally inherited, meaning it is passed from mothers to all their offspring.
Diseases: Examples include Leber’s hereditary optic neuropathy (LHON) and mitochondrial myopathy.
Slide 4: Chloroplast Inheritance
Chloroplasts: Organelles responsible for photosynthesis in plants.
Chloroplast DNA (cpDNA): Circular DNA molecule found in chloroplasts.
Inheritance Pattern: Often maternally inherited in most plants, but can vary in some species.
Examples: Variegation in plants, where leaf color patterns are determined by chloroplast DNA.
Slide 5: Plasmid Inheritance
Plasmids: Small, circular DNA molecules found in bacteria and some eukaryotes.
Features: Can carry antibiotic resistance genes and can be transferred between cells through processes like conjugation.
Significance: Important in biotechnology for gene cloning and genetic engineering.
Slide 6: Mechanisms of Extrachromosomal Inheritance
Non-Mendelian Patterns: Do not follow Mendel’s laws of inheritance.
Cytoplasmic Segregation: During cell division, organelles like mitochondria and chloroplasts are randomly distributed to daughter cells.
Heteroplasmy: Presence of more than one type of organellar genome within a cell, leading to variation in expression.
Slide 7: Examples of Extrachromosomal Inheritance
Four O’clock Plant (Mirabilis jalapa): Shows variegated leaves due to different cpDNA in leaf cells.
Petite Mutants in Yeast: Result from mutations in mitochondrial DNA affecting respiration.
Slide 8: Importance of Extrachromosomal Inheritance
Evolution: Provides insight into the evolution of eukaryotic cells.
Medicine: Understanding mitochondrial inheritance helps in diagnosing and treating mitochondrial diseases.
Agriculture: Chloroplast inheritance can be used in plant breeding and genetic modification.
Slide 9: Recent Research and Advances
Gene Editing: Techniques like CRISPR-Cas9 are being used to edit mitochondrial and chloroplast DNA.
Therapies: Development of mitochondrial replacement therapy (MRT) for preventing mitochondrial diseases.
Slide 10: Conclusion
Summary: Extrachromosomal inheritance involves the transmission of genetic material outside the nucleus and plays a crucial role in genetics, medicine, and biotechnology.
Future Directions: Continued research and technological advancements hold promise for new treatments and applications.
Slide 11: Questions and Discussion
Invite Audience: Open the floor for any questions or further discussion on the topic.
Nutraceutical market, scope and growth: Herbal drug technologyLokesh Patil
As consumer awareness of health and wellness rises, the nutraceutical market—which includes goods like functional meals, drinks, and dietary supplements that provide health advantages beyond basic nutrition—is growing significantly. As healthcare expenses rise, the population ages, and people want natural and preventative health solutions more and more, this industry is increasing quickly. Further driving market expansion are product formulation innovations and the use of cutting-edge technology for customized nutrition. With its worldwide reach, the nutraceutical industry is expected to keep growing and provide significant chances for research and investment in a number of categories, including vitamins, minerals, probiotics, and herbal supplements.
Richard's entangled aventures in wonderlandRichard Gill
Since the loophole-free Bell experiments of 2020 and the Nobel prizes in physics of 2022, critics of Bell's work have retreated to the fortress of super-determinism. Now, super-determinism is a derogatory word - it just means "determinism". Palmer, Hance and Hossenfelder argue that quantum mechanics and determinism are not incompatible, using a sophisticated mathematical construction based on a subtle thinning of allowed states and measurements in quantum mechanics, such that what is left appears to make Bell's argument fail, without altering the empirical predictions of quantum mechanics. I think however that it is a smoke screen, and the slogan "lost in math" comes to my mind. I will discuss some other recent disproofs of Bell's theorem using the language of causality based on causal graphs. Causal thinking is also central to law and justice. I will mention surprising connections to my work on serial killer nurse cases, in particular the Dutch case of Lucia de Berk and the current UK case of Lucy Letby.
Cancer cell metabolism: special Reference to Lactate PathwayAADYARAJPANDEY1
Normal Cell Metabolism:
Cellular respiration describes the series of steps that cells use to break down sugar and other chemicals to get the energy we need to function.
Energy is stored in the bonds of glucose and when glucose is broken down, much of that energy is released.
Cell utilize energy in the form of ATP.
The first step of respiration is called glycolysis. In a series of steps, glycolysis breaks glucose into two smaller molecules - a chemical called pyruvate. A small amount of ATP is formed during this process.
Most healthy cells continue the breakdown in a second process, called the Kreb's cycle. The Kreb's cycle allows cells to “burn” the pyruvates made in glycolysis to get more ATP.
The last step in the breakdown of glucose is called oxidative phosphorylation (Ox-Phos).
It takes place in specialized cell structures called mitochondria. This process produces a large amount of ATP. Importantly, cells need oxygen to complete oxidative phosphorylation.
If a cell completes only glycolysis, only 2 molecules of ATP are made per glucose. However, if the cell completes the entire respiration process (glycolysis - Kreb's - oxidative phosphorylation), about 36 molecules of ATP are created, giving it much more energy to use.
IN CANCER CELL:
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
introduction to WARBERG PHENOMENA:
WARBURG EFFECT Usually, cancer cells are highly glycolytic (glucose addiction) and take up more glucose than do normal cells from outside.
Otto Heinrich Warburg (; 8 October 1883 – 1 August 1970) In 1931 was awarded the Nobel Prize in Physiology for his "discovery of the nature and mode of action of the respiratory enzyme.
WARNBURG EFFECT : cancer cells under aerobic (well-oxygenated) conditions to metabolize glucose to lactate (aerobic glycolysis) is known as the Warburg effect. Warburg made the observation that tumor slices consume glucose and secrete lactate at a higher rate than normal tissues.
Cancer cell metabolism: special Reference to Lactate Pathway
INTRODUCTION TO VHDL
1. What is VHDL?
VHDL stands for very high-speed integrated circuit hardware description
language. Which is one of the programming language used to model a digital
system by dataflow, behavioral and structural style of modeling. This language was
first introduced in 1981 for the department of Defense (DoD) under the VHSIC
programe. In 1983 IBM, Texas instruments and Intermetrics started to develop this
language. In 1985 VHDL 7.2 version was released. In 1987 IEEE standardized the
language.
Describing a design:
In VHDL an entity is used to describe a hardware module.
An entity can be described using,
1. Entity declaration.
2. Architecture.
3. Configuration
4. Package declaration.
5. Package body.
Entity declaration:It defines the names, input output signals and modes of a
hardware module.
Syntax:
entity entity_name is
Port declaration;
end entity_name;
An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.
2. Ports are interfaces through which an entity can communicate with its
environment. Each port must have a name, direction and a type. An entity may
have no port declaration also. The direction will be input, output or inout.
In Port can be read
Out Port can be written
Inout Port can be read and
written
Buffer Port can be read and
written, it
can have only one source.
Architecture:
It describes the internal description of design or it tells what is there inside
design. Each entity has atleast one architecture and an entity can have many
architecture. Architecture can be described using structural, dataflow, behavioral or
mixed style. Architecture can be used to describe a design at different levels of
abstraction like gate level, register transfer level (RTL) or behavior level.
Syntax:
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;
Here we should specify the entity name for which we are writing the
architecture body. The architecture statements should be inside the begin and end
keyword. Architecture declarative part may contain variables, constants, or
component declaration.
3. Configuration:
If an entity contains many architectures and any one of the possible
architecture binding with its entity is done using configuration. It is used to bind
the architecture body to its entity and a component with an entity.
Syntax:
configuration configuration_name of entity_name is
block_configuration;
end configuration_name.
Block_configuration defines the binding of components in a block. This can be
written as
for block_name
component_binding;
end for;
block_name is the name of the architecture body. Component binding binds the
components of the block to entities. This can be written as,
for component_labels:component_name
block_configuration;
end for;
Package declaration:
Package declaration is used to declare components, types, constants, functions
and so on.
Syntax:
package package_name is
Declarations;
end package_name;
4. Package body:
A package body is used to declare the definitions and procedures that are
declared in corresponding package. Values can be assigned to constants declared in
package in package body.
Syntax:
package body package_name is
Function_procedure definitions;
end package_name;
The internal working of an entity can be defined using different modeling styles
inside architcture body. They are
1. Dataflow modeling.
2. Behavioral modeling.
3. Structural modeling.
Structure of an entity:
Let’s try to understand with the help of one example.
5. Dataflow modeling:
In this style of modeling, the internal working of an entity can be implemented
using concurrent signal assignment.
Let’s take half adder example which is having one XOR gate and a AND gate.
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ha_en is
port (A,B:in bit;S,C:out bit);
end ha_en;
architecture ha_ar of ha_en is
begin
S<=A xor B;
C<=A and B;
end ha_ar;
Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic
type, called STD_ULOGIC. use is a keyword, which imports all the declarations
from this package. The architecture body consists of concurrent signal
assignments, which describes the functionality of the design. Whenever there is a
change in RHS, the expression is evaluated and the value is assigned to LHS.
6. Behavioral modeling:
In this style of modeling, the internal working of an entity can be implemented
using set of statements.
It contains:
Process statements
Sequential statements
Signal assignment statements
Wait statements
Process statement is the primary mechanism used to model the behavior of an
entity. It contains sequential statements, variable assignment (:=) statements or
signal assignment (<=) statements etc. It may or may not contain sensitivity list. If
there is an event occurs on any of the signals in the sensitivity list, the statements
within the process is executed.
Inside the process the execution of statements will be sequential and if one entity is
having two processes the execution of these processes will be concurrent. At the
end it waits for another event to occur.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ha_beha_en is
port(
A : in BIT;
B : in BIT;
S : out BIT;
C : out BIT
);
end ha_beha_en;
7. architecture ha_beha_ar of ha_beha_en is
begin
process_beh:process(A,B)
begin
S<= A xor B;
C<=A and B;
end process process_beh;
end ha_beha_ar;
Here whenever there is a change in the value of a or b the process statements are
executed.
Structural modeling:
The implementation of an entity is done through set of interconnected
components.
It contains:
Signal declaration.
Component instances
Port maps.
Wait statements.
Component declaration:
Syntax:
component component_name [is]
List_of_interface ports;
end component component_name;
Before instantiating the component it should be declared using component
declaration as shown above. Component declaration declares the name of the entity
and interface of a component.
8. Let’s try to understand this by taking the example of full adder using 2 half adder
and 1 OR gate.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;
architecture fa_ar of fa_en is
component ha_en
port(A,B:in bit;S,C:out bit);
end component;
signal C1,C2,S1:bit;
begin
HA1:ha_en port map(A,B,S1,C1);
HA2:ha_en port map(S1,Cin,SUM,C2);
CARRY <= C1 or C2;
9. end fa_ar;
The program we have written for half adder in dataflow modeling is instantiated as
shown above. ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are
the signals used for internal connections of the component which are declared
using the keyword signal. Port map is used to connect different components as well
as connect components to ports of the entity.
Component instantiation is done as follows.
Component_label: component_name port map (signal_list);
Signal_list is the architecture signals which we are connecting to component ports.
This can be done in different ways. What we declared above is positional binding.
One more type is the named binding. The above can be written as,
HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1 );
HA2:ha_en port map(A => S1,B => Cin, S=> SUM, C => C2);
Test bench:
The correctness of the above program can be checked by writing the test bench.
The test bench is used for generating stimulus for the entity under test. Let’s write
a simple test bench for full adder.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity tb_en is
end tb_en;
architecture tb_ar of tb_en is
signal a_i,b_i,c_i,sum_i,carry_i:bit;
10. begin
eut: entity work.fa_en(fa_ar)
port
map(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry_i);
stimulus: process
begin
a_i<='1';b_i<='1';c_i<='1';
wait for 10ns;
a_i<='0';b_i<='1';c_i<='1';
wait for 10ns;
a_i<='1';b_i<='0';c_i<='0';
wait for 10ns;
if now=30ns then
wait;
end if;
end process stimulus;
end tb_ar;
Here now is a predefined function that returns the current simulation time
What we saw upto this is component instantiation by positional and by name. In
this test bench example the entity is directly instantiated. The direct entity
instantiation syntax is:
Component_label: entity entity_name (architecture_name)
port map(signal_list);