This document outlines the course content for the Digital Electronics course taught by Dr. S. Yazhinian during the summer semester of 2023-2024. The course covers combination logic circuits, HDL modeling styles including structural, dataflow and behavioral, and provides examples of modeling common combinational logic circuits like adders, subtractors, multiplexers and decoders in VHDL. It also demonstrates modeling priority encoders using conditional and sequential signal assignments.

1. Dr.S.Yazhinian
School of Computing
Department of Computer Science & Engineering
10211CS201-Digital Electronics
Summer Semester(2023-2024)
Course Category : Program Core
Subject Handling Faculty : Dr.S.Yazhinian
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2. Dr.S.Yazhinian
UNIT II: COMBINATIONAL CIRCUITS AND HDL
Half adder – Full Adder – Half subtractor – Full subtractor –Multiplexer/
Demultiplexer – decoder - encoder – parity checker – parity generators
– code converters - Magnitude Comparator-Introduction to Verilog /
VHDL- Structural, Dataflow and Behavioral modeling. Structural,
Dataflow and Behavioral modeling of combinational logic circuits
(Multiplexer, Demultiplexer, decoder and encoder).
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VHDL Introduction
• VHDL stands for very high-speed integrated circuit hardware description
language.
• It is a programming language used to model a digital system by dataflow,
behavioral and structural style of modeling.
• This language was first introduced in 1981 for the department of Defense
(DoD) under the VHSIC program.
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Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be
described using,
• Entity declaration
• Architecture
• Configuration
• Package declaration
• Package body
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Entity Declaration
Syntax −
entity entity_name is
Port declaration;
end entity_name;
An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The
direction will be input, output or inout.
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Architecture
• Architecture − Architecture can be described using structural, dataflow,
behavioral or mixed style.
Syntax −
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;
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Data Flow Modeling
• In this modeling style, the flow of data through the entity is expressed using
concurrent (parallel) signal.
• The concurrent statements in VHDL are WHEN and GENERATE.
In concurrent code, the following can be used −
Operators
The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
The GENERATE statement;
The BLOCK statement
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Behavioral Modeling
• In this modeling style, the behavior of an entity as set of statements is executed
sequentially in the specified order.
• Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are
sequential.
• PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code
that are executed sequentially.
• The behavior statements are IF, WAIT, CASE, and LOOP
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Structural Modelling
• In this modeling, an entity is described as a set of interconnected
components.
• A component instantiation statement is a concurrent statement.
Therefore, the order of these statements is not important.
• The structural style of modeling describes only an interconnection of
components (viewed as black boxes), without implying any behavior
of the components themselves nor of the entity that they collectively
represent.
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Logic Operation – AND GATE
• VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity and1 is
port(x,y:in bit ; z:out bit);
end and1;
architecture virat of and1 is
begin
z<=x and y;
end virat;
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Logic Operation – OR Gate
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity or1 is
port(x,y:in bit ; z:out bit);
end or1;
architecture virat of or1 is
begin
z<=x or y;
end virat;
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Logic Operation – NOT Gate
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity not1 is
port(x:in bit ; y:out bit);
end not1;
architecture virat of not1 is
begin
y<=not x;
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Examples of VHDL Code
• Arithmetic Circuits in VHDL:
– Consider the half addercircuit
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• Using StructuralArchitecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_AIS
PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC);
END H_A;
ARCHITECTURE HA_STR OF H_AIS COMPONENT
XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC); END
COMPONENT;
COMPONENTAND2
PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC); END
COMPONENT;
BEGIN
X1: XOR2 PORT MAP (A,B,S);
X2: AND2 PORT MAP(A,B,C);
END HA_STR;
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• Using Data FlowArchitecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_AIS
PORT (A, B: IN STD_LOGIC; S, C: OUT
STD_LOGIC); END H_A;
ARCHITECTURE HA_DF OF H_A IS
BEGIN
S <= A XOR B AFTER
10ns; C <= AAND B
AFTER 5ns;
END HA_DF;
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• Using Behavioural Modeling
ENTITY H_A IS PORT(A, B: IN BIT;
S, C: OUT BIT); END H_A;
ARCHITECTUER BEHAVE_HA OF H_AIS
BEGIN
PROSESS (A, B) BEGIN
IF A=‘0’AND B=‘0’THEN
S <= ‘0’AFTER10ns; C <= ‘0’AFTER
10ns;
ELSEIFA=‘0’AND B=‘1’THEN
S <= ‘1’AFTER10ns;
C <= ‘0’AFTER10ns; ELSEIFA=‘1’
AND B=‘0’THEN
S <= ‘1’AFTER10ns; C <= ‘0’AFTER
10ns;
ELSEIF A=‘1’AND B=‘1’THEN
S <= ‘0’AFTER10ns;
C <= ‘1’AFTER10ns;
ENDIF;
END PROCESS; END BEHAVE_HA;
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• Using Data Flow Architecture withselected signal
assignment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_AIS
PORT (A, B: IN STD_LOGIC; S, C: OUT STD_LOGIC); END H_A;
ARCHITECTURE HA_DFSS OF H_AIS
BEGIN
HA_X <= A & B; HA_Y <= C & S;
WITH HA_X SELECT
HA_Y <= “00” WHEN “00”,
“01” WHEN “01”,
“01” WHEN “10”,
“10” WHEN “11”;
END HA_DFSS;
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Examples of VHDLCode
• Arithmetic Circuits in VHDL:
– Consider the half subtractorcircuit
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• Using StructuralArchitecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUTSTD_LOGIC);
END H_S;
ARCHITECTURE HS_STR OF H_S IS COMPONENT
XOR2
PORT (X, Y: IN STD_LOGIC; Z: OUT STD_LOGIC); END
COMPONENT;
COMPONENTAND2
PORT (P, Q: IN STD_LOGIC; R: OUT STD_LOGIC);
END COMPONENT; COMPONENT
NOT2
PORT (M: IN STD_LOGIC; N: OUT STD_LOGIC); END
COMPONENT;
SIGNAL BB: BIT;
BEGIN
X1: XOR2 PORT MAP(A,B,DIFF); X2: NOT2 PORT
MAP (A,AA);
X3: AND2 PORT MAP(AA,B,BORROW); END HS_STR;
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• Using Data FlowArchitecture:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC); END
H_S;
ARCHITECTURE HS_DF OF H_S IS
BEGIN
DIFF <= A XOR B AFTER10ns;
BORROW <= ((NOT A) AND B) AFTER5ns; END
HS_DF;
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• Using Behavioural Modeling
ENTITY H_S IS PORT(A, B: IN BIT;
DIFF, BORROW: OUT BIT); END H_S;
ARCHITECTUER BEHAVE_HS OF H_S IS
BEGIN
PROSESS (A, B) BEGIN
IF A=‘0’AND B=‘0’THEN
DIFF <= ‘0’AFTER 10ns; BORROW <= ‘0’
AFTER10ns;
ELSEIFA=‘0’AND B=‘1’THEN
DIFF <= ‘1’AFTER10ns;
BORROW <= ‘1’AFTER10ns; ELSEIFA=‘1’
AND B=‘0’THEN
DIFF <= ‘1’AFTER 10ns; BORROW <= ‘0’
AFTER10ns;
ELSEIF A=‘1’AND B=‘1’THEN
DIFF <= ‘0’AFTER10ns;
BORROW <= ‘0’AFTER10ns;
ENDIF;
END PROCESS; END BEHAVE_HS;
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• Using Data Flow Architecture with selected
signal assignment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_S IS
PORT (A, B: IN STD_LOGIC; DIFF, BORROW: OUT STD_LOGIC); END H_S;
ARCHITECTURE HS_DFSS OF H_S IS
BEGIN
HA_X <= A & B;
HA_Y <= BORROW & DIFF; WITH HA_X
SELECT
HA_Y <= “00” WHEN “00”,
“11” WHEN “01”,
“01” WHEN “10”,
“00” WHEN “11”;
END HS_DFSS;
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Examples of VHDLCode
• Multiplexers in VHDL:
– Consider the 4:1 multiplexercircuit
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• Using CASE statement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX IS
PORT( I3: IN STD_LOGIC_VECTOR(1 DOWNTO 0); I2: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); I1: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); I0: IN
STD_LOGIC_VECTOR(1 DOWNTO 0); S:IN
STD_LOGIC_VECTOR(1 DOWNTO 0); O:OUT
STD_LOGIC_VECTOR(1 DOWNTO 0));
END MUX;
ARCHITECTURE BEHV1 OF MUX IS
BEGIN
PROCESS(I3,I2,I1,I0,S) BEGIN
-- USE CASE STATEMENT CASE S IS
WHEN "00" => O <= I0; WHEN "01"
=> O <= I1; WHEN "10" => O <= I2;
WHEN "11" => O <=I3;
WHEN OTHERS => O <= "ZZ"; END CASE;
END PROCESS; END BEHV1;
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Examples of VHDLCode
• Decoder in VHDL:
– Consider the 2:4 decodercircuit
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• Using Sequential Architecture model
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER24 IS
PORT( A, B, EN:IN STD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 TO 3));
END DECODER24;
ARCHITECTURE BEHV_DEC OF DECODER24 IS BEGIN
-- PROCESS STATEMENT
PROCESS (A, B, EN)
VARIABLE AB, BB: STD_LOGIC;
BEGIN
AB := NOTA; BB := NOT B;
IF EN = ‘1’THEN
Z(3) <= NOT(AAND B); Z(2) <= NOT
(AB AND B); Z(1) <= NOT (AAND BB);
Z(0) <= NOT (AB AND BB);
ELSE
Z <= “1111”;
END IF;
END PROCESS;
END BEHV_DEC;
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• Using CASE Statement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER24 IS
PORT( A, B, EN:INSTD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 to 3));
END DECODER24;
ARCHITECTURE BEHV_DEC2 OF DECODER24 IS SIGNAL AB
: STD_LOGIC_VECTOR (1 DOWN TO 0); BEGIN
AB <= A & B; PROCESS (AB, EN)
BEGIN
IF EN = ‘1’THEN
CASE AB IS
WHEN "00" => Z <= “1110";
WHEN "01" => Z <= “1101“; WHEN OTHERS
=> Z <= “1011“;
END CASE; ELSE Z <= “1111";
END IF;
END PROCESS END
BEHV_DEC2;
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• Using Selected signal AssignmentStatement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER24 IS
PORT( A, B, EN:INSTD_LOGIC;
Z:OUT STD_LOGIC_VECTOR(0 TO 3)); END
DECODER24;
ARCHITECTURE BEHV_DEC2 OF DECODER24 IS SIGNAL
ENAB : STD_LOGIC_VECTOR (2 DOWN TO 0); BEGIN
ENAB <= EN & A &B; WITH
ENAB SELECT
Z <= “1110” WHEN “100”,
“1101” WHEN “101”,
“1011” WHEN “110”,
“0111” WHEN “111”;
“1111” WHEN OTHERS; END
BEHV_DEC2;
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Examples of VHDLCode
• Priority Encoder in VHDL:
– Consider the Decimal to BCD Priority Encodercircuit
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• Using Conditional Signal AssignmentStatement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0)); END
PRIORITY_ENCODER;
ARCHITECTURE BEHV_PE OF PRIORITY_ENCODER IS BEGIN
Y <= “0110” WHEN I(9) = ‘0’ELSE “0111”
WHEN I(8) = ‘0’ELSE
“1000” WHEN I(7) = ‘0’ELSE
“1001” WHEN I(6) = ‘0’ELSE
“1010” WHEN I(5) = ‘0’ELSE
“1011” WHEN I(4) = ‘0’ELSE
“1100” WHEN I(3) = ‘0’ELSE
“1101” WHEN I(2) = ‘0’ELSE
“1110” WHEN I(1) = ‘0’ELSE
“1111” END
BEHV_DEC2;
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• Using Sequential Signal Statement
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRIORITY_ENCODER IS
PORT( I : IN STD_LOGIC_VECTOR(9 DOWN TO0);
Y : OUT STD_LOGIC_VECTOR(3 DOWN TO 0) );
END PRIORITY_ENCODER;
ARCHITECTURE BEHV_PE2 OF PRIORITY_ENCODER IS
BEGIN
PROCESS(I)
BEGIN
IF I(9) = ‘0’THEN Y <= ‘0110’;
ELSEIF I(8) = ‘0’THEN Y <= ‘0111’;
ELSEIF I(7) = ‘0’ THEN Y <= ‘1000’;
ELSEIF I(6) = ‘0’ THEN Y <= ‘1001’;
ELSEIF I(5) = ‘0’ THEN Y <= ‘1010’;
ELSEIF I(4) = ‘0’ THEN Y <= ‘1011’;
ELSEIF I(3) = ‘0’ THEN Y <= ‘1100’;
ELSEIF I(2) = ‘0’ THEN Y <= ‘1101’;
ELSEIF I(1) = ‘0’ THEN Y <= ‘1110’;
ELSE Y <= ‘1111’
END IF; END
PROCESS;
END BEHV_DEC2;
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Examples of VHDL Code
• Comparator in VHDL:
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COMPARATOR IS
PORT( A, B : IN STD_LOGIC_VECTOR(1 DOWN
TO0); AGTB, AEQB, ALTBY : OUT
STD_LOGIC);
END COMPARATOR;
ARCHITECTURE BEHV OF COMPARATOR IS
BEGIN
AGTB <= ‘1’ WHEN A>B ELSE
‘0’; AEQB <= ‘1’ WHEN A=B
ELSE ‘0’; ALTB <= ‘1’ WHEN
A<B ELSE‘0’;
END BEHV;
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Examples of VHDL Code
• BCD to 7-Segment Decoder in VHDL:
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DEC_7_SEG IS
PORT( BCD : IN STD_LOGIC_VECTOR(3 DOWN TO 0);
LED7 : OUT STD_LOGIC_VECTOR(1 TO 7));
END DEC_7_SEG;
ARCHITECTURE BCDTO7SEG OF DEC_7_SEG IS
BEGIN
PROCESS(BCD)
BEGIN
CASE BCD IS
WHEN “0000” => LED7 <= “1111110”;
WHEN “0001” => LED7 <= “0110000”;
WHEN “0010” => LED7 <= “1101101”;
WHEN “0011” => LED7 <= “1111001”;
WHEN “0100” => LED7 <= “0110011”;
WHEN “0101” => LED7 <= “1011011”;
WHEN “0110” => LED7 <= “0011111”;
WHEN “0111” => LED7 <= “1110000”;
WHEN “1000” => LED7 <= “1111111”;
WHEN “1001” => LED7 <= “1110011”;
WHEN OTHERS => LED7 <= “-------”;
END CASE;
END PROCESS;
END BCDTO7SEG;
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Examples of VHDL Code
• Register in VHDL:
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFT4 IS
PORT(DIN:IN STD_LOGIC;
CLOCK, CLEAR:IN STD_LOGIC;
Q:OUT STD_LOGIC(3 DOWN TO 0));
END SHIFT4;
ARCHITECTURE BEHV OF DFF IS
BEGIN
PROCESS(CLEAR, CLOCK)
BEGIN
IF CLEAR ='0' THEN Q <= “0000”;
ELSEIF (CLOCK='1' AND CLOCK'EVENT)THEN
Q(3) <= DIN;
Q(2) <= Q(3);
Q(1) <= Q(2);
Q(1) <= Q(0);
END IF;
END PROCESS;
END BEHV;
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VHDL Code for a 4 - bit Up Counter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;
architecture virat of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;
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VHDL Code for a 4-bit Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dcounter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;
architecture virat of dcounter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end virat;
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