SlideShare a Scribd company logo

Introduction to VHDL

•Download as PPTX, PDF•
•
M
Mohamed Samy

Overview on VHDL Skills gained: 1- VHDL History and usage 2- VHDL design flow 3- Understand concurrency This is part of VHDL 360 course

EducationTechnologyDesign
1 of 16
VHDL 360© by: Mohamed Samy Samer El-Saadany
Copyrights Copyright © 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2
Course Prerequisites Digital/Logic design System architecture Computer architecture (is a plus) Software programming (is a plus) 3 VHDL 360 ©
Module 0 Introduction to VHDL
Objective Overview on VHDL Skills gained: VHDL History and usage VHDL design flow Understand concurrency VHDL 360 © 5
6 VHDL Standard Synthesizable VHDL What is VHDL? VHDL is A High level modeling language A model that will be either used to synthesize H/W or just used as a simulation model Only a subset of the language can be used for synthesis VHDL 360 ©
VHDL history ,[object Object],Early 1980s: Developed by U.S. Department of Defense 1987: IEEE Standard 1076 - 87 1993: IEEE Standard 1076 – 93 (New features) 1999: Analog Mixed Signal extension (VHDL-AMS) 2008: IEEE Std 1076 – 2008 (New features) 7 VHDL 360 ©
Uses of VHDL Design representation using different abstraction levels Design documentation Design simulation Design synthesis Design verification 8 VHDL 360 ©
Basic Design Flow 9 DesignEntry Place and Route VHDL 360 © Behavioral Simulation failed Post Place & Route Simulation failed Succeeded Synthesis Succeeded Start Production Post Synthesis Simulation failed Succeeded
Let’s have a quick look at the following model & try to understand the main sections in the code -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY model1 IS PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic); END model1 ; ARCHITECTURErtlOF model1 IS -- This is a comment SIGNAL x :std_logic; SIGNAL y :std_logic; BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y; -- end of line comment ENDrtl; VHDL 360 © Libraries & Packages headers Interface definition (input/output ports) Functional/behavioral Implementation 10
A closer look at the code: “Entity” -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY model1 IS PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic); END model1 ; VHDL 360 © Reusing Library components Packages defining data types & Functions to be used in our code Defining a model with name “model1” Defining the interface ports, their types & their direction model1 11
A closer look at the code: “Architecture” ARCHITECTURErtlOF model1 IS -- This is a comment SIGNAL x :std_logic; SIGNAL y :std_logic; BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y;-- end of line comment ENDrtl; VHDL 360 © Comments start with -- Internal declarations, for example signals used for connections Comments start with -- Assignments relating outputs to inputs 12
Concurrency BEGIN x <= a AND b; y <= c AND d; e <= x OR y; ENDrtl; VHDL 360 © Think Hardware: In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordingly Similarly the value @ y will always change whenever c/d changes It might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently These assignment statements are concurrent, they can be written in any order VHDL is concurrent by nature 13
Simple Exercise: Deduce the logic of the below model -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY exercise1 IS PORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic); END exercise1 ; ARCHITECTUREbehavOF exercise1 IS BEGIN c <= a AND b; s <= a XOR b; ENDbehav; VHDL 360 © 14
Simple Exercise: Deduce the logic of the below model -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY exercise1 IS PORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic); END exercise1 ; ARCHITECTUREbehavOF exercise1 IS BEGIN c <= a AND b; s <= a XOR b; ENDbehav; VHDL 360 © I got it!! This is a Half adder Model 15
Basic Concepts of Digital Design Please revise the following: ,[object Object]

Recommended

Fpga & VHDL
Fpga & VHDLFpga & VHDL
Fpga & VHDLFrancesco De Canio
 
FPGA
FPGAFPGA
FPGARMDAcademicCoordinat
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology TutorialArrow Devices
 
Verilog tutorial
Verilog tutorialVerilog tutorial
Verilog tutorialMaryala Srinivas
 
Actel fpga
Actel fpgaActel fpga
Actel fpgaAnish Gupta
 
HDL (hardware description language) presentation
HDL (hardware description language) presentationHDL (hardware description language) presentation
HDL (hardware description language) presentationDigital Marketing Evangelist
 
Verilog
VerilogVerilog
VerilogMohamed Rayan
 
Xilinx 4000 series
Xilinx 4000 seriesXilinx 4000 series
Xilinx 4000 seriesdragonpradeep
 

Recommended

Fpga & VHDL
Fpga & VHDLFpga & VHDL
Fpga & VHDLFrancesco De Canio
 
FPGA
FPGAFPGA
FPGARMDAcademicCoordinat
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology TutorialArrow Devices
 
Verilog tutorial
Verilog tutorialVerilog tutorial
Verilog tutorialMaryala Srinivas
 
Actel fpga
Actel fpgaActel fpga
Actel fpgaAnish Gupta
 
HDL (hardware description language) presentation
HDL (hardware description language) presentationHDL (hardware description language) presentation
HDL (hardware description language) presentationDigital Marketing Evangelist
 
Verilog
VerilogVerilog
VerilogMohamed Rayan
 
Xilinx 4000 series
Xilinx 4000 seriesXilinx 4000 series
Xilinx 4000 seriesdragonpradeep
 
Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdlRaj Mohan
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clockMantra VLSI
 
VHDL course
VHDL courseVHDL course
VHDL courseIbrahim Mezzah
 
Modules and ports in Verilog HDL
Modules and ports in Verilog HDLModules and ports in Verilog HDL
Modules and ports in Verilog HDLanand hd
 
Hart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation projectHart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation projectMohan Patel
 
Verilog Tasks and functions
Verilog Tasks and functionsVerilog Tasks and functions
Verilog Tasks and functionsVinchipsytm Vlsitraining
 
FPGA Verilog Processor Design
FPGA Verilog Processor DesignFPGA Verilog Processor Design
FPGA Verilog Processor DesignArchana Udaranga
 
AXI Protocol.pptx
AXI Protocol.pptxAXI Protocol.pptx
AXI Protocol.pptxYazan Yousef
 
Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)Dhaval Kaneria
 
Cpld fpga
Cpld fpgaCpld fpga
Cpld fpgaanishgoel
 
TMS320C6X Architecture
TMS320C6X ArchitectureTMS320C6X Architecture
TMS320C6X ArchitectureShweta Tripathi
 
Verilog HDL Training Course
Verilog HDL Training CourseVerilog HDL Training Course
Verilog HDL Training CoursePaul Laskowski
 
Delays in verilog
Delays in verilogDelays in verilog
Delays in verilogJITU MISTRY
 
Unit VI CPLD-FPGA Architecture
Unit VI CPLD-FPGA ArchitectureUnit VI CPLD-FPGA Architecture
Unit VI CPLD-FPGA ArchitecturePrincipal,Guru Nanak Institute of Technology, Nagpur
 
VLSI Lab manual PDF
VLSI Lab manual PDFVLSI Lab manual PDF
VLSI Lab manual PDFUR11EC098
 
VHDL
VHDLVHDL
VHDLAmit Kumar Rathi
 
Data flow model -Lecture-4
Data flow model -Lecture-4Data flow model -Lecture-4
Data flow model -Lecture-4Dr.YNM
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coveragePushpa Yakkala
 
UVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATIONUVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATIONIAEME Publication
 
Unit v. HDL Synthesis Process
Unit v. HDL Synthesis ProcessUnit v. HDL Synthesis Process
Unit v. HDL Synthesis ProcessPrincipal,Guru Nanak Institute of Technology, Nagpur
 
Project
ProjectProject
ProjectJayendra Yadav
 
1.introduction to hd ls
1.introduction to hd ls1.introduction to hd ls
1.introduction to hd lsNational Institute of Electronics and Information Technology
 

More Related Content

What's hot

Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdlRaj Mohan
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clockMantra VLSI
 
Modules and ports in Verilog HDL
Modules and ports in Verilog HDLModules and ports in Verilog HDL
Modules and ports in Verilog HDLanand hd
 
Hart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation projectHart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation projectMohan Patel
 
FPGA Verilog Processor Design
FPGA Verilog Processor DesignFPGA Verilog Processor Design
FPGA Verilog Processor DesignArchana Udaranga
 
Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)Dhaval Kaneria
 
Verilog HDL Training Course
Verilog HDL Training CourseVerilog HDL Training Course
Verilog HDL Training CoursePaul Laskowski
 
Delays in verilog
Delays in verilogDelays in verilog
Delays in verilogJITU MISTRY
 
VLSI Lab manual PDF
VLSI Lab manual PDFVLSI Lab manual PDF
VLSI Lab manual PDFUR11EC098
 
Data flow model -Lecture-4
Data flow model -Lecture-4Data flow model -Lecture-4
Data flow model -Lecture-4Dr.YNM
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coveragePushpa Yakkala
 
UVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATIONUVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATIONIAEME Publication
 

What's hot (20)

Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdl
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clock
 
VHDL course
VHDL courseVHDL course
VHDL course
 
Modules and ports in Verilog HDL
Modules and ports in Verilog HDLModules and ports in Verilog HDL
Modules and ports in Verilog HDL
 
Hart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation projectHart protocol physical and data link layer implementation project
Hart protocol physical and data link layer implementation project
 
Verilog Tasks and functions
Verilog Tasks and functionsVerilog Tasks and functions
Verilog Tasks and functions
 
FPGA Verilog Processor Design
FPGA Verilog Processor DesignFPGA Verilog Processor Design
FPGA Verilog Processor Design
 
AXI Protocol.pptx
AXI Protocol.pptxAXI Protocol.pptx
AXI Protocol.pptx
 
Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)Serial Peripheral Interface(SPI)
Serial Peripheral Interface(SPI)
 
Cpld fpga
Cpld fpgaCpld fpga
Cpld fpga
 
TMS320C6X Architecture
TMS320C6X ArchitectureTMS320C6X Architecture
TMS320C6X Architecture
 
Verilog HDL Training Course
Verilog HDL Training CourseVerilog HDL Training Course
Verilog HDL Training Course
 
Delays in verilog
Delays in verilogDelays in verilog
Delays in verilog
 
Unit VI CPLD-FPGA Architecture
Unit VI CPLD-FPGA ArchitectureUnit VI CPLD-FPGA Architecture
Unit VI CPLD-FPGA Architecture
 
VLSI Lab manual PDF
VLSI Lab manual PDFVLSI Lab manual PDF
VLSI Lab manual PDF
 
VHDL
VHDLVHDL
VHDL
 
Data flow model -Lecture-4
Data flow model -Lecture-4Data flow model -Lecture-4
Data flow model -Lecture-4
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coverage
 
UVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATIONUVM ARCHITECTURE FOR VERIFICATION
UVM ARCHITECTURE FOR VERIFICATION
 
Unit v. HDL Synthesis Process
Unit v. HDL Synthesis ProcessUnit v. HDL Synthesis Process
Unit v. HDL Synthesis Process
 

Viewers also liked

Short.course.introduction.to.vhdl
Short.course.introduction.to.vhdlShort.course.introduction.to.vhdl
Short.course.introduction.to.vhdlRavi Sony
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Amr Rashed
 
Pulse code modulation
Pulse code modulationPulse code modulation
Pulse code modulationNaveen Sihag
 
PULSE CODE MODULATION (PCM)
PULSE CODE MODULATION (PCM)PULSE CODE MODULATION (PCM)
PULSE CODE MODULATION (PCM)vishnudharan11
 

Viewers also liked (12)

Project
ProjectProject
Project
 
1.introduction to hd ls
1.introduction to hd ls1.introduction to hd ls
1.introduction to hd ls
 
Vhdl
VhdlVhdl
Vhdl
 
Short.course.introduction.to.vhdl
Short.course.introduction.to.vhdlShort.course.introduction.to.vhdl
Short.course.introduction.to.vhdl
 
VHDL
VHDLVHDL
VHDL
 
PCM (Pulse Code Modulation)
PCM (Pulse Code Modulation)PCM (Pulse Code Modulation)
PCM (Pulse Code Modulation)
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Introduction to FPGA, VHDL
Introduction to FPGA, VHDL
 
Basics of Vhdl
Basics of VhdlBasics of Vhdl
Basics of Vhdl
 
Pcm
PcmPcm
Pcm
 
Pulse code modulation
Pulse code modulationPulse code modulation
Pulse code modulation
 
PULSE CODE MODULATION (PCM)
PULSE CODE MODULATION (PCM)PULSE CODE MODULATION (PCM)
PULSE CODE MODULATION (PCM)
 
Pulse code modulation
Pulse code modulationPulse code modulation
Pulse code modulation
 

Similar to Introduction to VHDL

Create your first model for a simple logic circuit
Create your first model for a simple logic circuitCreate your first model for a simple logic circuit
Create your first model for a simple logic circuitMohamed Samy
 
Verilog overview
Verilog overviewVerilog overview
Verilog overviewposdege
 
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...New Open Source project at HGI for SmartHome Device Abstraction Templates - A...
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...mfrancis
 
An Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprAn Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprPrabhavathi P
 
Writing more complex models (continued)
Writing more complex models (continued)Writing more complex models (continued)
Writing more complex models (continued)Mohamed Samy
 
Synthesis Examples
Synthesis ExamplesSynthesis Examples
Synthesis ExamplesMohamed Samy
 
Building Hierarchy
Building HierarchyBuilding Hierarchy
Building HierarchyMohamed Samy
 
How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDLEutectics
 
Close encounters in MDD: when Models meet Code
Close encounters in MDD: when Models meet CodeClose encounters in MDD: when Models meet Code
Close encounters in MDD: when Models meet Codelbergmans
 
Close Encounters in MDD: when models meet code
Close Encounters in MDD: when models meet codeClose Encounters in MDD: when models meet code
Close Encounters in MDD: when models meet codelbergmans
 
Pragmatic Model Driven Development using openArchitectureWare
Pragmatic Model Driven Development using openArchitectureWarePragmatic Model Driven Development using openArchitectureWare
Pragmatic Model Driven Development using openArchitectureWareMichael Vorburger
 
Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101Mahmoud Abdellatif
 
Writing more complex models
Writing more complex modelsWriting more complex models
Writing more complex modelsMohamed Samy
 
Data types and Operators Continued
Data types and Operators ContinuedData types and Operators Continued
Data types and Operators ContinuedMohamed Samy
 

Similar to Introduction to VHDL (20)

Create your first model for a simple logic circuit
Create your first model for a simple logic circuitCreate your first model for a simple logic circuit
Create your first model for a simple logic circuit
 
Verilog overview
Verilog overviewVerilog overview
Verilog overview
 
Vhdl new
Vhdl newVhdl new
Vhdl new
 
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...New Open Source project at HGI for SmartHome Device Abstraction Templates - A...
New Open Source project at HGI for SmartHome Device Abstraction Templates - A...
 
An Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprAn Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl ppr
 
Writing more complex models (continued)
Writing more complex models (continued)Writing more complex models (continued)
Writing more complex models (continued)
 
Synthesis Examples
Synthesis ExamplesSynthesis Examples
Synthesis Examples
 
Clean Architecture
Clean ArchitectureClean Architecture
Clean Architecture
 
Building Hierarchy
Building HierarchyBuilding Hierarchy
Building Hierarchy
 
How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDL
 
Close encounters in MDD: when Models meet Code
Close encounters in MDD: when Models meet CodeClose encounters in MDD: when Models meet Code
Close encounters in MDD: when Models meet Code
 
Close Encounters in MDD: when models meet code
Close Encounters in MDD: when models meet codeClose Encounters in MDD: when models meet code
Close Encounters in MDD: when models meet code
 
Pragmatic Model Driven Development using openArchitectureWare
Pragmatic Model Driven Development using openArchitectureWarePragmatic Model Driven Development using openArchitectureWare
Pragmatic Model Driven Development using openArchitectureWare
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
 
Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101
 
Dica ii chapter slides
Dica ii chapter slidesDica ii chapter slides
Dica ii chapter slides
 
Writing more complex models
Writing more complex modelsWriting more complex models
Writing more complex models
 
Report on VLSI
Report on VLSIReport on VLSI
Report on VLSI
 
Data types and Operators Continued
Data types and Operators ContinuedData types and Operators Continued
Data types and Operators Continued
 
Vhdl 1 ppg
Vhdl 1 ppgVhdl 1 ppg
Vhdl 1 ppg
 

Recently uploaded

REMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptxREMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptxDr. Ravikiran H M Gowda
 
OSCM Unit 2_Operations Processes & Systems
OSCM Unit 2_Operations Processes & SystemsOSCM Unit 2_Operations Processes & Systems
OSCM Unit 2_Operations Processes & SystemsSandeep D Chaudhary
 
Simple, Complex, and Compound Sentences Exercises.pdf
Simple, Complex, and Compound Sentences Exercises.pdfSimple, Complex, and Compound Sentences Exercises.pdf
Simple, Complex, and Compound Sentences Exercises.pdfstareducators107
 
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...Amil baba
 
21st_Century_Skills_Framework_Final_Presentation_2.pptx
21st_Century_Skills_Framework_Final_Presentation_2.pptx21st_Century_Skills_Framework_Final_Presentation_2.pptx
21st_Century_Skills_Framework_Final_Presentation_2.pptxJoelynRubio1
 
Play hard learn harder: The Serious Business of Play
Play hard learn harder: The Serious Business of PlayPlay hard learn harder: The Serious Business of Play
Play hard learn harder: The Serious Business of PlayPooky Knightsmith
 
Tatlong Kwento ni Lola basyang-1.pdf arts
Tatlong Kwento ni Lola basyang-1.pdf artsTatlong Kwento ni Lola basyang-1.pdf arts
Tatlong Kwento ni Lola basyang-1.pdf artsNbelano25
 
How to setup Pycharm environment for Odoo 17.pptx
How to setup Pycharm environment for Odoo 17.pptxHow to setup Pycharm environment for Odoo 17.pptx
How to setup Pycharm environment for Odoo 17.pptxCeline George
 
Graduate Outcomes Presentation Slides - English
Graduate Outcomes Presentation Slides - EnglishGraduate Outcomes Presentation Slides - English
Graduate Outcomes Presentation Slides - Englishneillewis46
 
dusjagr & nano talk on open tools for agriculture research and learning
dusjagr & nano talk on open tools for agriculture research and learningdusjagr & nano talk on open tools for agriculture research and learning
dusjagr & nano talk on open tools for agriculture research and learningMarc Dusseiller Dusjagr
 
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptx
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptxOn_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptx
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptxPooja Bhuva
 
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdf
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdfUnit 3 Emotional Intelligence and Spiritual Intelligence.pdf
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdfDr Vijay Vishwakarma
 
Understanding Accommodations and Modifications
Understanding Accommodations and ModificationsUnderstanding Accommodations and Modifications
Understanding Accommodations and ModificationsMJDuyan
 
PANDITA RAMABAI- Indian political thought GENDER.pptx
PANDITA RAMABAI- Indian political thought GENDER.pptxPANDITA RAMABAI- Indian political thought GENDER.pptx
PANDITA RAMABAI- Indian political thought GENDER.pptxakanksha16arora
 
Spellings Wk 4 and Wk 5 for Grade 4 at CAPS
Spellings Wk 4 and Wk 5 for Grade 4 at CAPSSpellings Wk 4 and Wk 5 for Grade 4 at CAPS
Spellings Wk 4 and Wk 5 for Grade 4 at CAPSAnaAcapella
 
Towards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptxTowards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptxJisc
 
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...Pooja Bhuva
 
On National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan FellowsOn National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan FellowsMebane Rash
 

Recently uploaded (20)

REMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptxREMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptx
 
OSCM Unit 2_Operations Processes & Systems
OSCM Unit 2_Operations Processes & SystemsOSCM Unit 2_Operations Processes & Systems
OSCM Unit 2_Operations Processes & Systems
 
Simple, Complex, and Compound Sentences Exercises.pdf
Simple, Complex, and Compound Sentences Exercises.pdfSimple, Complex, and Compound Sentences Exercises.pdf
Simple, Complex, and Compound Sentences Exercises.pdf
 
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
 
21st_Century_Skills_Framework_Final_Presentation_2.pptx
21st_Century_Skills_Framework_Final_Presentation_2.pptx21st_Century_Skills_Framework_Final_Presentation_2.pptx
21st_Century_Skills_Framework_Final_Presentation_2.pptx
 
Play hard learn harder: The Serious Business of Play
Play hard learn harder: The Serious Business of PlayPlay hard learn harder: The Serious Business of Play
Play hard learn harder: The Serious Business of Play
 
Tatlong Kwento ni Lola basyang-1.pdf arts
Tatlong Kwento ni Lola basyang-1.pdf artsTatlong Kwento ni Lola basyang-1.pdf arts
Tatlong Kwento ni Lola basyang-1.pdf arts
 
How to setup Pycharm environment for Odoo 17.pptx
How to setup Pycharm environment for Odoo 17.pptxHow to setup Pycharm environment for Odoo 17.pptx
How to setup Pycharm environment for Odoo 17.pptx
 
Graduate Outcomes Presentation Slides - English
Graduate Outcomes Presentation Slides - EnglishGraduate Outcomes Presentation Slides - English
Graduate Outcomes Presentation Slides - English
 
dusjagr & nano talk on open tools for agriculture research and learning
dusjagr & nano talk on open tools for agriculture research and learningdusjagr & nano talk on open tools for agriculture research and learning
dusjagr & nano talk on open tools for agriculture research and learning
 
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptx
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptxOn_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptx
On_Translating_a_Tamil_Poem_by_A_K_Ramanujan.pptx
 
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdf
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdfUnit 3 Emotional Intelligence and Spiritual Intelligence.pdf
Unit 3 Emotional Intelligence and Spiritual Intelligence.pdf
 
Understanding Accommodations and Modifications
Understanding Accommodations and ModificationsUnderstanding Accommodations and Modifications
Understanding Accommodations and Modifications
 
Our Environment Class 10 Science Notes pdf
Our Environment Class 10 Science Notes pdfOur Environment Class 10 Science Notes pdf
Our Environment Class 10 Science Notes pdf
 
PANDITA RAMABAI- Indian political thought GENDER.pptx
PANDITA RAMABAI- Indian political thought GENDER.pptxPANDITA RAMABAI- Indian political thought GENDER.pptx
PANDITA RAMABAI- Indian political thought GENDER.pptx
 
Spellings Wk 4 and Wk 5 for Grade 4 at CAPS
Spellings Wk 4 and Wk 5 for Grade 4 at CAPSSpellings Wk 4 and Wk 5 for Grade 4 at CAPS
Spellings Wk 4 and Wk 5 for Grade 4 at CAPS
 
Towards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptxTowards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptx
 
VAMOS CUIDAR DO NOSSO PLANETA! .
VAMOS CUIDAR DO NOSSO PLANETA! .VAMOS CUIDAR DO NOSSO PLANETA! .
VAMOS CUIDAR DO NOSSO PLANETA! .
 
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
 
On National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan FellowsOn National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan Fellows
 

Introduction to VHDL

  • 1. VHDL 360© by: Mohamed Samy Samer El-Saadany
  • 2. Copyrights Copyright © 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2
  • 3. Course Prerequisites Digital/Logic design System architecture Computer architecture (is a plus) Software programming (is a plus) 3 VHDL 360 ©
  • 5. Objective Overview on VHDL Skills gained: VHDL History and usage VHDL design flow Understand concurrency VHDL 360 © 5
  • 6. 6 VHDL Standard Synthesizable VHDL What is VHDL? VHDL is A High level modeling language A model that will be either used to synthesize H/W or just used as a simulation model Only a subset of the language can be used for synthesis VHDL 360 ©
  • 7.
  • 8. Uses of VHDL Design representation using different abstraction levels Design documentation Design simulation Design synthesis Design verification 8 VHDL 360 ©
  • 9. Basic Design Flow 9 DesignEntry Place and Route VHDL 360 © Behavioral Simulation failed Post Place & Route Simulation failed Succeeded Synthesis Succeeded Start Production Post Synthesis Simulation failed Succeeded
  • 10. Let’s have a quick look at the following model & try to understand the main sections in the code -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY model1 IS PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic); END model1 ; ARCHITECTURErtlOF model1 IS -- This is a comment SIGNAL x :std_logic; SIGNAL y :std_logic; BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y; -- end of line comment ENDrtl; VHDL 360 © Libraries & Packages headers Interface definition (input/output ports) Functional/behavioral Implementation 10
  • 11. A closer look at the code: “Entity” -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY model1 IS PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic); END model1 ; VHDL 360 © Reusing Library components Packages defining data types & Functions to be used in our code Defining a model with name “model1” Defining the interface ports, their types & their direction model1 11
  • 12. A closer look at the code: “Architecture” ARCHITECTURErtlOF model1 IS -- This is a comment SIGNAL x :std_logic; SIGNAL y :std_logic; BEGIN -- This is another comment x <= a AND b; y <= c AND d; e <= x OR y;-- end of line comment ENDrtl; VHDL 360 © Comments start with -- Internal declarations, for example signals used for connections Comments start with -- Assignments relating outputs to inputs 12
  • 13. Concurrency BEGIN x <= a AND b; y <= c AND d; e <= x OR y; ENDrtl; VHDL 360 © Think Hardware: In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordingly Similarly the value @ y will always change whenever c/d changes It might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently These assignment statements are concurrent, they can be written in any order VHDL is concurrent by nature 13
  • 14. Simple Exercise: Deduce the logic of the below model -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY exercise1 IS PORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic); END exercise1 ; ARCHITECTUREbehavOF exercise1 IS BEGIN c <= a AND b; s <= a XOR b; ENDbehav; VHDL 360 © 14
  • 15. Simple Exercise: Deduce the logic of the below model -- LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY exercise1 IS PORT( a :INstd_logic; b :INstd_logic; c :OUTstd_logic; s :OUTstd_logic); END exercise1 ; ARCHITECTUREbehavOF exercise1 IS BEGIN c <= a AND b; s <= a XOR b; ENDbehav; VHDL 360 © I got it!! This is a Half adder Model 15
  • 16.
  • 18. Level vs. Edge triggered
  • 22. Please revise the following (Logic gates, multiplexers, decoders, counters, adders, multipliers, shift registers, all types of flip flops)16 VHDL 360 ©