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March 25, 2006 Reconfigurable Computing Dr. Partha Pratim Das Head of Engineering, Interra Systems (India) Pvt. Ltd.   Emerging Architectures for Embedded Systems
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Source & Disclaimer ,[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Setting the Stage What are Embedded Systems? & Why Reconfigurable Computing for them?
What are Embedded Systems? ,[object Object],[object Object]
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Reconfigurable Computing

  • 1. March 25, 2006 Reconfigurable Computing Dr. Partha Pratim Das Head of Engineering, Interra Systems (India) Pvt. Ltd. Emerging Architectures for Embedded Systems
  • 2.
  • 3.
  • 4.
  • 5. Setting the Stage What are Embedded Systems? & Why Reconfigurable Computing for them?
  • 6.
  • 8.
  • 9.
  • 10. Embedded Systems Market Segments Source: The Death of the DSP by Nick Tredennick www.qstech.com , August 2000
  • 11.
  • 12.
  • 13.
  • 14.
  • 15. YF-22
  • 17.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26.
  • 27.
  • 29.
  • 30.
  • 31.
  • 32.
  • 33.
  • 34.
  • 35.
  • 36.
  • 37.
  • 38.
  • 39. Reconfigurable Architectures Case Study of New Computing Machines
  • 40.
  • 41. D-Fabrix Array Elixent Source : DFA1000 RISC Accelerator Data Sheet & Website www.elixent.com
  • 42.
  • 43.
  • 44. Basic D-Fabrix Array Element ALU 4 4 1 Typical instructions: A + B Cin ? A:B A - B A == B A & B A > B A | B not A A xor B not B INSTR 4 A B C IN /CONTROL C OUT 1 4 F Output register options: Transparent Reset: 0000, 1111 Clocked: always, when enabled, never REG
  • 45.
  • 46.
  • 47. D-Fabrix: Routing 16 4-bit busses cross each ALU horizontally and vertically for short and long connections M 4-bit connections are made by setting a configuration bit to ‘1’ Each ALU connects to 8 others via just one switch delay Under 128 configuration bits per ALU+switchbox => Can configure 512 ALUs (64 kbits) in ~20  s
  • 48.
  • 49. DFA 1000: D-Fabrix based RISC Accelerator
  • 50.
  • 51.
  • 52. DFA 1000: Applications & Benchmarks 200Mpixel/second (two macro-blocks in parallel) JPEG Encoder 400Mpixels/sec (four 8x8 DCTs in parallel) 8x8 DCT (16 image lines in parallel) Dither 400Mpixels/sec Floyd-Steinberg Color ~1024 Voice channels UMTS Viterbi 400Msample/sec 5th Order CIC Filter
  • 53.
  • 54.
  • 55. ACM – Adaptive Computing Machine Based on SRGA – Self-Reconfigurable Gate Array Architecture QuickSilver Source: A Self-Reconfigurable Gate Array Architecture , Reetinder Sidhu et al, 10th International Workshop on Field Programmable Logic and Applications, August 2000 . A look into QuickSilver's ACM architecture, Paul Master, CTO QuickSilver, EE Times, September 12, 2002 (4:39 p.m. EST) Website www.qstech.com
  • 56.
  • 57.
  • 58.
  • 59.
  • 60.
  • 61.
  • 63.
  • 64. XPP: eXtreme Processing Platform Pact Corp Source: The XPP White Paper www.pactcorp.com
  • 65.
  • 66. XPP: How it Works
  • 67.
  • 68. XPP: Configurations – Vector * Matrix
  • 69.
  • 70. PulseDSP™ Systolix Source : Website www.systolix.com
  • 71.
  • 72.
  • 73.
  • 74.
  • 75.
  • 76. Programming RAP Overview of Development Tools Source : Websites of Respective Companies
  • 77. Summary of Tools CGN16XXX Data Flow Description / C Intelligent Network Processor Software Development Environment (SDE) Cognigine picoArray Signal Flow Description / Embedded C picoTools picoChip XPP Core / NML / System C C, NML (Native Mapping Language) XDS – Software Development Suite, XPP-VC –Vectorizing C-Compiler Pact Corp ACM C + temporal & spatial extensions. Silverware QuickSilver A7S CSoC VHDL / Verilog / Schematic Capture FastChip Development System Triscend PulseDSP cores Schematic Capture Systolix Design System (SDS) Systolix D-Fabrix Verilog / VHDL / Handel-C / MATLAB D-Sign Elixent Target Entry Tools Company
  • 78. D-Sign: Elixent NOM Generator NOM2EOM Converter Synthesis Physical RDA Generator AIM Lib ADM Lib Concorde Macros Optimisations Verilog / VHDL Design De-Compiler Intermediate Design in Verilog / VHDL / XML IDM Lib Library Maker Arch-I Adaptor Bit-twiddling Nibble align AIM ADM IDM PRO rules
  • 79.
  • 80. XDS – XPP Dev. Tool: Pact Corp
  • 81. XPP-VC – XPP C Compiler: Pact Corp
  • 82.
  • 83.
  • 84.

Editor's Notes

  1. [20060325] Changed: Systolix www.systolix.co.uk RadioScape (www.radioscape.com) acquires Systolix: http://www.electronicstalk.com/news/rab/rab109.html [20051023] Dropped: Triscend www.triscend.com This has got acquired by Xilinx in Mar, 2003. Refer: http://www.xilinx.com/prs_rls/xil_corp/0435_triscend_acquisition.htm Xilinx’s solutions in Reconfigurable space is given in: http://www.xilinx.com/products/design_resources/config_sol/grouping/fpga_config.htm [20051024] Dropped: Cognigine www.cognigine.com Cannot find this website in the Internet. There are many references to their work – but all dates to early 2000s only.
  2. RadioScape uses Systolix's DSP expertise to expand its licensable intellectual property portfolio for Layer-1 wireless baseband development. http://www.electronicstalk.com/news/rab/rab109.html
  3. With this platform in place, algorithms are mapped onto the array. This is done by drawing the signal flow across the array - describing it in an HDL such as Verilog, or a higher-level language like Handel-C - or Matlab. Need an 8-bit adder? Use two ALUs. 32-bit adder? 8 ALUs. Perhaps an Add/Compare/Select (ACS) unit? Again, just a few ALUs.