The document details the Dynamic Reconfigurable Resource Array (DRRA), a customizable embedded fabric design targeted at signal processing applications in radio and multimedia. DRRA consists of a computational fabric, memory fabric, and system interface, allowing for application-level customizations and efficient resource management through dynamic partitioning and fine-grained power management. Its industrial evaluation highlights its ability to handle multiple functionalities efficiently, demonstrating computational and silicon efficiency comparable to ASICs.

1. DRRA: Dynamically Reconfigurable Resource Array
DRRA is an customisable embedded coarse grain reconfigurable fabric that targets streaming signal
processing applications in radio and multi-media applications.
DRRA is composed of three components: computational fabric, memory fabric and interface to the
system SOC.
DRRA is a design template whose customized instance is intended to be used as an embedded macro
in a SOC for implementing accelerators and/or DSP sub-systems.
DRRA Fabric with its components
Dynamically created Private Execution partions
Matched with desired and available parallelism
A SOC with
DRRA Fabric
Memory banks
instances
Memory Fabric Instruction NOC System
Industry Standard Interconnect
Packet swtiched Controller
Bus/NOC hybrid
Codec
Data NOC
Circuit Switched Modem
Memory Bus
System Controller
Control Bus
DRRA
accelerator
Streaming
Register Files DRRA
Sub-system
Morphable
datapath unit
Computation Fabric Sequencer
Interconnect
fabric
DRRA’s Unique Features
ASIC-close silicon and computational efficiency
DRRA is a domain specific design using building blocks whose granularity and functionality is matched
with operations in the domain functionality. This gives DRRA computational and silicon efficiencies
close to ASIC.
Software like engineering efficiency
DRRA is fully programmable. This allows the same fabric instance to be re-programmed to cope with
changes in standards, multiple functionalities and also in-field upgrade of software for improvement
and bug-fixes. A Matlab to DRRA configware and an assembler is available.
Dynamic partitions to match the desired and available parallelism
DRRA’s unique interconnect scheme enables dynamic creation of partition with datapaths that are as
wide and deep as desired; this is customisation at application level.
Predictable and Composable
Applications typically run in their own Private Execution partitions (PREX) making DRRA an efficient
and composable system; PREX eliminates the overhead and non-determinism due to sharing.
Pre-characterized regular physical design along with the PREX concept enables early and accurate
prediction of energy, performance and area.

2. Fine Grain Power Management
Clock gating, Power gating and Dynamic Voltage Frequency scaling power managment modes are
available and can apply to an arbitrary PREX enabling a partition to be powered down as soon as the
application is idle. Voltage frequency operating point is also adjusted to a single application rather
than the wort case when multiple applications share a large building block as is typically done in
MPSOCs.
Customisable
DRRA can be customized for a) operand width including floating point numbers, b) ALU and register file
modes, c) dimension of register files and sequencer memories and d) size of comptuation and memory
fabrics. Once an application is mapped, reconfigurability can be selectively sacrificed to further gain
computational and silicon efficiency.
Industrial Case Study
DRRA has been evaluated by a major telecom house for a multi-mode accelerator. Two very different
functionalities 2048 point FFT for LTE and a correlation pool for UMTS standards were mapped to the
same fabric instance. The results have been published in ISCAS 2013 and shown below:
140 0,1
13,8 0,09 0,01
120 18.69% 37.44%
9,9 0,08
11,5 47.70% 38.12%
100
5,7 23.16% 0,07 0,032
Power (mW)
Area (mm2)
3,34 0,06 0,002
80 68,07 18.3%
0,05 0,0134
61,7 0,015 0,0087
60
50,11 0,04 0,0015
0,01
40 0,03
0,02 0,039 0,044
20 43,44 0,03
31,18 31,13 0,01
0 0
Reconfigurable Customized ASIC Reconfigurable Customized ASIC
DRRA DRRA DRRA DRRA
Register File DPU Sequencer Switch Box
Comparison to the Competition