Submit Search
Upload
IRJET- Analysis of Proposed Finfet based Full Adder using CMOS Logic Style
•
0 likes
•
10 views
IRJET Journal
Follow
https://www.irjet.net/archives/V6/i4/IRJET-V6I4861.pdf
Read less
Read more
Engineering
Report
Share
Report
Share
1 of 4
Download now
Download to read offline
Recommended
Gdi cell
Gdi cell
shipra_mishra
Modified Gate Diffusion Input-MGDI
Modified Gate Diffusion Input-MGDI
shubham jha
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...
VLSICS Design
Low insertion loss of surface mount device low pass filter at 700 MHz
Low insertion loss of surface mount device low pass filter at 700 MHz
journalBEEI
Mukherjee2015
Mukherjee2015
Bannoth Madhusudhan
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
IRJET Journal
Reducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select Adder
paperpublications3
Design & development of embedded application
Design & development of embedded application
eSAT Publishing House
Recommended
Gdi cell
Gdi cell
shipra_mishra
Modified Gate Diffusion Input-MGDI
Modified Gate Diffusion Input-MGDI
shubham jha
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...
VLSICS Design
Low insertion loss of surface mount device low pass filter at 700 MHz
Low insertion loss of surface mount device low pass filter at 700 MHz
journalBEEI
Mukherjee2015
Mukherjee2015
Bannoth Madhusudhan
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
IRJET Journal
Reducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select Adder
paperpublications3
Design & development of embedded application
Design & development of embedded application
eSAT Publishing House
Using sigma-delta quantizer Based PI for inductive power transfer systems
Using sigma-delta quantizer Based PI for inductive power transfer systems
International Journal of Power Electronics and Drive Systems
CPLD xc9500
CPLD xc9500
A B Shinde
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
eSAT Journals
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
IRJET Journal
Neel patel paper
Neel patel paper
BECME
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
IOSRJVSP
Design And Verification of AMBA APB Protocol
Design And Verification of AMBA APB Protocol
IJERA Editor
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
Journal Papers
IRJET-K- Band Differential LNA using Gan HEMT
IRJET-K- Band Differential LNA using Gan HEMT
IRJET Journal
40G 100G gigabit ethernet technology overview
40G 100G gigabit ethernet technology overview
MapYourTech
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET Journal
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
Piero Belforte
Seminar on field programmable gate array
Seminar on field programmable gate array
Saransh Choudhary
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
TELKOMNIKA JOURNAL
40120140504012
40120140504012
IAEME Publication
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
IDES Editor
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
IRJET Journal
A review on virtex fpga family from xilinx
A review on virtex fpga family from xilinx
University of Kassel
Ijecet 06 08_003
Ijecet 06 08_003
IAEME Publication
Implementation of cmos 3
Implementation of cmos 3
IAEME Publication
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET Journal
A Low power and area efficient CLA adder design using Full swing GDI technique
A Low power and area efficient CLA adder design using Full swing GDI technique
IJERA Editor
More Related Content
What's hot
Using sigma-delta quantizer Based PI for inductive power transfer systems
Using sigma-delta quantizer Based PI for inductive power transfer systems
International Journal of Power Electronics and Drive Systems
CPLD xc9500
CPLD xc9500
A B Shinde
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
eSAT Journals
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
IRJET Journal
Neel patel paper
Neel patel paper
BECME
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
IOSRJVSP
Design And Verification of AMBA APB Protocol
Design And Verification of AMBA APB Protocol
IJERA Editor
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
Journal Papers
IRJET-K- Band Differential LNA using Gan HEMT
IRJET-K- Band Differential LNA using Gan HEMT
IRJET Journal
40G 100G gigabit ethernet technology overview
40G 100G gigabit ethernet technology overview
MapYourTech
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET Journal
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
Piero Belforte
Seminar on field programmable gate array
Seminar on field programmable gate array
Saransh Choudhary
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
TELKOMNIKA JOURNAL
40120140504012
40120140504012
IAEME Publication
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
IDES Editor
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
IRJET Journal
A review on virtex fpga family from xilinx
A review on virtex fpga family from xilinx
University of Kassel
Ijecet 06 08_003
Ijecet 06 08_003
IAEME Publication
Implementation of cmos 3
Implementation of cmos 3
IAEME Publication
What's hot
(20)
Using sigma-delta quantizer Based PI for inductive power transfer systems
Using sigma-delta quantizer Based PI for inductive power transfer systems
CPLD xc9500
CPLD xc9500
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
Design and implementation of 15 4 compressor using 1-bit semi domino full add...
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
IRJET- Grid Connected Third Harmonic Injection PWM in a Multilevel Invert...
Neel patel paper
Neel patel paper
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
Design And Verification of AMBA APB Protocol
Design And Verification of AMBA APB Protocol
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
IRJET-K- Band Differential LNA using Gan HEMT
IRJET-K- Band Differential LNA using Gan HEMT
40G 100G gigabit ethernet technology overview
40G 100G gigabit ethernet technology overview
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
RTB: BIDIRECTIONAL TRANSCEIVER (ESSCIRC85)
Seminar on field programmable gate array
Seminar on field programmable gate array
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
Joint control of a robotic arm using particle swarm optimization based H2/H∞ ...
40120140504012
40120140504012
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
Design & Simulation of Half Adder Circuit using AVL Technique Based on CMOS T...
A review on virtex fpga family from xilinx
A review on virtex fpga family from xilinx
Ijecet 06 08_003
Ijecet 06 08_003
Implementation of cmos 3
Implementation of cmos 3
Similar to IRJET- Analysis of Proposed Finfet based Full Adder using CMOS Logic Style
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET Journal
A Low power and area efficient CLA adder design using Full swing GDI technique
A Low power and area efficient CLA adder design using Full swing GDI technique
IJERA Editor
Performance evaluation of full adder
Performance evaluation of full adder
IOSRJECE
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...
IRJET Journal
Ce4301462465
Ce4301462465
IJERA Editor
Analysis of FinFET and CNTFET based HybridCMOS Full Adder Circuit
Analysis of FinFET and CNTFET based HybridCMOS Full Adder Circuit
IRJET Journal
www.ijerd.com
www.ijerd.com
IJERD Editor
Designing of Adders and Vedic Multiplier using Gate Diffusion Input
Designing of Adders and Vedic Multiplier using Gate Diffusion Input
IRJET Journal
J010224750
J010224750
IOSR Journals
IRJET - Low Power Design for Fast Full Adder
IRJET - Low Power Design for Fast Full Adder
IRJET Journal
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS
IDES Editor
Ix3416271631
Ix3416271631
IJERA Editor
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET Journal
IRJET- Low Power Adder and Multiplier Circuits Design Optimization in VLSI
IRJET- Low Power Adder and Multiplier Circuits Design Optimization in VLSI
IRJET Journal
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET Journal
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
IRJET Journal
PC Based DC Motor Speed Control using PID for Laboratory
PC Based DC Motor Speed Control using PID for Laboratory
ijtsrd
Monitoring AC Drive by using RS485 & GSM Module
Monitoring AC Drive by using RS485 & GSM Module
RSIS International
IRJET- Simulation of 10nm Double Gate MOSFET using Visual TCAD Tool
IRJET- Simulation of 10nm Double Gate MOSFET using Visual TCAD Tool
IRJET Journal
Harmonic current reduction by using the super lift boost converter for two st...
Harmonic current reduction by using the super lift boost converter for two st...
IJSRED
Similar to IRJET- Analysis of Proposed Finfet based Full Adder using CMOS Logic Style
(20)
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
A Low power and area efficient CLA adder design using Full swing GDI technique
A Low power and area efficient CLA adder design using Full swing GDI technique
Performance evaluation of full adder
Performance evaluation of full adder
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...
IRJET- Performance Evalution of Gate Diffusion Input and Modified Gate Di...
Ce4301462465
Ce4301462465
Analysis of FinFET and CNTFET based HybridCMOS Full Adder Circuit
Analysis of FinFET and CNTFET based HybridCMOS Full Adder Circuit
www.ijerd.com
www.ijerd.com
Designing of Adders and Vedic Multiplier using Gate Diffusion Input
Designing of Adders and Vedic Multiplier using Gate Diffusion Input
J010224750
J010224750
IRJET - Low Power Design for Fast Full Adder
IRJET - Low Power Design for Fast Full Adder
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS
Ix3416271631
Ix3416271631
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET- Low Power Adder and Multiplier Circuits Design Optimization in VLSI
IRJET- Low Power Adder and Multiplier Circuits Design Optimization in VLSI
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
PC Based DC Motor Speed Control using PID for Laboratory
PC Based DC Motor Speed Control using PID for Laboratory
Monitoring AC Drive by using RS485 & GSM Module
Monitoring AC Drive by using RS485 & GSM Module
IRJET- Simulation of 10nm Double Gate MOSFET using Visual TCAD Tool
IRJET- Simulation of 10nm Double Gate MOSFET using Visual TCAD Tool
Harmonic current reduction by using the super lift boost converter for two st...
Harmonic current reduction by using the super lift boost converter for two st...
More from IRJET Journal
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
IRJET Journal
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
IRJET Journal
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
IRJET Journal
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
IRJET Journal
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
IRJET Journal
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
IRJET Journal
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
IRJET Journal
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
IRJET Journal
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
IRJET Journal
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
IRJET Journal
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
IRJET Journal
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
IRJET Journal
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
IRJET Journal
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
IRJET Journal
React based fullstack edtech web application
React based fullstack edtech web application
IRJET Journal
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
IRJET Journal
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
IRJET Journal
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
IRJET Journal
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
IRJET Journal
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
IRJET Journal
More from IRJET Journal
(20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
React based fullstack edtech web application
React based fullstack edtech web application
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Recently uploaded
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
dollysharma2066
UNIT III ANALOG ELECTRONICS (BASIC ELECTRONICS)
UNIT III ANALOG ELECTRONICS (BASIC ELECTRONICS)
Dr SOUNDIRARAJ N
Heart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptx
PoojaBan
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfid
NikhilNagaraju
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
srsj9000
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.ppt
SAURABHKUMAR892774
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentation
GDSCAESB
CCS355 Neural Network & Deep Learning UNIT III notes and Question bank .pdf
CCS355 Neural Network & Deep Learning UNIT III notes and Question bank .pdf
Asst.prof M.Gokilavani
Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...
VICTOR MAESTRE RAMIREZ
Call Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile service
rehmti665
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
9953056974 Low Rate Call Girls In Saket, Delhi NCR
Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024
hassan khalil
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Low Rate Call Girls In Saket, Delhi NCR
Exploring_Network_Security_with_JA3_by_Rakesh Seal.pptx
Exploring_Network_Security_with_JA3_by_Rakesh Seal.pptx
null - The Open Security Community
Churning of Butter, Factors affecting .
Churning of Butter, Factors affecting .
Satyam Kumar
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
Asst.prof M.Gokilavani
pipeline in computer architecture design
pipeline in computer architecture design
ssuser87fa0c1
Concrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptx
KartikeyaDwivedi3
Artificial-Intelligence-in-Electronics (K).pptx
Artificial-Intelligence-in-Electronics (K).pptx
britheesh05
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptx
k795866
Recently uploaded
(20)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
UNIT III ANALOG ELECTRONICS (BASIC ELECTRONICS)
UNIT III ANALOG ELECTRONICS (BASIC ELECTRONICS)
Heart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptx
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfid
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.ppt
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentation
CCS355 Neural Network & Deep Learning UNIT III notes and Question bank .pdf
CCS355 Neural Network & Deep Learning UNIT III notes and Question bank .pdf
Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...
Call Girls Delhi {Jodhpur} 9711199012 high profile service
Call Girls Delhi {Jodhpur} 9711199012 high profile service
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
Exploring_Network_Security_with_JA3_by_Rakesh Seal.pptx
Exploring_Network_Security_with_JA3_by_Rakesh Seal.pptx
Churning of Butter, Factors affecting .
Churning of Butter, Factors affecting .
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
CCS355 Neural Network & Deep Learning Unit II Notes with Question bank .pdf
pipeline in computer architecture design
pipeline in computer architecture design
Concrete Mix Design - IS 10262-2019 - .pptx
Concrete Mix Design - IS 10262-2019 - .pptx
Artificial-Intelligence-in-Electronics (K).pptx
Artificial-Intelligence-in-Electronics (K).pptx
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptx
IRJET- Analysis of Proposed Finfet based Full Adder using CMOS Logic Style
1.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 04 | Apr 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 4085 Analysis of Proposed FinFET Based Full Adder using CMOS Logic Style Harshita Gehlot1, Mohd Ejaz Aslam Lodhi2 1M. Tech. Scholar, Department of ECE, Indira Gandhi Delhi Technical University for Women, Delhi, India 2Assistant Professor, Department of E ECE, Indira Gandhi Delhi Technical University for Women, Delhi, India ------------------------------------------------------------------------***------------------------------------------------------------------------- Abstract - With the innovation in technology, FinFETs are the new emerging transistors that can work in the nanometer range to overcome Short Channel Effects (SCE) as conventional CMOS has Short Channel Effects. The logic styles used for implementation are Gate Diffusion Input (GDI) and Static Energy Recovery Full (SERF) Adder. To improvetheFull Adder architecture many improvements has been made. Hence, in order to reduce the Short Channel Effects, FinFET based Full Adder has proposed. The experiment designs are implemented in CADENCE VIRTUOSO software using 180nm technology GPDK tool kit and performance analyses were done with respect to Power, Delay and Power Delay Product (PDP). Here FinFET Based GDI Adder and FinFET Based SERF Adder results in less switching activity and area due to less number of transistors i.e. 10. The result shows that the power of FinFET SERF Adder is reduced to 58.86 % compared to FinFET GDI Full Adder. The Delay of FinFET SERF Adder is reduced to 24.98% compared to FinFET GDI Full Adder. The PDP of FinFET SERF Adder has reduced to 69.14% compared to FinFET GDI Full Adder. It is evident that the FinFET based SERF Adder using CMOS Logic Style helpful in digital application in respect of portable, reliable, energy efficient, consume low power and perform high speed. Key Words: FinFET, Full Adder, GDI, SERF 1. INTRODUCTION Now a day, modern digital devices are of a great demand in many industrial applications because these devices are portable, reliable, energy efficient, consume low power and perform high speed. The most important feature of modern electronics is low power and energy efficient active block that enables the implementation of long lasting battery operated devices. FinFETs are the new emerging transistors that can work in the nanometer range to overcome these Short Channel Effects and low power FinFET based Full Adder implemented by using CADENCE VIRTUOSO tools in 45nm technology [1]. Study of different full adder cells with two logic styles i.e. FinFET Based one bit Full Adder Cell using Transmission Gate (TG) and CMOS Logic StylesAt10,22and 32nm[2]. Moore’s Law: Gordon Moore: co-founder of Intel. Predicted that the number of transistors per chip would grow exponentially [3]. He has set the pace for our modern digital revolution and utilized that the computing world increases in power and decreases in cost. Ultra Low Power Based one bit Full Adder using different Nanometer Technologies and simulations were done at 45nm, 32nm technologies. [4] Binary addition is the basic operation found in most arithmetic components. Computation needs to be achieved by using area efficient circuits operating at high speed with low power consumption. Addition is the fundamental arithmetic operation and most fundamental arithmetic component of the processor is adder. A full adder is a logical circuit that performs an addition operation on three one-bit binary numbers. Complementary Metal-Oxide- Semiconductor (CMOS) is a technology for constructing integrated circuits. To improve the Full Adder architecture many improvements has been made by researchers. Full adders are fundamental cell in various circuits which is used to perform arithmetic operations and the VLSI design can be addressed at various design levels. Conventional CMOS has Short Channel Effects and difficult in implementation, thereby market demand retarding day by day. Hence, in order to reduce the Short Channel Effects, FinFET based Full Adder using CMOS logic style has been proposed. In this study, The logic styles used for implementation are Gate Diffusion Input (GDI) and Static Energy RecoveryFull (SERF)Adder. Theexperimentdesigns are implemented in CADENCE VIRTUOSO software using 180nm technology GPDK tool kit and performance analyses were done with respect to Power, Delay and Power Delay Product (PDP). 2. CMOS LOGIC STYLES 2.1 Gate Diffusion Input Operation Gate Diffusion Input (GDI) is nothing but Gate Diffusion Input Technique. This type of technique is suitable for lower delay and designing a circuit with reduced power. This is because the technique helps to decreasethetransistorcount when compared with CMOS and other obtainablelowpower methods. [1] Fig-1: Basic GDI Cell [Ref 1]
2.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 04 | Apr 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 4086 GDI Cell method is based on the use of a simple cell asshown in Figure [1]. At a first glance the basic cell reminds the standard CMOS inverter, but there are some important differences: Gate Diffusion Input CELL) contains three inputs – G (common gate input of NMOS and PMOS) P (input to the source/drain of PMOS) N (input to the source/drain of NMOS) Bulks of both NMOS and PMOS are connected to N or P (respectively), so it can be arbitrarily biased atcontrastwith CMOS inverter. This design can implement a wide variety of logic functions using only two transistors. This methodissuitablefordesign of fast, low-power circuits, using a reduced number of transistors, while improving logic level swing and static power characteristics and allowing simple top down design by using small cell library. Fig- 2: GDI CMOS Full Adder [Ref 1] GDI full adder contains three input pins A, B and Cin andtwo output pins sum and Cout. It is built from two XOR gates and one MUX. 2.2 Static Energy Recovery Full Adder (SERF) As an initial step toward designing low power arithmetic circuit modules, we designed a Static Energy Recovery Full (SERF) adder cell module illustrated in Figure.3 The implementation of XOR and XNOR of A and B is done using pass transistor logic and an inverter is to complement the input signal A. This implementation results infasterXOR and XNOR outputs and also ensures that there is a balanceof delays at the output of these gates. This leads to less spurious SUM and Carry signal. The energy recovering logic reuses charge and therefore consumes less power than non- energy recovering logic. [6] . Fig-3: Block Diagram of SERF Adder [Ref 6] In this section, The two new full adders consists of less number of transistors, because of less number of transistors results in less switching activity and area. 3. PROPOSED FinFET BASED FULL ADDER 3.1 FinFET GDI Full Adder The Gate Diffusion Input Technique decreases both delay and power. FinFET GDI full adder consists of three input pins and two output pins. Here we are using shorted gate FinFET according to the modes of operation. The supply voltage is taken as 1.2V for FinFET GDI Adder usingcadence Virtuoso tool at 180nm technology. In FinFET GDI Adder multiplexer is taken as selective input. Multiplexerlookslike an inverter in order to generate the carry expression we definitely use multiplexer. Fig-4: FinFET based GDI Full Adder [Ref 1] FinFET GDI doesn’t achieve full swing because of the threshold voltage loss. Another reason for FinFETGDIadder is taking three inputs without the use of VDD and GND. The Gate Diffusion Input Technique would possibly enrich the tool chest of VLSI Designers. 3.2 FinFET based SERF Adder SERF design, FinFET Based full adder is implemented by using 10 transistors. Here we are using shorted gate FinFET according to the modes of operation. This circuit performs well at higher supply voltages, but the supply voltage is low this circuit fails to work.
3.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 04 | Apr 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 4087 Fig-5: FinFET Based SERF Adder The energy recovering logic reuses charge and therefore consumes less power than non-energy recovering logic. It should be noted that the new SERF adder has no direct path to the ground. The elimination of a path to the ground reduces power consumption. The combination ofnothaving a direct path to ground and the re- application of the load charge to the control gate makes the energy-recovering full adder an energy efficient design. 4. SIMULATION AND RESULTS ANALYSIS All the FinFET based full adders simulations are done using Cadence Virtuoso in 180nm technology with supply voltage of 1.2V for GDI FinFET Full Adder and 1.5V for FinFETbased SERF Adder. Power dissipation, delay and Power delay product (PDP) are measured for differentdesigntechniques. Fig-6: Schematic Diagram for FinFET GDI Full Adder Fig-7: Transient response of Finfet based GDI Full Adder When the input signal is ABCin=”001”, suppose that the circuit is operating at supply voltage VDD=1.2V and the threshold voltage for PMOS and NMOS circuit are -0.33 and 0.34 respectively. In this case, Fig.7 illustrate the problem which is even more degradation at lower supply voltagesfor the circuit. Fig-8: Schematic of Proposed FinFET Based SERF Adder When Cin is high, Cout is charged to supply voltage, but when Cin is low, Cout discharged to threshold voltage of PMOS (Vtp) which is greater than thresholdvoltageofNMOS (Vtn) by using PMOS pass transistor. In this case the Sum signal is dependent on the value of Cin, for instance, if Cin is high, the Sum is equal to difference between supply voltage and threshold voltage cause a problem in sub threshold mode. Fig-9: Transient response of Finfet based SERF Adder This analysis shows the SERF adder is performs poorly at lower supply voltages. When ABCin=”110” and “111” are applied. As seen from Fig (9), when A=1 and B=1, the E node voltage is difference between supply voltage and threshold voltage (Vdd-Vth). Now if Cin is low or logic ‘0’ then Cout= Vdd-2Vth and the Sum signal is going to zero driven by a MOS transistor with its gate connectedtoVdd-Vth.When Cin is equal to ‘1’, Cout is connected to supply voltage (Vdd) and the SUM signal will equal to difference between supply voltage and threshold voltage. Another problem with this design is when input vector AB=”01” or “10” then floating node connected to the ground.
4.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 04 | Apr 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 4088 5. COMPARISON VALUES Table-1: Comparison Values for FinFET GDI Full Adder and Finfet SERF Adder [180nm Technology] PARAMETERS FinFET GDI Adder FinFET SERF Adder Technology 180nm 180nm Supply Voltage 1.2 V 1.5V Power(uW) 13.81 5.68 Delay(ps) 80.92 60.70 PDP 10^-21 1117.50 344.8367 Power consumption and delay time both are lowest for FinFET based SERF Adder. The FinFET based SERF Adder also has very low delay comparisontoFinFETGDI Full Adder whereas FinFET Based SERF Adder has low Power Delay Product. The results show that the PDP of FinFET SERF Adder is reduced to 69.14 % compared toFinFETGDI Full Adder.The Delay of FinFET SERF Adder is reducedto24.98%compared to FinFET GDI Full Adder and the Power of FinFET SERF Adder is reduced to 58.86 % compared to FinFET GDI Full Adder. 6. CONCLUSION In this project, it is revealed that two different Full Adder circuits are implemented by using FinFET based GDI Adder and FinFET based SERF Adder and Simulated in CADENCE VIRTUOSO TOOLS using 180nm Technology with the supply voltage of 1.2 V for FinFET GDI Full Adder and 1.5V for FinFET SERF Adder, however information available such combination using FinFET based SERF Adder. Hereboththe full adders consist of less number of transistors, because of less number of transistors results in less switching activity and area. A broad comparison of all the designs are showing the gradual improvement in respect of reducing power, delay and Power delay product (PDP). Based on analysis of Proposed FinFET Based Full Adder using CMOS Logic Style , it is conclude that the FinFET based SERF Adder usingCMOS Logic Style helpful in digital application in respect of portable, reliable, energy efficient, consume low power and perform high speed. REFERENCES [1] M. Vamsi Prasad, K. Naresh Kumar, “Low Power FinFET Based Full Adder Design”, International Journal of Advanced Research in Computer and Communication Engineering , Vol. 6, Issue8,August 2017, pp.328-335. [2] Shivani Sharma, Gaurav Soni, “Comparison analysis of FinFET based 1-bit full adder cell implemented using different logic styles at 10, 22 and 32nm”, IOSR Journal of VLSI and Signal Processing, Volume 6, Issue 1, Jan.-Feb. 2016,pp.26-35. [3] Sheenu Rana, Rajesh Mehra, “Optimized CMOS Design of Full Adder using 45nm Technology”, International Journal of Computer Applications, Volume 142, No.13, May 2016. [4] Anitesh Sharma, Ravi Tiwari, “Comparative Analysis of Ultra Low Power Based 1-bit Full Adder Using Different Nanometer Technologies”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 4, Issue 11, November 2015, pp.9307-9314. [5] V. Dileep Chowdary, P. K. Prasad Babu, S. Ahmed Basha , M. Sreenivasulu , K. Sudhakar, “Design of Low Power CMOS Adder, Serf, ModifiedSerfAdder”, International Journal of Innovative Science, Engineering & Technology, Vol. 2, Issue 7, July 2015,pp.1-10. [6] S. Arif Basha & C.V. Subhaskara Reddy, “Low Power Highly Optimized Full Adder By Using Different Techniques With 10 Transistors”, International Journal of Engineering Research,VolumeNo.3Issue No: Special 2, March 2014, pp: 95-96 - [7] Debika Chaudhuri, Atanu Nag, Sukanta Bose, “Low Power Full Adder Circuit Implemented In Different Logic”, International Journal ofInnovativeResearch in Science, Engineering and Technology, Volume 3, special issue 6, Feb. 2014,pp.124-129. [8] Richa Saraswatal, Shyam Akashe and Shyam Babu, “Designing and Simulation of Full Adder Cell using FinFET Technique”, Proceedings of 7th International Conference on Intelligent Systems and Control, 2013.
Download now