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IRJET- A Novel Topology for a Single Phase Hyperlevel Inverter using a Single DC Power Source
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1.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1532 A Novel Topology for a Single Phase HyperLevel Inverter using a Single DC Power Source Mohammad Al-Sammak1, Bilal Sulaiman2 1M.Sc.Eng., Dept. of Industrial Automation Engineering, Technical Engineering College, Tartous, Syria 2B.Eng., Dept. of Industrial Automation Engineering, Technical Engineering College, Tartous, Syria -------------------------------------------------------------------------***------------------------------------------------------------------------ Abstract - This paper proposes a new design of a Single DC Source Multilevel inverter (SDCMI) topology as a hyperlevel inverter to reduce the total harmonic distortion of the output voltage and current. This new design converts two buck converters (BC) into a hyperlevel inverter to create n number of levels, the number of these levels can be changed without the need to change thetopologystructure, becausethenumber of levels is controlled by the SPWM switching frequency. This novel topology of the proposed hyperlevel inverter in this paper was designed to produce 1000 level 220V output voltage, 50Hz with a nominal power of 1KW. The mathematical model of the proposed topology has been demonstrated in this paper. Key Words: multilevel; inverter; single phase; reduced switch-count; single DC source. 1. INTRODUCTION Multilevel inverters are becoming industry’s choice because of their reduced voltage stress, capability for generating an almost-sinusoidal voltage, built-in redundancy and other benefits. The general concept of operation of a multilevel inverter (MLI) involves utilizing a higher number of active semiconductor switches to performthepowerconversionin small voltage steps. One clear disadvantage of MLI is the higher number of semiconductor switches required. Furthermore, implementation of conventional MLI topologies requires the control system to be more complex. Another disadvantage of MLI is that the small voltage steps are typically produced by isolated voltage sources or a bank of series capacitors. Isolated voltage sourcesmaynotalways be readily available, and series capacitors require voltage balancing [1]. Recently, a transformer-less buck converter (BC) based H-bridge topology was implemented to obtain variable DC voltage form a single DC source [2]. The disadvantage of this topology is that itrequiresanadditional BC unit. Another topology that converts single DC source multilevel inverter (SDCMI) intoa BCandMLIwasproposed. However, the main disadvantage of this topology is that it is capable of producing a small numberofoutputvoltagelevels with a constant duty cycle over each level time[3].Thenovel topology of the single DC hyperlevel inverter (SDCHI) proposed in this paper offers in terms of number of output voltage levels, a step-based variable duty cycle and a lower total harmonic distortion (THD) for both the voltage and current output waveforms. In this paper, a novel topology is proposed. The proposed topology of the SDCHI exhibits better performance, when compared to similar SDCMI topologies, in terms of the number of switches, current commutation path and voltage stress on the switches. The validity of the proposedtopology is verified by MATLAB®/Simulink® simulations’ results. The rest of the paper is organized as follows: The architecture and principle of operation in Section 2. Comparisons of the discussed topologies are presented in Section 3, and simulation results are presented in Section 4. Finally, conclusions are drawn in Section 5. 2. Architecture and principle of operation 2.1 Architecture The basic architectureof the proposedtopologyofSDCHI, shown in Fig. 1, is based on the basic forward converter, sometimes called a step-down or buck converter topology [5]. The proposedtopologyarchitectureoftheSDCHIconsists of a single DC power source, four unidirectional switches SW1, SW2, SW3, and SW4, two inductors L1 and L2, two capacitors C1 and C2 and two diodes D1 and D2. The proposed topology architectureis capableofgeneratingboth positive and negative polarity output voltage across the load oV . The output voltage value is proportional to the duty cycle of the control signal of SW2 and SW4, while SW1 and SW3 control the polarity of the outputvoltage.SW1andSW2, shown in Fig. 1. are responsible of generating variable positive output voltage, while SW3 and SW4 are responsible of generating variable negative output voltage. SW1 SW3 SW4 D1 D2 L1 L2 R SW2 C1 C2 oV iE Fig -1: Structure of the proposed topology of the SDCHI
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International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1533 2.2 Control System Block Diagram The switches of the SDCHI are driven by the SDCHI control system shown in Fig. 2. This simple control system consists of two main units, the pulse generator unit and the logic unit. The pulse generator unit consists of two comparators (A and B). Comparator A, compares the reference signal with zero voltage, and outputs polarity control signal that is responsible for controlling SW1 and SW3 switches. Since polarity is controlled by comparator A output, comparator B must output a PWM control signal that resembles only the positive phase of the reference signal. Hence, comparator B isa modifiedtypicalPWMgenerator[4] that compares the reference signal that has a certain frequency with a higher frequency saw tooth signal, and outputs the PWM control signal that is responsible for controlling SW2 and SW4 switches. The longer the switch is on, compared to the off periods, the higher the total power supplied to the load. Pulse Generator Logic Unit Polarity Control PWM Control SW1 SW2 SW3 SW4 Ref OSC + _ + _ | u | A B s f D o f Fig -2: SDCHI control system block diagram 2.3 Operation Principle High Side and Low Side Principle of Operation For analysis purposes, it is assumed that components are lossless and the output voltage oV is maintained constant because of the large magnitude of the capacitors C1 and C2 across the output. The input voltage iE is also assumed constant, such that iE ≥ oV . If all the stored energy in the inductor is transferred to the capacitor and the load before the switch is turned back on, operation is termed discontinuous inductor current, since the inductor current has reached zero. If the switch is turnedonbeforethecurrent in the inductor reaches zero, that is, if continuous current flows in the inductor, operation is termed continuous. In this paper, the proposed topology is assumed to operate in continuous inductor current. The proposed topology of the SDCHI operates in a (high side, low side) switching principle. Thus,thearchitecturecan be divided into two parts; the high side part and the low side one. Each of these sides operates in two states, resulting in four overall different states of operation for the proposed topology. These states are shown in Table 1. SW2 PWM SW1 SW3 Reference Signal tD1tSW2 TS tD2tSW4 TSTS TS Active Side High Side Low Side SW4 SW4 TS TS SW2 SW4SW2 t t t t t t t 1, 2L L i 1, 2L Li iI iI 1, 2D DI 1, 2D DI oI o I oI oI o I oI 2 o T o T 1, 2L L i i I 1, 2D D I o I Fig-3: Waveforms of reference signal, PWM switching signals, inductors currents, input current, diodes currents and output current. Table -1: Switching states for the proposed topology Side States SW1 SW2 SW3 SW4 oV High Side 1 1 1 0 0 iE D 2 1 0 0 0 1iE D Low Side 3 0 0 1 1 iE D 4 0 0 1 0 1iE D (a) SW1 SW3 SW4 D2 D4 L1 L2 R SW2 C1 C2 iE oV ON
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International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1534 (b) SW1 SW3 SW4 D2 D4 L1 L2 R SW2 C1 C2 iE OFF oV SW1 SW3 SW4 D2 D4 L1 L2 R SW2 C1 C2 (c) iE oV ON SW1 SW3 SW4 D2 D4 L1 L2 R SW2 C1 C2 (d) iE OFF oV Fig -4: Schematics of switching states (see Table 1). High side part: The transistor SW1 is on and the input voltage iE is chopped by transistor SW2. When SW2 is on (state 1 shown in Fig. 4.a), because the input voltage iE is greater than the load voltage oV , energy is transferred from the DC power source to 1L , C1, and the load. When SW2 is turned off (state 2 shown in Fig. 4.b), stored energy in 1L is transferred via diode D1 to C1 and the load. The high side part shown in Fig. 3. illustrate SDCHI circuit current and switches signal waveforms for period [0, 2oT ], where oT is the period of the reference signal. The inductor 1L current is analyzed first when the switch SW2 is on, then when the switch SW2 is off. When transistor SW2 is turned on for period 2SWt , the difference between the supply voltage iE and the output voltage oV is impressed across 1L . From 1 1V L di dt L i t , the linear current change through the inductor will be 1 11 2 1 L L i o L SW E V i i i t L (1) When SW2 is switched off for the remainder of the switching period, 1 2D S SWt T t , the freewheel diode D1 conducts and oV is impressed across 1L . Thus, using 1V L i t , rearranged 1 2( ) 1 o L S SW V i T t L (2) Equating equations (1) and (2) gives 2 2i o SW o S SWE V t V T t (3) This expression shows that the inductor 1L average voltage is zero, and after rearranging ( o iP P ) 2o i SW i o S V I t D E I T (4) This equation also shows that for a given input voltage, the output voltage isdeterminedbythetransistorconduction duty cycle D and the output is always less than the input voltage. This confirms and validates the original analysis assumption that iE ≥ oV . The voltage transfer function is independent of the load, circuit inductance 1L and capacitance C1. The inductor rms ripple current (and capacitor ripple current in this case) from equations (1) and (2), for continuous inductor current, is given by 1 1 1 1 12 3 2 3 1 1 12 3 oL L r S i S Vi i D T L E D DT L (5) while the inductor total rms current is 2 2 22 1 1 1 2 1 2 1 1 11 1 1 2 3 1 3 L rms L L r L L L LL L i I i I i i i i i (6) The switch and diodeaverage and rms currentsare given by 2SW i OI I DI (7) 2 1SW rms L rmsI Di (8) 1 1D o i oI I I D I (9) 1 11D rms L rmsI Di (10) If the average inductor current, hence output current, is 1LI , then the maximumand minimuminductorcurrentlevels are given by
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International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1535 1 1 1 1 1 1 2 2 1 1 1 2 1 L o L L o S o V i I i I D T L D V R f L (11) and 1 1 1 1 1 1 2 2 1 1 1 2 1 L o L L o S o V i I i I D T L D V R f L (12) respectively, where 1Li is given by equation (1) or (2). The average output current is 1 11 1 2 L LL o oI i i I V R . The output power is therefore 2 oV R which equals the input power, namely 2i i i SWE I E I . Circuit waveforms for continuous inductor current conduction are shown in Fig. 3. Low Side part: The transistor SW3 is on and the input voltage iE is chopped by transistor SW4. When SW4 is on (state 3 shown in Fig. 4.c), because the input voltage iE is greater than the load voltage oV (the output voltage value duringlowsidepart operation is negative due to reverse polarity ), energy is transferred from the DC power source to 2L , C2, and the load. When SW4 is turned off (state 4 shown in Fig. 4.d), stored energy in 2L is transferred via diode D2 to C2 and the load. The high side part shown in Fig. 3. Illustrate SDCHI circuit current and switches signal waveforms for period [ 2oT , oT ]. The inductor 2L current isanalyzedfirstwhentheswitch SW4 is on, then when the switch SW4 is off. When transistor SW4 is turned on for period 4SWt , the difference between the supply voltage iE and the output voltage oV is impressed across 2L . From 2 2V L di dt L i t , the linear current change through the inductor will be 2 22 4 2 L L i o L SW E V i i i t L (13) When SW4 is switched off for the remainder of the switching period, 2 4D S SWt T t , the freewheel diode D2 conducts and oV is impressed across 2L . Thus, using 2V L i t , rearranged 2 4( ) 2 o L S SW V i T t L (14) Equating equations (13) and (14) gives 4 4i o SW o S SWE V t V T t (15) This expression shows that the inductor 2L average voltage is zero, and after rearranging ( o iP P ) 4o i SW i o S V I t D E I T (16) This equation also shows that for a given input voltage, the output voltage isdeterminedbythetransistorconduction duty cycle D and the output is always less than the input voltage. This confirms and validates the original analysis assumption that iE ≥ oV . The voltage transfer function is independent of the load, circuit inductance 2L and capacitance C2. The inductor rms ripple current (and capacitor ripple current in this case)fromequations(13)and (14), for continuous inductor current, is given by 2 2 1 1 22 3 2 3 1 1 22 3 oL L r S i S Vi i D T L E D DT L (17) while the inductor total rms current is 2 2 2 2 22 2 2 2 22 2 22 2 1 2 3 1 3 L L rms L LL r L LL L i i I I i i i i i (18) The switch and diodeaverage and rms currentsare given by 4SW i OI I D I (19) 4 2SW rms L rmsI Di (20) 2 1D o i oI I I D I (21) 2 21D rms L rmsI Di (22) If the average inductor current, hence output current, is 2LI , then the maximumandminimuminductorcurrentlevels are given by 2 2 2 1 1 1 2 2 2 1 1 2 2 L o L L o S o V i I i I D T L D V R f L (23) and 2 2 2 1 1 1 2 2 2 1 1 2 2 L o L L o S o V i I i I D T L D V R f L (24) respectively, where 2Li is givenbyequation(13)or(14). The average output current is 2 22 1 2 L LL o oI i i I V R . The output power is therefore 2 oV R which equals the input power, namely 4i i i SWE I E I . Circuit waveforms for continuous inductor current conduction are shown in Fig. 3.
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International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1536 Form the previous equations, we can determine the output voltage and current equations of the proposed topology of the SDCHI for period [0, oT ] 1 2 0 2 2 o L O o L o T I t I T I t T (25) 0 2 2 o i O o i o T E D t V T E D t T (26) Architecture components calculation Inductor calculation 1o s L V D L f I (27) Capacitor calculation (min) 8 L o s o I C f V (28) 3. Comparison with conventional SDCMI topologies: In this section, the proposed topology is compared to the topologies presented in [2][3].Table2showsthecomparison of conventional SDCMI with the SDCHI. A comparative analysis shows that, when one H-bridge is used, h=1, the SDCHI has a higher number of output voltagelevels.TheTHD of the output voltage of the SDCMI is below 5%. According to the IEEE-519 or IEC 555-2 standard, the THD in the output voltage should be less than five percent[6].WhenonlyoneH- bridge is used (h=1), the proposed SDCLI has the lowest output voltage THD. Therefore, the proposed topology of the SDCHIachieves the most pure sinusoidal voltageandcurrent output waveform. Performance and circuitparametersofthe SDCMI and the proposed topology of the SDCHI are shown in Table 3. Table -2: Comparison of different parameters of the proposed SDCHI with reported SDCMI Ref blockV in volt No. of Levels No. of levels shown in reported study No. of switches h =1 THD % Exp dcV = 12V h = 1 Exp h = 1 [2] >4 dcV > 48 n n 3 to 255 4 <5% [3] 4 dcV 48 n n 13 4 <5% SDCHI 80 dcV 960 n = o s T T n 1000 4 <5% Table -3: Performance and circuit parameters of single phase SDCMI for THD <5 Ref blockV ( dcV = 12V) n othersN [2] >48 21 One DC to DC converter [3] 48 13 Inductor and capacitor SDCHI 960 1000 Two inductors and two capacitors 4. Simulation Results Fig. 5. shows the schematic of the system under study. Simulations were carried out using MATLAB/Simscape (R2017a, The MathWorks Inc., Natick, MA, USA). The semiconductor switches are MOSFETs SCT30N120 with voltage and current ratings of 1200V, 45A. Table 4 lists the specifications of the SDCHI used for simulations. Fig-5: Simulation model of SDCHI Fig-6: Simulation model of control system block Table-4: Parameters for SDCHI simulations Parameter Value Output frequency of 50Hz Switching frequency sf 50KHz DC power source iV 240 V Inductors 1 2,L L 8.33mH Capacitors 1 2,C C 1uF Levels n 1000 Load R 40Ω
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International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 10| October 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1537 Fig. 7. Load voltage and reference signal waveforms of the SDCHI Fig. 8. Load current signal waveform Fig-9: THD of load voltage of the SDCHI Fig-10: THD of load current of the SDCHI 5. Conclusion In this paper, a new inverter topology has been proposed which has superior features over conventional topologies in terms of control requirements,costandreliability.Itisshown that this topology can be a good candidate for converters used in powerapplicationssuchasFACTS,HVDC,PVsystems, UPS, etc. The new feedback control system for the proposed topology, which is based on SPWM control methodhasfewer complexities. The simulation results for a thousand-level inverter of the proposed topology are demonstrated in this paper. The results clearly show that the proposed topology can effectively work as a multilevel inverter with a lower output voltage and current THD. REFERENCES [1] S. Srikanthan and M. K. Mishra, “DC capacitor voltage equalization in neutral clamped inverters for DSTATCOM application,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2768–2775, Aug. 2010. [2] Reddy, B.D., Anish, N.K., Selvan, M.P, Moorthi, S., Embedded control of n-level DC-DC-AC inverter, IEEE Trans. on Power Electronics, 30(2015) 3703-3711. [3] Jiwanjot Singh , Ratna Dahiya , Lalit Mohan Saini,“Single DC Source H-Bridge Topology as A Low Cost Multilevel Inverter for Marine Electric Systems,” Indian Journal of Geo Marine Sciences Vol. 47 (06), June 2018, pp. 1199- 1207. [4] K. Jang-Hwan, S.-K. Sul, and P. N. Enjeti, “A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltage source inverter,”IEEETrans. Ind. Appl., vol. 44, no. 4, pp. 1239–1248,Jul./Aug. 2008. [5] R.W. Erickson, D. Maksimovic, Fundamental of Power Electronic, Kluver Academic Publisher, University of Colorado, USA, 2005. [6] Babaei, E., Hosseini, S.H., New cascaded multilevel inverter topology with minimum number of switches, Energy conversion and management Elsevier,50(2009) 2761-2767. BIOGRAPHIES Mr. Mohammad Al-Sammak, M.Sc.Eng., Industrial Automation Engineering. He is teaching power electronics in Technical Engineering faculty of Tartous University. He has published several researchpapersin well-known journals. Mr. Bilal Sulaiman, B.Eng., Industrial Automation Engineering. Currently studying Master in Technology Management in the Syrian Virtual University (SVU).
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