Modular multilevel converter (MMC) is a relatively new and promising topology for HVDC systems. HVDC systems should remain connected during grid faults and isolate the fault. This paper studies the dynamic performance of transformer-less MMC integrated HVDC systems during unbalanced conditions and asymmetrical grid faults. It proposes a new control technique to improve unbalanced system’s performance. The objective of the proposed controller is eliminating negative and zero sequence currents and to improve the overall performance. The controller calculates zero and negative sequence reference voltages and eliminates zero and negative sequence currents without using any current regulator. Therefore the controller is very fast and robust. The effectiveness of the proposed control technique has been validated by EMTDC /PSCAD simulations.

1. Control of Modular Multilevel Converter based
HVDC Systems During Asymmetrical Grid Faults
Ghazal Falahi
FREEDM Systems Center
Electrical and Computer Engineering Department
North Carolina State University
Raleigh US
Alex Huang
FREEDM Systems Center
Electrical and Computer Engineering Department
North Carolina State University
Raleigh US
Abstract— Modular multilevel converter (MMC) is a relatively
new and promising topology for HVDC systems. HVDC systems
should remain connected during grid faults and isolate the fault.
This paper studies the dynamic performance of transformer-less
MMC integrated HVDC systems during unbalanced conditions
and asymmetrical grid faults. It proposes a new control
technique to improve unbalanced system’s performance. The
objective of the proposed controller is eliminating negative and
zero sequence currents and to improve the overall performance.
The controller calculates zero and negative sequence reference
voltages and eliminates zero and negative sequence currents
without using any current regulator. Therefore the controller is
very fast and robust. The effectiveness of the proposed control
technique has been validated by EMTDC /PSCAD simulations.
Keywords-MMC, HVDC, unbalanced operation, zero-
sequence,negative-sequence.
I. INTRODUCTION
Voltage source converter (VSC) based HVDC is a relatively
new type of transmission system incorporating controllable
switching converters. VSC-HVDC systems can produce active
and reactive power independently, which allows them to
operate with small or no AC support. HVDC systems have
high voltage ratings on both AC and DC sides and multilevel
converters are good candidates to provide high voltage on both
sides of an HVDC system. Among multilevel converters,
modular multilevel converter (MMC) is a fairly new structure
introduced by Marquardt Lesnicar and is a suitable candidate
for VSC based HVDC [1].
HVDC transmission systems should continuously deliver
power. The HVDC interconnection grid codes state that the
converter station must support the grid voltage during faults
by injecting reactive current. Moreover, the faulty side should
be isolated from the healthy side and the system should be
restored to normal operating condition as quickly as possible
[1-4]. Zero and negative sequence components increase
system’s current, which may cause protection devices to
activate. A well-designed control system should keep systems
normal operation and prevent the protection devices from
tripping frequently.
This paper studies the dynamics performance of transformer-
less MMC-HVDC system during unbalanced conditions and
proposes an alternative solution to improve the performance of
the system during faults. This study incorporates modulation
waveform and mathematical calculation of zero and negative
voltage components and modifies the control structure to
eliminate undesired current terms generated due to the fault.
The proposed controller is fast and robust. Furthermore it
eliminates zero and negative current components without
using current regulator or any additional controller.
This paper is organized as follows. Section II covers the MMC
mathematical model and operation principal. Section III
demonstrates MMC-HVDC control, operation, and dynamic
performance. Section IV presents the proposed solution to
eliminate zero sequence and negative sequence during
network transients and faults and compares the results for both
cases with and without the additional controller and section V
concludes the paper.
II. MMC MATHEMATICAL MODEL AND OPERATION
PRINCIPAL
The three-phase MMC converter configuration used in HVDC
applications is shown in Fig. 1. The converter is composed of
three-phase legs each consisting of two arms made by series
connection of some identical half-bridge modules called cells
or sub-modules (SM). The SMs are inserted or bypassed based
on the switching state of the two switching device in each half
bridge. The two switches are complementary and table 1
shows the sub-module output voltage in different switching
states. The currents in phase-k (k=a, b, c) consist of ik-up and ik-
low which are the upper and lower arm current in each phase.
Applying KVL to the arms of the converter yields to the
following:
(1)
(2)

2. (3)
(4)
Where uk is the phase k voltage, u0 is the potential to ground
DC side neutral point and the inductance of each arm equals
2L. The MMC grid connection dynamic is described as
(5)
Control system for the each MMC converter shown in fig. 1
includes four parts [5]:
1. An individual capacitor voltage controller, which keeps the
sub module capacitor voltages on their reference values.
2. The averaging controller that controls the total capacitor
voltages in each leg to follow the reference value which is
2Vdc.
3. The system controller, which controls active and reactive
power. The reference of active power is determined by
network demanded active power or the DC-link voltage
controller. The reference for reactive power is either
determined by ac voltage regulator or by the reactive power
demand.
4. The PWM voltage command generation, which adds up the
output of three mentioned controllers to build the modulation
waveform. The overall control structure is shown in fig. 4. The
ac voltage command or modulation index for each phase is
calculated by adding the output of three mentioned controllers
as shown in the following equations.
(j:1-n) (6)
(j: n+1 - 2n) (7)
The voltage command is normalized by each dc-capacitor
voltage Vcju and compared with a triangular waveform having a
maximum value of unity and minimum value of zero with a
carrier frequency of fc. Carrier shifted PWM modulation
technique is used for switching and carrier waveform of each
cell is phase shifted by 360/n [5].
TABLE I. SWITCHING STATE OF SUB-MODULES
State S1 S2 Vsm
1 ON OFF Vc
2 OFF ON 0
3 OFF OFF 0
Fig. 1: Modular multilevel converter
I. HVDC MMC OPERATION
The single line diagram of an MMC-HVDC system is shown
in fig. 2, which consists of two MMCs connected to the utility
grid on one side and the DC transmission line on the other
side. The DC link voltage in this system is maintained by the
sum of sub-module voltages inserted in the converter leg and
there is no bulky DC link capacitor as in other VSC-HVDC
systems. HVDC transmission systems regulate active and
reactive power by changing the amplitude and phase of the
converter line currents with respect to PCC and there are
usually two control loops to maintain the power control.
The outer controller regulates the power transfer between the
AC and DC systems and the inner or faster controller is
responsible for tracking the references generated by the power
control, DC or AC voltage control loop. MMC 2 is usually the
grid side converter and MMC 1 is the generator side converter.
The main objective of the control system is to keep the DC-
link voltage constant while keeping sinusoidal grid currents.
As soon as a fault occurs due to short circuit or any other issue
in the AC system or in case of unbalance condition in the
network there will be positive, zero and negative sequence
voltages and currents in the system. In HVDC configuration
with transformer, the Y/ transformer eliminates the zero
sequence components. In transformer-less MMC-HVDC
configuration zero sequence component is present in the
voltages, which results in high zero sequence currents. In
addition to zero sequence negative sequence also exists in the
system voltages resulting in negative sequence current flowing
in the system, which deteriorate the performance.
The MMC-HVDC system is simulated in PSCAD/EMTDC for
the parameters presented in table 2. Figs 5 and 6 show the
normal operation of the system under study. The dynamic
performances of the modeled system during power command
reversal is shown in Fig. 5. The active power reversal
command is sent at t=0.4 secs and reactive power is reversed
at t=0.7secs and P1, P2, Q1 and Q2 are plotted. Fig. 6 shows the
step change in DC link reference voltage.
Cell 2
Cell n
Cell (n+1)
Cell (n+2)
Cell 1
Cell (2n)
DC
link
va
vb
vc
DC
link
u0
ia-up
ia-low
Udc/2
Udc/2
ia
ib
ic
2L
2L
2L 2L
2L 2L
La
Lb
Lc
ib-up ic-up
ib-low ic-low
ua
ub
uc
S1
S2
VS
M
V
c

3. Fig.2 HVDC MMC single line diagram
Fig. 3 MMC individual and total capacitor voltage controller
V*ac
PI
i*odref
Vod
iod
PI
i*qref
0Leq
0Leq
ioq
Voq
3dq/abc
System controller
P*ref
PI
V*dc
Vdc
Q*ref
PI
Vac
Fig. 4 power controllers
II. MMC-HVDC SYSYEM OPERATION UNDER FAULTS
Any fault in the MMC-HVDC system leads into to the
changes of series of parameter values therefore faults can be
detected through observing the variables that carry the fault
signatures [7]. To study the performance of the simulated
system and understand the impact of fault on the dynamic
performance, a SLG fault is applied to MMC-HVDC system
on converter 2 side at 0.3 secs. In order to investigate the fault
propagation in the system no additional control is
implemented at this point. PCC voltage and currents become
imbalanced as soon as fault is applied and zero and negative
sequence appear in the system voltages and currents.
During unbalance grid condition the negative-sequence
components will cause the DC link to oscillate at double
fundamental frequency however DC-link voltage oscillations
in MMC-HVDC system is not very significant because the
MMC sub-module capacitors maintain the DC-link voltage.
There is also ripple due to zero-sequence component if the
midpoint DC link is not grounded. Fig. 7 shows the dynamic
response of MMC-HVDC system to changes in rms AC
voltages when the outer loop in side 2 controls the AC rms
voltage and gives the reactive power command to the inner
control loop. The AC voltages are changed from 0.95pu to
1.05 pu at t=0.3 sec and they return to 0.95pu at t=0.4 sec.
Fig 8 shows the performance of the MMC-HVDC system
when SLG fault is applied at converter 2 side. The top plot in
Fig. 8 shows the PCC voltage for three phases. When SLG
fault is applied at t=0.3 sec the PCC voltages and currents
become unbalanced. Fourth and fifth plot from the top show
the zero sequence voltage and current appear in the system
starting 0.3 sec. Negative sequence in the voltages are shown
in the fourth plot.
Fig. 5 Power reversal test
Fig. 6 Step change in DC link voltage
Fig. 7 Dynamic response of MMC-HVDC system to changes in rms AC
voltage
The presence of negative and zero sequence components in the
system weakens the performance and could damage
semiconductors or cause the protection devices to trip
therefore the control system should be modified to eliminate
these components as fast as possible.
PI
Vc*
Vcju
(j=1-2n)
±
-1 :-Ik-up , Ik-low 0
+1 :-Ik-up , Ik-low 0
VBju*
Individual DC voltage controller
PI PI
1/2
Vc*
Vcu
Ik-low
Ik-up
Icir*
Icir
VAu*
Total DC voltage controller 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Activeandreactivepowerside1&2(pu)
P2
Q1
P1
Q2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-1
0
1
2
3
4
5
Time (secs)
Vdc(pu)
Vdc ref
Vdc
0 0.1 0.2 0.3 0.4 0.5 0.6
-1.5
-1
-0.5
0
0.5
1
1.5
Time(sec)
Vabcside2(pu)
Va
Vb
Vc
0.1 0.2 0.3 0.4 0.5 0.6
-2
-1
0
1
2
time (sec)
Q1&Q2(pu)
Q1
Q2
0 0.1 0.2 0.3 0.4 0.5 0.6
-4
-3
-2
-1
0
1
2
3
time(sec)
P1&P2(pu)
P1
P2

4. There are different methods to eliminate zero and negative
sequence components and most of the presented methods
focus on eliminating zero and negative sequence current
components using an additional controller. This paper
proposes an alternative control structure, which is based on
modifying the modulation waveform via adding additional
terms according to measured zero and negative sequence
voltages.
III. PROPOSED CONTROL STRUCTURE
The transformer-less MMC-HVDC simulation results confirm
that during faults or unbalance condition, there are zero and
negative sequence voltages in the system, which cause zero
and negative sequence current to flow in the system. The basic
idea of the proposed control structure is to command the
converter to generate required zero and negative sequence that
matches the zero and negative sequence voltage present in the
system. Adding virtual zero and negative sequence sources to
the system will help reducing zero and negative sequence
currents seen by the VSC during fault or unbalanced
conditions. Figs. 10 and 11 simply illustrate the structure of
the proposed controller. The zero and negative sequence
elimination terms are added to the modulation.
The process of calculating the negative sequence voltage
includes direct measurement and scaling of PCC zero and
negative sequence voltages and forcing the converter
controller to generate the same voltages at its output terminals.
Virtual voltages generated by the converter cancel out the
measured zero and negative voltages in PCC and force the
converter’ negative sequence currents to zero. The calculations
are all done instantly without using current regulator therefore
the controller is very fast.
Time (secs)
Fig. 8 MMC-HVDC system dynamic when SLG fault is applied at PCC2
TABLE II. MMC-HVDC SYSTEM SPECIFICATIONS
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-3
-2
-1
0
1
2
3
PCCvoltages(pu)
Ea
Eb
Ec
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1
0
1
2
3Phasecurrents(pu)
ia
ib
ic
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vdc(pu)
Vdc
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Zerosequencevoltages(pu)
E0a
E0b
E0c
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
Zerosequencecurrent(pu)
izero
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Negativesequencevoltages(pu)
Ea
Eb
Ec
System parameters Values
AC system 138 kV-LL rms
Power 50 MW
Fundamental frequency 60Hz
MMC switching frequency 180Hz
Source inductance Ls 2mH
Arm inductance 7mH
Submodule capacitor 2500uF
DC link voltage 340 KV

5. Fig. 9 Dynamic performance of MMC-HVDC system with proposed control
structure SLG fault applied at 0.3 sec
Fig. 10 Zero and negative sequence calculation
Fig.11 Proposed control structure
Equations (8)-(10) summarize zero and negative sequence
calculations [8-9].
(8)
(9)
= = (10)
Fig. 9 demonstrates the performance of the proposed control
structure in MMC-HVDC system when SLG fault is applied at
0.3 sec. The top plot shows three-phase currents in converter
2 side, which remain balanced after SLG fault is applied. The
id and iq components of the negative sequence current are
displayed in the second plot. Third plot shows the DC link
voltage waveform and fourth plot shows zero sequence current
when the new control structure is applied.
The updated modulation waveform calculation is shown in
Fig. 11 and includes the output of all controllers. The
additional zero and negative sequence elimination terms are
circled in red.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
3Phasecurrentsside2(pu)
ia
ib
ic
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
Id&Iqnegativesequence(pu)
Idneg ref
Idneg
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
1
2
3
4
5
6
Vdc(pu)
Vdc
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.1
-0.05
0
0.05
0.1
Zero-sequencecurrent(pu)
izero
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Ea0,Eb0,Ec0(pu)
E0a
E0b
E0c
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1
-0.5
0
0.5
1
daneg,dbneg,dcneg(pu)
Eaneg
Ebneg
Ecneg
dazero
Zero sequence
calculation dbzero
dczero
n
n
n
Ea
Eb
Ec
Ea0
Eb0
Ec0
daneg
Vcju
Eliminating
zero
sequence
Eliminating
positive
sequence
Vcjv
Vcjw
dbneg
dcneg
n
n
n
VAu*
VBju* Vi/n E/(2n)
Vju* (j=1-n)
dAneg dAzero
VAu*
VBju* Vi/n E/(2n)
Vju* (j=n+1-2n)
dAneg dAzero

6. After updating the control structure, zero and negative
sequence currents are almost zero. The calculated zero and
negative voltages terms that added to the modulation are
shown in Fig 9.
III. CONCLUSION
This paper analyzed the dynamic performance of an MMC-
HVDC system during normal operation and SLG AC fault. In
addition, an alternative control structure was proposed to
eliminate zero and negative sequence currents during faults
and unbalanced conditions. The presented method uses
instantaneous calculated values of negative and zero sequence
and does not use any additional controller thus it is very fast
compared to other solutions that incorporate some type of
controller to eliminate negative and zero sequence. The
control diagram of the recommended algorithm was presented
and PSCAD simulations prove the fast response of the
proposed control structure.
ACKNOWLEDGMENT
This work used ERC shared facilities supported by the
National Science Foundation. The author would also like to
thank Saman Babaei.
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