Design of a Ahuja compensated OTA as an improvement of a poorly performing Miller amplifier.

1. 05 Feb 2017
ANALOG CIRCUIT DESIGN
Amplifier Compensation
TEAM MEMBERS
ANGELO PARISI angelo2.parisi@mail.polimi.it
GUIDO GIUNCHI guido.giunchi@mail.polimi.it
NICOLÒ BONACINA nicolo.bonacina@mail.polimi.it
PAOLO FRIGERIO paolo8.frigerio@mail.polimi.it
PART 1: Miller compensation
As a first step we realize, from a current analysis based
on noise restrictions (leaving the input-to-mirror
overdrives ratio as a parameter), that the
compensation capacitance required is in the range of
700fF - 1.2pF.
We start by setting 𝐶𝑐 to 1pF; in order to achieve a
40MHz GBWP we need a 250µS gm for the input pair.
To remain on the safe side, we consider 𝑉𝑜𝑣,𝑖𝑛=0.21V,
thus requiring 2 ∗ 𝐼𝑖𝑛=52.78µA as total current of the
input stage.
Back to the former parametric noise analysis, we
obtain 0.638 as the ratio of the overdrives, which gives
us the mirror overdrive voltage: 𝑉𝑜𝑣, 𝑚
=0.33V.
From the asymptotic approximated formulas of the
singularities, we derived the expression of the phase
margin as a function of the output and input stage
currents. Choosing about 65°, we obtain an output-to-
first-stage current ratio of 24.4, resulting in an output
stage current of about 643µA.
We thus calculate the aspect ratios of the transistors.
We start taking into account the corner frequency;
neglecting, as a first step, the PMOS input pair
contribution we obtain a starting value for the mirror
cross section, and thus for the length.
We notice a trade-off between noise and phase margin
contribution of the mirror: the additional high
frequency pole (and the nearby zero), given by the
parasitic capacitance at the transdiode drain, moves
down in frequency as we increase the mirror overdrive
to reduce its noise.
Given this trade-off we decide to set all the overdrives
to about 200mV, so that we fix the value of the input
stage current and transistors aspect ratios.
We now need to tune the value of the compensation
capacitance in order to comply with GBWP and phase
margin requirements. This ends the first part of the
design.
The chosen current values are:
𝐼𝑖𝑛=70µA 𝐼𝑜𝑢𝑡=643µA
PART 2: Alternative frequency
compensations
We decide to try all three different compensation
techniques, namely nulling resistor, Ahuja and voltage
buffer.
At the end the Ahuja turns out to be the best solution
in terms of current consumption and area occupation,
as we expected considering the large value of the load
capacitance.
Following, a brief summary of the ensued steps and the
final outcome for each of them.
 NULLING RESISTOR
As a first guess, we try the nulling resistor approach,
since it requires no additional bias current and is able
to provide a LHP zero to compensate for other
singularities.
Regarding this, we set 𝑅 𝑛=2.385kΩ to introduce the
aforementioned zero at 60MHz (more or less on the
second pole). Simulation gives a 65° phase margin. As
we expected, the results confirm that 𝑅 𝑛 adds no noise.
As a quick way to evaluate the parasitic capacitance 𝐶2
effect on the phase we disconnect it from the circuit:
we discover that it reduces phase margin by about 9°.
We operate a parametric analysis on the value of 𝑅 𝑛:
we find out the optimal (i.e: maximum phase margin)
value to be 3.9kΩ. From that we lower the output stage
current making sure to comply with requirements (we
don't modify the first stage).
The final results are:
Currents:
𝐼𝑜𝑢𝑡=174µA, 2 ∗ 𝐼𝑖𝑛=70µA, 𝐼 𝑏𝑖𝑎𝑠=1µA
Total current consumption = 245µA
Output stage area:
PMOS (59.1/0.52) [µm/µm]

2. NMOS (29.55/0.52) [µm/µm]
Total output stage area = 46.1 (µm)²
Bode plot for Nulling Resistor compensation
 AHUJA
First of all, we expect a complex conjugate pole pair to
appear. We decide to place the zero at the same
frequency of the poles, in order to obtain a phase
margin more or less around 90°.
We maximize the phase margin similarly to what we
did for the nulling resistor, this time through a
parametric sweep on the buffer bias current. This way
we can lower the output stage current. Again through
a parametric sweep on the current we are able to
recover 20µA from the previous design.
We could try to lower the input stage current by
lowering the NMOS mirror overdrive voltages: this
would in turn lower the GBWP allowing a smaller value
of the compensation capacitance. In the end we would
face the same problem met during the first phase, so
we decide to keep the input stage as it is (in order not
to worsen noise performance and phase margin).
Bode plot for Ahuja compensation
𝐶𝑐=1.25pF
Buffer:
𝐼 𝑏𝑢𝑓=65µA, (17.15/0.35) [µm/µm], Vgate = 1.35V
Currents:
𝐼𝑜𝑢𝑡=107µA, 2 ∗ 𝐼𝑖𝑛=70µA, 𝐼 𝑏𝑖𝑎𝑠=1µA, 𝐼 𝑏𝑢𝑓=65µA
Total current consumption = 242µA
Output stage area:
PMOS (36.32/0.52) [µm/µm]
NMOS (18.16/0.52) [µm/µm]
Total output stage area = 28.33 (µm)²
Total current consumption and area occupation are
lower than what we can achieve through the nulling
resistor approach.
 VOLTAGE BUFFER
Similarly to Ahuja, we expect a complex conjugate pair:
we place the zero as in the previous case. We also set,
as a starting point, the previously calculated Ahuja
parameters in order to make a comparison.
We obtain a low Q factor, so we have real split poles.
We lower the buffer current to increase the Q factor:
𝑄 = √
𝑔𝑚6
𝑔𝑚 𝐵
𝐶2
𝐶𝐿
and raise as well the output stage current to push them
towards higher frequencies.
In order to have the zero at a frequency larger than the
GBWP, a lower boundary for the buffer current exists at
10 µA. Taking this into account, we set the remaining
values in order to mimic Ahuja performances.
Bode plot for Voltage Buffer compensation
𝐶𝑐=1.25pF
Buffer:
𝐼 𝑏𝑢𝑓=26µA, (3.19/0.35) [µm/µm]
Currents:
𝐼𝑜𝑢𝑡=144µA, 2 ∗ 𝐼𝑖𝑛=69µA, 𝐼 𝑏𝑖𝑎𝑠=1µA, 𝐼 𝑏𝑢𝑓=26µA
Total current consumption = 240µA
Output stage area:
PMOS (48.87/0.52) [µm/µm]
NMOS (24.44/0.52) [µm/µm]
Total output stage area = 38.12 (µm)²

3. FINAL OUTCOME
In the end we choose the Ahuja compensation
technique: it allows a current consumption reduction
from 733µA to 242µA, an overall area reduction from a
total of 578.2(µm)² to a total of 437.3(µm)².
Concerning these parameters the Ahuja is slightly
better than the nulling resistor approach, and it shows
a step response characterized by a lower overshoot
with respect to both the other techniques.
MOS W [µm] L [µm]
M1 43.30 1.50
M2 43.30 1.50
M3 43.30 3.00
M4 43.30 3.00
M5 25.15 0.52
M6 18.16 0.52
M7 36.32 0.52
M8 0.36 0.52
BUFFER 17.15 0.35
Ahuja dimensions
DC gain 80.0 dB
Phase margin 60.3°
UGF 43.9 MHz
GBWP 40.5 MHz
White noise 11.7 nV/√Hz
Corner frequency 9.1kHz
Ahuja performance
FURTHER CONSIDERATIONS
 The buffer branch impedances are directly in parallel
with those of the input stage: the current buffer is a
cascode from an impedance standpoint, so it does not
weigh as much as the "lower" generator does. The two
transistor implementing the current generators would
ultimately result in a fairly larger area that should be
properly taken into account when comparing the Ahuja
and the Voltage buffer, whose performances might
become quite similar (Even if they are well below the
specifications in both cases).
 The above considerations about area consumption
have been made under the assumption that each
component takes up its own compact region on the
Silicon wafer, independently from the others. In a real
design, however, some advanced techniques (e.g.
interdigitated MOS layout or area sharing) will likely
imply a different area at the advantage of a better
performance in terms of non-idealities rejection (e.g.
threshold voltage spread).
 As a figure of merit of our amplifier, we also test each
circuit response to a pulse-like input (1V pulse
centered around 1.5V). We show here the results as a
conclusion to our report.
Slew rate limited (25V/µs), 34% overshoot, 50MHz ripple
Slew rate limited (17.5V/µs),12% overshoot, 63MHz ripple
Slew rate limited (28.7V/µs) in the first two peakings
26% overshoot, 62MHz ripple