This document describes the design and simulation of a two-stage differential operational amplifier (op-amp) integrator in 180nm CMOS technology. It discusses the stability analysis of op-amps using gain and phase margin curves. The circuits were simulated and analyzed at different bias voltages. The unity gain bandwidth of the op-amp was 15MHz at 0.7V and 21MHz at 0.4V, with power consumptions of 7.158mW and 6.998mW respectively. The power of the integrator circuit was 7.844mW when operated at a frequency of 10kHz. Simulation results showed the circuits had positive gain and phase margins, indicating stability.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
IRJET-Design of Charge Pump for PLL with Reduction In Current Mismatch and Va...IRJET Journal
The document describes the design of an improved charge pump circuit for phase locked loops (PLLs) with reduced current mismatch and variation. A current steering topology is used along with a feedback loop and compensation circuit. The proposed charge pump was designed in 180nm CMOS technology and simulated using Cadence. It achieved a current mismatch between 10-21%, flat output current over a 0.514V output voltage variation, and an output voltage swing of 1.525V. This represents an improvement over conventional charge pump designs in terms reducing current variation and extending the output voltage range.
Analysis of a Quasi Resonant Switch Mode Power Supply for Low Voltage Applica...IDES Editor
QRC provides efficient and regulated switch mode
power supplies for robotic and satellite applications. This paper
addresses the enhanced controller techniques for high
frequency isolation based push-pull Quasi Resonant
Converter. This technique is similar to the conventional PI
controller technique but varies only the enhancement
constants to improve the time domain response of the
converter. The proposed converter is designed for low output
voltage and power rating, characteristically 5V and 5 W, with
the comprehension of current design trends towards enhanced
performance. At the primary stage, to validate the design of
the converter, simulation is performed in PSIM for ±50% load
variations. A prototype model of this converter is developed.
The results obtained from the experimental set-up are
presented and analysed in detail. The results reveal the
superiority of the proposed method.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
IRJET - Design and Analysis of a Comparator for ADC in Tanner EDAIRJET Journal
This document describes the design and analysis of comparators for use in flash analog-to-digital converters (ADCs). It discusses several comparator circuit designs including dynamic comparators, latch-track comparators, low voltage comparators, and high-speed comparators. The comparators are simulated in Cadence Virtuoso using a 180nm CMOS technology to compare their power, area, and delay characteristics for optimizing flash ADC design. Key goals in comparator design for flash ADCs include reducing power consumption, area overhead, and increasing conversion speed.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
IRJET-Design of Charge Pump for PLL with Reduction In Current Mismatch and Va...IRJET Journal
The document describes the design of an improved charge pump circuit for phase locked loops (PLLs) with reduced current mismatch and variation. A current steering topology is used along with a feedback loop and compensation circuit. The proposed charge pump was designed in 180nm CMOS technology and simulated using Cadence. It achieved a current mismatch between 10-21%, flat output current over a 0.514V output voltage variation, and an output voltage swing of 1.525V. This represents an improvement over conventional charge pump designs in terms reducing current variation and extending the output voltage range.
Analysis of a Quasi Resonant Switch Mode Power Supply for Low Voltage Applica...IDES Editor
QRC provides efficient and regulated switch mode
power supplies for robotic and satellite applications. This paper
addresses the enhanced controller techniques for high
frequency isolation based push-pull Quasi Resonant
Converter. This technique is similar to the conventional PI
controller technique but varies only the enhancement
constants to improve the time domain response of the
converter. The proposed converter is designed for low output
voltage and power rating, characteristically 5V and 5 W, with
the comprehension of current design trends towards enhanced
performance. At the primary stage, to validate the design of
the converter, simulation is performed in PSIM for ±50% load
variations. A prototype model of this converter is developed.
The results obtained from the experimental set-up are
presented and analysed in detail. The results reveal the
superiority of the proposed method.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
IRJET - Design and Analysis of a Comparator for ADC in Tanner EDAIRJET Journal
This document describes the design and analysis of comparators for use in flash analog-to-digital converters (ADCs). It discusses several comparator circuit designs including dynamic comparators, latch-track comparators, low voltage comparators, and high-speed comparators. The comparators are simulated in Cadence Virtuoso using a 180nm CMOS technology to compare their power, area, and delay characteristics for optimizing flash ADC design. Key goals in comparator design for flash ADCs include reducing power consumption, area overhead, and increasing conversion speed.
Design and Implementation of Single Phase AC-DC Buck-Boost Converter for Powe...IJPEDS-IAES
This paper discusses the Power Factor Correction (PFC) for single phase AC-DC Buck-Boost Converter (BBC) operated in Continuous Conduction Mode (CCM) using inductor average current mode control. The proposed control technique employs Proportional-Integral (PI) controller in the outer voltage loop and the Inductor Average Current Mode Control (IACMC) in the inner current loop for PFC BBC. The IACMC has advantages such as robustness when there are large variations in line voltage and output load. The PI controller is developed by using state space average model of BBC. The simulation of the proposed system with its control circuit is implemented in MatLab/Simulink. The simulation results show a nearly unity power factor can be attained and there is almost no change in power factor when the line frequency is at various ranges. Experimental results are provided to show its validity and feasibility.
PERFORMANCE INVESTIGATION OF ASYMMETRIC MULTILEVEL INVERTER WITH REDUCED SWIT...ecij
This paper investigates the performance of Asymmetric Multilevel Inverter (AMLI) with reduced number of switches for fuel cell applications. The proposed topology generates fifteen-level output with improved spectral quality of the output. Moreover, a novel hybrid modulation strategy based on Variable Amplitude Phase Opposition Disposition (VAPOD) technique is implemented. The proposed topology is powered by PEM fuel cell source which is modeled in MATLAB. The performance parameters such as Total Harmonic Distortion (THD), Weighted THD (WTHD), Harmonic Spread Factor (HSF) and Distortion Factor (DF) are computed to verify the performance of the proposed topology. Circuit simulation studies are carried out in MATLAB/SIMULINK software and the results are verified.
This document presents a design and simulation of a boost converter with input ripple cancellation for applications like fuel cells. It proposes a boost converter with a tapped inductor and ripple cancellation network (RCN) consisting of a small inductor and capacitor. This helps reduce input current ripples compared to a conventional boost converter. The RCN achieves input ripple cancellation by having its inductor current increase as the main inductor current decreases and vice versa. Simulation results show the proposed converter has lower input current ripple while maintaining output voltage regulation through a closed loop controller.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
For the up-coming generations of power-supply systems, the load located area power-supply sources are an effective one, in terms of our requirements: simplicity, integrity, battery-backup, etc. This could follow the Normalization of power factor & Reducing THD% values on input current, which makes us to add an essential to include a power-factor correction unit at supply side in these new typical topologies. This Proposed architecture presents an integrated battery manage system which can also offers PF correction along with Galvanic-Isolation of battery in a humble single structure. [3] The proposed scheme has the reliable characters like increased efficiency, compact circuit and reduced costs associated with a traditional standalone multiple-stages UPS with PFC. This paper addresses the UPS action, the analysis and simulation results of Proposed UPS scheme.
IRJET- Analysis and Implementation of Active Power FiltersIRJET Journal
This document discusses active power filters (APF) which can eliminate harmonics from power systems. It begins with an abstract that describes how APFs can compensate for harmonic currents, power factor, and load imbalance using pulse width modulation to generate the desired output voltage.
The introduction provides background on increasing non-linear loads that distort voltage/current waveforms and introduce harmonics, reducing power factor. APFs are introduced as a solution to compensate for reactive power, regulate voltage, and eliminate harmonics.
The document then classifies APFs based on system topology as shunt, series, or hybrid configurations. It also categorizes them based on the converter as either voltage source inverters or current source
A Five – Level Integrated AC – DC ConverterIJTET Journal
This paper presents the implementation of a new five – level integrated AC – DC converter with high input power factor and reduced input current harmonics complied with IEC1000-3-2 harmonic standards for electrical equipments. The proposed topology is a combination of boost input power factor pre – regulator and five – level DC – DC converter. The single – stage PFC (SSPFC) approach used in this topology is an alternative solution to low – power and cost – effective applications.
This document summarizes research on pulse width modulation (PWM) techniques for three-phase inverters. It describes sinusoidal PWM switching schemes that allow control of output voltage magnitude and frequency. Simulation models of three-phase inverters using sawtooth and triangular carrier waveforms are presented and analyzed. The results show that a sawtooth carrier waveform produces a more appropriate three-phase voltage waveform compared to a triangular carrier waveform. In conclusion, sinusoidal PWM inverters can generate clean sinusoidal output voltages through comparison of reference and carrier signals to control switching.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONSjmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
1) The document discusses operational amplifiers (Op-Amps), including their history, characteristics, and various configurations.
2) Op-Amps have very high gain, high input impedance, and low output impedance. They are often used in amplifier, filter, and instrumentation circuits.
3) There are two main Op-Amp configurations - open loop and closed loop. Open loop has stability issues while closed loop with negative feedback is more commonly used and has advantages like stabilized gain and reduced distortion.
4) Common closed loop Op-Amp circuits include the inverting amplifier, non-inverting amplifier, voltage follower, integrator, and differential amplifier. These are built using negative feedback techniques.
This document summarizes the design of a sigma-delta analog-to-digital converter (ADC) using operational transconductance amplifiers (OTAs). It first describes the basic architecture of a sigma-delta ADC and the role of the OTA. It then presents the design of a two-stage OTA with sleep insertion and leakage feedback techniques to improve parameters such as gain and power consumption. The design is simulated in 0.18μm CMOS technology with a 1.8V supply. Other blocks of the ADC such as the comparator, 1-bit digital-to-analog converter, and integrator are also described along with simulation results showing improvements in power and performance over earlier designs.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
1) The document describes a system for controlling the speed of a CUK converter-fed BLDC motor using a PI controller.
2) A CUK converter is used to provide power to the BLDC motor and PI control is applied to regulate the output voltage of the CUK converter in order to control the motor speed.
3) Simulation results show that the proposed PI controller is able to effectively control the motor speed while maintaining low current ripple and reducing torque ripples.
Improved power quality buck boost converter for SMPSIJECEIAES
In this paper, a Neural Network (NN) controlled Buck-Boost Converter (BBC) based Switched Mode Power Supply (SMPS) for a PC application is proposed. The proposed BBC is analyzed, modeled and designed for the rated load. Generally, the utilization of Multiple Output SMPS (MOSMPS) for PC application introduces Power Quality (PQ) issues in the power system network. Unlike conventional SMPS the proposed NN controlled BBC can accomplish improvement of power quality. The NN controller reduces the Total Harmonic Distortion (THD) of source current below 5%, maintains input side Power Factor (PF) to be nearly unity and improves the output voltage regulation. In the proposed system, NN controller replaces the conventional PI controller and overcomes the drawbacks of the conventional system. The proposed BBC is validated adopting MATLAB/SIMULINK software. The simulation analysis validate that the proposed NN controlled BBC performs better than conventional converter in terms of PQ indices under fluctuating conditions.
This document describes testing of a boost rectifier for a back-to-back converter used in a doubly fed induction generator wind energy system. The design of the back-to-back converter components is explained, including selection of IGBT switches, DC link capacitor, and driver circuits. A 1 kW prototype was fabricated in the laboratory. Testing was performed on the rectifier sections and showed the boosting was obtained as required. A microcontroller was used to generate PWM pulses to control the IGBTs in the boost rectifier. Experimental results demonstrated boosting of the rectified voltages for various input voltages and pulse widths.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS) tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB), 6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of 8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression point
Bridgeless PFC-Modified SEPIC Rectifier With Extended Gain for Universal Inpu...IISTech2015
This document presents a bridgeless PFC-modified SEPIC rectifier topology designed to operate in discontinuous conduction mode for universal input voltage applications. The proposed topology aims to achieve near unity power factor and low total harmonic distortion of the input current. It provides advantages like zero-current turn-on of power switches and simple control circuitry. The performance is compared to a modified full-bridge SEPIC rectifier in terms of efficiency, total harmonic distortion, and power factor. Simulation and hardware results are presented.
Application of Backstepping to the Virtual Flux Direct Power Control of Five-...IJPEDS-IAES
This paper proposes a virtual flux direct power control-space vector modulation combined with backstepping control for three-phase five-level neutral point clamped shunt active power filter. The main goal of the proposed active filtering system is to eliminate the unwanted harmonics and compensate fundamental reactive power drawn from the nonlinear loads. In this study, the voltage-balancing control of four split dc capacitors of the five-level active filter is achieved using five-level space vector modulation with balancing strategy based on the effective use of the redundant switching states of the inverter voltage vectors. The obtained results showed that, the proposed multilevel shunt active power filter with backstepping control can produce a sinusoidal supply current with low harmonic distortion and in phase with the line voltage.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
Design and Implementation of Single Phase AC-DC Buck-Boost Converter for Powe...IJPEDS-IAES
This paper discusses the Power Factor Correction (PFC) for single phase AC-DC Buck-Boost Converter (BBC) operated in Continuous Conduction Mode (CCM) using inductor average current mode control. The proposed control technique employs Proportional-Integral (PI) controller in the outer voltage loop and the Inductor Average Current Mode Control (IACMC) in the inner current loop for PFC BBC. The IACMC has advantages such as robustness when there are large variations in line voltage and output load. The PI controller is developed by using state space average model of BBC. The simulation of the proposed system with its control circuit is implemented in MatLab/Simulink. The simulation results show a nearly unity power factor can be attained and there is almost no change in power factor when the line frequency is at various ranges. Experimental results are provided to show its validity and feasibility.
PERFORMANCE INVESTIGATION OF ASYMMETRIC MULTILEVEL INVERTER WITH REDUCED SWIT...ecij
This paper investigates the performance of Asymmetric Multilevel Inverter (AMLI) with reduced number of switches for fuel cell applications. The proposed topology generates fifteen-level output with improved spectral quality of the output. Moreover, a novel hybrid modulation strategy based on Variable Amplitude Phase Opposition Disposition (VAPOD) technique is implemented. The proposed topology is powered by PEM fuel cell source which is modeled in MATLAB. The performance parameters such as Total Harmonic Distortion (THD), Weighted THD (WTHD), Harmonic Spread Factor (HSF) and Distortion Factor (DF) are computed to verify the performance of the proposed topology. Circuit simulation studies are carried out in MATLAB/SIMULINK software and the results are verified.
This document presents a design and simulation of a boost converter with input ripple cancellation for applications like fuel cells. It proposes a boost converter with a tapped inductor and ripple cancellation network (RCN) consisting of a small inductor and capacitor. This helps reduce input current ripples compared to a conventional boost converter. The RCN achieves input ripple cancellation by having its inductor current increase as the main inductor current decreases and vice versa. Simulation results show the proposed converter has lower input current ripple while maintaining output voltage regulation through a closed loop controller.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
For the up-coming generations of power-supply systems, the load located area power-supply sources are an effective one, in terms of our requirements: simplicity, integrity, battery-backup, etc. This could follow the Normalization of power factor & Reducing THD% values on input current, which makes us to add an essential to include a power-factor correction unit at supply side in these new typical topologies. This Proposed architecture presents an integrated battery manage system which can also offers PF correction along with Galvanic-Isolation of battery in a humble single structure. [3] The proposed scheme has the reliable characters like increased efficiency, compact circuit and reduced costs associated with a traditional standalone multiple-stages UPS with PFC. This paper addresses the UPS action, the analysis and simulation results of Proposed UPS scheme.
IRJET- Analysis and Implementation of Active Power FiltersIRJET Journal
This document discusses active power filters (APF) which can eliminate harmonics from power systems. It begins with an abstract that describes how APFs can compensate for harmonic currents, power factor, and load imbalance using pulse width modulation to generate the desired output voltage.
The introduction provides background on increasing non-linear loads that distort voltage/current waveforms and introduce harmonics, reducing power factor. APFs are introduced as a solution to compensate for reactive power, regulate voltage, and eliminate harmonics.
The document then classifies APFs based on system topology as shunt, series, or hybrid configurations. It also categorizes them based on the converter as either voltage source inverters or current source
A Five – Level Integrated AC – DC ConverterIJTET Journal
This paper presents the implementation of a new five – level integrated AC – DC converter with high input power factor and reduced input current harmonics complied with IEC1000-3-2 harmonic standards for electrical equipments. The proposed topology is a combination of boost input power factor pre – regulator and five – level DC – DC converter. The single – stage PFC (SSPFC) approach used in this topology is an alternative solution to low – power and cost – effective applications.
This document summarizes research on pulse width modulation (PWM) techniques for three-phase inverters. It describes sinusoidal PWM switching schemes that allow control of output voltage magnitude and frequency. Simulation models of three-phase inverters using sawtooth and triangular carrier waveforms are presented and analyzed. The results show that a sawtooth carrier waveform produces a more appropriate three-phase voltage waveform compared to a triangular carrier waveform. In conclusion, sinusoidal PWM inverters can generate clean sinusoidal output voltages through comparison of reference and carrier signals to control switching.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONSjmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
1) The document discusses operational amplifiers (Op-Amps), including their history, characteristics, and various configurations.
2) Op-Amps have very high gain, high input impedance, and low output impedance. They are often used in amplifier, filter, and instrumentation circuits.
3) There are two main Op-Amp configurations - open loop and closed loop. Open loop has stability issues while closed loop with negative feedback is more commonly used and has advantages like stabilized gain and reduced distortion.
4) Common closed loop Op-Amp circuits include the inverting amplifier, non-inverting amplifier, voltage follower, integrator, and differential amplifier. These are built using negative feedback techniques.
This document summarizes the design of a sigma-delta analog-to-digital converter (ADC) using operational transconductance amplifiers (OTAs). It first describes the basic architecture of a sigma-delta ADC and the role of the OTA. It then presents the design of a two-stage OTA with sleep insertion and leakage feedback techniques to improve parameters such as gain and power consumption. The design is simulated in 0.18μm CMOS technology with a 1.8V supply. Other blocks of the ADC such as the comparator, 1-bit digital-to-analog converter, and integrator are also described along with simulation results showing improvements in power and performance over earlier designs.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
1) The document describes a system for controlling the speed of a CUK converter-fed BLDC motor using a PI controller.
2) A CUK converter is used to provide power to the BLDC motor and PI control is applied to regulate the output voltage of the CUK converter in order to control the motor speed.
3) Simulation results show that the proposed PI controller is able to effectively control the motor speed while maintaining low current ripple and reducing torque ripples.
Improved power quality buck boost converter for SMPSIJECEIAES
In this paper, a Neural Network (NN) controlled Buck-Boost Converter (BBC) based Switched Mode Power Supply (SMPS) for a PC application is proposed. The proposed BBC is analyzed, modeled and designed for the rated load. Generally, the utilization of Multiple Output SMPS (MOSMPS) for PC application introduces Power Quality (PQ) issues in the power system network. Unlike conventional SMPS the proposed NN controlled BBC can accomplish improvement of power quality. The NN controller reduces the Total Harmonic Distortion (THD) of source current below 5%, maintains input side Power Factor (PF) to be nearly unity and improves the output voltage regulation. In the proposed system, NN controller replaces the conventional PI controller and overcomes the drawbacks of the conventional system. The proposed BBC is validated adopting MATLAB/SIMULINK software. The simulation analysis validate that the proposed NN controlled BBC performs better than conventional converter in terms of PQ indices under fluctuating conditions.
This document describes testing of a boost rectifier for a back-to-back converter used in a doubly fed induction generator wind energy system. The design of the back-to-back converter components is explained, including selection of IGBT switches, DC link capacitor, and driver circuits. A 1 kW prototype was fabricated in the laboratory. Testing was performed on the rectifier sections and showed the boosting was obtained as required. A microcontroller was used to generate PWM pulses to control the IGBTs in the boost rectifier. Experimental results demonstrated boosting of the rectified voltages for various input voltages and pulse widths.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS) tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB), 6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of 8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression point
Bridgeless PFC-Modified SEPIC Rectifier With Extended Gain for Universal Inpu...IISTech2015
This document presents a bridgeless PFC-modified SEPIC rectifier topology designed to operate in discontinuous conduction mode for universal input voltage applications. The proposed topology aims to achieve near unity power factor and low total harmonic distortion of the input current. It provides advantages like zero-current turn-on of power switches and simple control circuitry. The performance is compared to a modified full-bridge SEPIC rectifier in terms of efficiency, total harmonic distortion, and power factor. Simulation and hardware results are presented.
Application of Backstepping to the Virtual Flux Direct Power Control of Five-...IJPEDS-IAES
This paper proposes a virtual flux direct power control-space vector modulation combined with backstepping control for three-phase five-level neutral point clamped shunt active power filter. The main goal of the proposed active filtering system is to eliminate the unwanted harmonics and compensate fundamental reactive power drawn from the nonlinear loads. In this study, the voltage-balancing control of four split dc capacitors of the five-level active filter is achieved using five-level space vector modulation with balancing strategy based on the effective use of the redundant switching states of the inverter voltage vectors. The obtained results showed that, the proposed multilevel shunt active power filter with backstepping control can produce a sinusoidal supply current with low harmonic distortion and in phase with the line voltage.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
This paper presents an ultralow-power operational amplifier (OpAmp) designed for long-life autonomous portable equipment. The OpAmp uses transistors biased in the subthreshold region to operate on a 0.8V supply with power consumption of only 1.2uW. Simulation results show it achieves 51dB open-loop gain, 57kHz unity-gain frequency, 60° phase margin, and 65dB common-mode rejection ratio for an 8pF load. The OpAmp is implemented in a 0.18um CMOS process and uses a fully differential design with a rail-to-rail input stage and class-AB output stage along with a common-mode feedforward circuit to remove common-mode input
Design of a current Mode Sample and Hold Circuit at sampling rate of 150 MS/sIJERA Editor
A current mode sample and hold circuit is presented in this paper at 180nm technology. The major concerns of
VLSI are area, power, delay and speed. Hence, we have used a MOSFET in triode region in the proposed
architecture for voltage to current conversion instead of a resistor being used in previously proposed circuit. The
proposed circuit achieves high sampling frequency and with more accuracy than the previous one. The
performance of the proposed circuit is depicted in the form of simulation results.
Application of AGPU for Matrix ConvertersIAES-IJPEDS
A simple PI control loop for the matrix converter system is designed in the simulation to maintain a constant output voltage inspite of any disturbance in the source. The single phase matrix converter employs a modified safe- commutation strategy, which results in the elimination of voltage spikes on switches, without the need of a snubber circuit when there is an inductive load being utilized. This is facilitated through the proper switching control algorithm. The sine PWM pulses are generated as switching pulses to the converter to reduce the THD.
Efficient Design of Differential Trans- Conductance Amplifier with Sub-Thresh...IJEEE
This document presents the design of a low voltage differential CMOS transconductance amplifier operating in the sub-threshold region of 0.5V to 1.5V. A 180nm CMOS technology is used in the design on Cadence. Simulation results show the amplifier achieves a maximum differential output at a bias current of 500nA, with a common mode rejection ratio of 88dB and static power consumption of 241nW under normal input conditions. The layout is presented and verified using DRC and LVS tools in Cadence.
Physical designing of low power operational amplifierDevendra Kushwaha
The document provides details about a master's thesis project to design a novel low power operational amplifier. It begins with an introduction to operational amplifiers, describing their basic structure and ideal characteristics. The literature review discusses previous work on designing low power and low noise operational amplifiers using techniques like current driven bulk, Miller compensation, and class AB amplifiers. Key inferences from the literature are that most work has been done on 120nm CMOS technology, noise can be reduced by adjusting transconductance, and cascoded structures provide better gain than cascaded structures. The document outlines the scope of work, methodology, expected outcomes, and software requirements for the thesis project.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
This document describes the design of a low frequency filter using an operational transconductance amplifier (OTA). It begins with an introduction explaining that biomedical signals are usually low frequency (10 mHz to 500 Hz) and require low power and portable equipment. OTA filters can meet these needs. It then discusses OTA circuit design principles and how to simulate a resistor using an OTA. The document presents circuits for simulating a positive floating resistor with one or two OTAs. It describes using these OTA resistor simulations to design an OTA-C low pass filter and shows simulation results validating the theoretical cut-off frequencies achieved by varying the bias current.
Designed a differential input and single ended output high gain (>= 85 dB) operational amplifier using CMOS 0.35um technology using a single independent current source. The amplifier was also designed to achieve a CMRR (>= 80dB), Average Slew Rate (>= 15 V/us), UGF (>= 15 MHz) & Output Voltage Swing ( >= 1.4V). The maximum power dissipation through the complete circuit including the current source branch was limited to 0.3 mW.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
Analysis & Performance of Operational Transconductance Amplifier at 180nm Tec...IRJET Journal
This document summarizes the design and simulation of a two-stage CMOS operational transconductance amplifier (OTA) in 180nm technology. The OTA was designed and simulated using Eldo simulator. DC analysis showed all transistors operating in saturation. AC analysis yielded a gain of 75dB, phase margin of 53.8 degrees, and unity gain bandwidth of 30.5MHz. Transient analysis showed a slew rate of 0.37V/us and settling time of 472ns. The OTA consumes 536.5uW of power under a 1.8V supply. Scaling the supply voltage to 1.5V and 1.2V achieved power savings of 18% and 35% with minor compromises to
Cascaded Multilevel Inverter Based Active Power Filters: A Survey of ControlsIOSR Journals
This document summarizes several control strategies for cascaded multilevel inverter based active power filters, including:
1. P-q theory with PI controller, which calculates real and reactive power to generate reference currents but has errors when voltages are distorted.
2. Average power method with carrier phase shifted PWM, which gives accurate results even with distorted voltages by using a PLL and calculating average power.
3. Instantaneous real-power theory with triangular-sampling current modulator, which generates reference currents to compensate for harmonics and reactive power in real-time using simple calculations. It maintains the DC bus voltage and works for generic power systems.
This document summarizes a research paper on fuzzy control of a multicell converter. It begins with an introduction to stacked multicell converters, which allow sharing of voltage and current stresses across switches. It then discusses the topology and operation of the multicell converter. Sinusoidal pulse width modulation is used to control the output voltage. Fuzzy logic control is then proposed to control the RMS voltage value using MATLAB. Simulation results show that total harmonic distortion is reduced with increasing voltage levels in the multicell converter output waveform. Open and closed loop control of a 6x2 multicell converter are analyzed through MATLAB simulation.
Small Signal Modeling Of Controller For Statcom Used In Distribution System F...IJERA Editor
This document presents a small signal model of a STATCOM (Static Synchronous Compensator) used for reactive power management in a distribution system. A PI controller is designed for the reactive current component of the STATCOM. The model linearizes the nonlinear STATCOM model and performs small signal modeling of the phase angle and modulation index. Simulation results in MATLAB/Simulink show the model with PI controllers can improve the power factor of the grid current for linear inductive loads by adjusting the reactive power output of the STATCOM.
This paper presents the design and performance comparison of a two stage
operational amplifier topology using CMOS and BiCMOS technology. This conventional op
amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and
0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated,
analyzed and performance parameters are compared. The performance parameters such as
gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally,
we conclude the suitability of CMOS technology over BiCMOS technology for low power
RF design.
IRJET- Simulation and Analysis of Five Level SPWM InverterIRJET Journal
This document summarizes the simulation and analysis of a five level single phase pulse width modulation (SPWM) inverter. The inverter circuit is divided into three parts: a gate driver circuit to generate control signals by comparing a triangular carrier wave and reference sine wave, the inverter circuit consisting of four IGBTs in an H-bridge configuration, and an external voltage control circuit to vary the collector-emitter voltage of the IGBTs. Simulation results show that a five level inverter produces a multi stepped output voltage waveform and reduces total harmonic distortion compared to a single level inverter, as determined by fast Fourier transform analysis. Higher level inverters could achieve even lower harmonic distortion.
A novel three phase bidirectional AC buck converter circuit using power
MOSFET is analyzed for input power factor, harmonic profile and efficiency of the
converter for power quality improvement. The equal PWM (EPWM) technique is a used to
increase number of pulses per half cycle (P) in order to vary these parameters. The rms
value of the fundamental component of the output voltage can be increased by varying the
duty ratio (K) of the pulses. It is observed from the simulation results obtained using
MATLAB/simulink that the proposed scheme using EPWM technique significantly reduces
low order harmonics, eliminates certain harmonics for certain values of P, improves input
power factor and hence significantly reduces the filter size of the converter.
Alternating current (AC) electrical drives mainly require smaller current (or torque) ripples and lower total harmonic distortion (THD) of voltage for excellent drive performances. Normally, in practice, to achieve these requirements, the inverter needs to be operated at high switching frequency. By operating at high switching frequency, the size of filter can be reduced. However, the inverter which oftenly employs insulated gate bipolar transistor (IGBT) for high power applications cannot be operated at high switching frequency. This is because, the IGBT switching frequency cannot be operated above 50 kHz due to its thermal restrictions. This paper proposes an alternate switching strategy to enable the use of IGBT for operating the inverter at high switching frequency to improve THD performances. In this strategy, each IGBT in a group of switches in the modified inverter circuit will operate the switching frequency at one-fourth of the inverter switching frequency. The alternate switching is implemented using simple analog and digital integrated circuits.
This document summarizes a research paper that proposes using an artificial neural network tuned by a simulated annealing algorithm for real-time credit card fraud detection. The paper describes how simulated annealing can be used to train the weights of a neural network model to classify credit card transactions as fraudulent or non-fraudulent based on attributes of past transactions. The algorithm is tested on a real-world credit card transaction dataset and is found to effectively classify most transactions correctly, though some misclassifications still occur.
Wireless sensor networks (WSN) have been widely used in various applications.
In these networks nodes collect data from the attached sensors and send their data to a base
station. However, nodes in WSN have limited power supply in form of battery so the nodes
are expected to minimize energy consumption in order to maximize the lifetime of WSN. A
number of techniques have been proposed in the literature to reduce the energy
consumption significantly. In this paper, we propose a new clustering based technique
which is a modification of the popular LEACH algorithm. In this technique, first cluster
heads are elected using the improved LEACH algorithm as usual, and then a cluster of
nodes is formed based on the distance between node and cluster head. Finally, data from
node is transferred to cluster head. Cluster heads forward data, after applying aggregation,
to the cluster head that is closer to it than sink in forward direction or directly to the sink.
This reduction in distance travelled improves the performance over LEACH algorithm
significantly.
This document provides an overview of vertical handover decision strategies in heterogeneous wireless networks. It begins with an introduction to always best connectivity requirements in next generation networks that allow users to move between different network technologies. It then discusses the key aspects of handover management, including the three phases of initiation, decision, and execution. Various criteria for the handover decision process are described, such as received signal strength, network connection time, available bandwidth, power consumption, cost, security, and user preferences. Different types of handover decision strategies are categorized, including those based on network conditions, user preferences, multiple attributes, fuzzy logic/neural networks, and context awareness. The strategies are analyzed and their advantages/disadvantages compared.
In Cognitive Radio Networks (CRN), Cooperative Spectrum Sensing (CSS) is
used to improve performance of spectrum sensing techniques used for detection of licensed
(Primary) user’s signal. In CSS, the spectrum sensing information from multiple unlicensed
(Secondary) users are combined to take final decision about presence of primary signal. The
mixing techniques used to generate final decision about presence of PU’s signal are also
called as Fusion techniques / rules. The fusion techniques are further classified as data
fusion and decision fusion techniques. In data fusion technique all the secondary users
(SUs) share their raw information of spectrum detection like detected energy or other
statistical information, while in decision fusion technique all the SUs take their local
decisions and share the decision by sending ‘0’ or ‘1’ corresponding to absence and presence
of PU’s signal respectively. The rules used in decision fusion techniques are OR rule, AND
rule and K-out-of-N rule. The CSS is further classified as distributed CSS and centralized
CSS. In distributed CSS all the SUs share the spectrum detection information with each
other and by mixing the shared information; all the SUs take final decision individually. In
centralized CSS all the SUs send their detected information to a secondary base station /
central unit which combines the shared information and takes final decision. The secondary
base station shares the final decision with all the SUs in the CRN. This paper covers
overview of information fusion methods used for CSS and analysis of decision fusion rules
with simulation results.
This paper analyzes the impact of network scalability on various physical attributes of Zigbee networks. Simulations were conducted using Qualnet to evaluate the performance of the Zigbee physical layer based on energy consumption and throughput. Energy consumption was analyzed for different modulation schemes (ASK, BPSK, OQPSK), network sizes (2-50 nodes), and clear channel assessment modes. The results showed that OQPSK and ASK had lower energy consumption than BPSK. Throughput was highest for OQPSK. While carrier sense had slightly higher throughput than other CCA modes, the energy consumption differences between CCA modes were minor.
This paper gives a brief idea of the moving objects tracking and its application.
In sport it is challenging to track and detect motion of players in video frames. Task
represents optical flow analysis to do motion detection and particle filter to track players
and taking consideration of regions with movement of players in sports video. Optical flow
vector calculation gives motion of players in video frame. This paper presents improved
Luacs Kanade algorithm explained for optical flow computation for large displacement and
more accuracy in motion estimation.
A rapid progress is seen in the field of robotics both in educational and industrial
automation sectors. The Robotics education in particular is gaining technological advances
and providing more learning opportunities. In automotive sector, there is a necessity and
demand to automate daily human activities by robot. With such an advancement and
demand for robotics, the realization of a popular computer game will help students to learn
and acquire skills in the field of robotics. The computer game such as Pacman offers
challenges on both software and hardware fronts. In software, it provides challenges in
developing algorithms for a robot to escape from the pool of attacking robots and to develop
algorithms for multiple ghost robots to attack the Pacman. On the hardware front, it
provides a challenge to integrate various systems to realize the game. This project aims to
demonstrate the pacman game in real world as well as in simulation. For simulation
purpose Player/Stage is used to develop single-client and multi-client architectures. The
multi- client architecture in player/stage uses one global simulation proxy to which all the
robot models are connected. This reduces the overhead to manage multiple robots proxy.
The single-client architecture enables only two robot models to connect to the simulation
proxy. Multi-client approach offers flexibility to add sensors to each port which will be used
distinctly by the client attached to the respective robot. The robots are named as Pacman
and Ghosts, which try to escape and attack respectively. Use of Network Camera has been
done to detect the global positions of the robots and data is shared through inter-process
communication.
In Content-Based Image Retrieval (CBIR) systems, the visual contents of the
images in the database are took out and represented by multi-dimensional characteristic
vectors. A well known CBIR system that retrieves images by unsupervised method known
as cluster based image retrieval system. For enhancing the performance and retrieval rate
of CBIR system, we fuse the visual contents of an image. Recently, we developed two
cluster-based CBIR systems by fusing the scores of two visual contents of an image. In this
paper, we analyzed the performance of the two recommended CBIR systems at different
levels of precision using images of varying sizes and resolutions. We also compared the
performance of the recommended systems with that of the other two existing CBIR systems
namely UFM and CLUE. Experimentally, we find that the recommended systems
outperform the other two existing systems and one recommended system also comparatively
performed better in every resolution of image.
Information Systems and Networks are subjected to electronic attacks. When
network attacks hit, organizations are thrown into crisis mode. From the IT department to
call centers, to the board room and beyond, all are fraught with danger until the situation is
under control. Traditional methods which are used to overcome these threats (e.g. firewall,
antivirus software, password protection etc.) do not provide complete security to the system.
This encourages the researchers to develop an Intrusion Detection System which is capable
of detecting and responding to such events. This review paper presents a comprehensive
study of Genetic Algorithm (GA) based Intrusion Detection System (IDS). It provides a
brief overview of rule-based IDS, elaborates the implementation issues of Genetic Algorithm
and also presents a comparative analysis of existing studies.
Step by step operations by which we make a group of objects in which attributes
of all the objects are nearly similar, known as clustering. So, a cluster is a collection of
objects that acquire nearly same attribute values. The property of an object in a cluster is
similar to other objects in same cluster but different with objects of other clusters.
Clustering is used in wide range of applications like pattern recognition, image processing,
data analysis, machine learning etc. Nowadays, more attention has been put on categorical
data rather than numerical data. Where, the range of numerical attributes organizes in a
class like small, medium, high, and so on. There is wide range of algorithm that used to
make clusters of given categorical data. Our approach is to enhance the working on well-
known clustering algorithm k-modes to improve accuracy of algorithm. We proposed a new
approach named “High Accuracy Clustering Algorithm for Categorical datasets”.
Brain tumor is a malformed growth of cells within brain which may be
cancerous or non-cancerous. The term ‘malformed’ indicates the existence of tumor. The
tumor may be benign or malignant and it needs medical support for further classification.
Brain tumor must be detected, diagnosed and evaluated in earliest stage. The medical
problems become grave if tumor is detected at the later stage. Out of various technologies
available for diagnosis of brain tumor, MRI is the preferred technology which enables the
diagnosis and evaluation of brain tumor. The current work presents various clustering
techniques that are employed to detect brain tumor. The classification involves classification
of images into normal and malformed (if detected the tumor). The algorithm deals with
steps such as preprocessing, segmentation, feature extraction and classification of MR brain
images. Finally, the confirmatory step is specifying the tumor area by technique called
region of interest.
A Proxy signature scheme enables a proxy signer to sign a message on behalf of
the original signer. In this paper, we propose ECDLP based solution for chen et. al [1]
scheme. We describe efficient and secure Proxy multi signature scheme that satisfy all the
proxy requirements and require only elliptic curve multiplication and elliptic curve addition
which needs less computation overhead compared to modular exponentiations also our
scheme is withstand against original signer forgery and public key substitution attack.
This document proposes a digital watermarking technique using LSB replacement with secret key insertion for enhanced data security. The technique works by inserting a watermark into the least significant bits of pixels in an image. A secret key is also inserted during transmission for additional security. The watermarked image is generated without noticeably impacting image quality. The proposed method was tested on sample images and successfully embedded watermarks while maintaining visual quality. The technique aims to provide copyright protection and authentication of digital images and documents.
Today among various medium of data transmission or storage our sensitive data
are not secured with a third-party, that we used to take help of. Cryptography plays an
important role in securing our data from malicious attack. This paper present a partial
image encryption based on bit-planes permutation using Peter De Jong chaotic map for
secure image transmission and storage. The proposed partial image encryption is a raw data
encryption method where bits of some bit-planes are shuffled among other bit-planes based
on chaotic maps proposed by Peter De Jong. By using the chaotic behavior of the Peter De
Jong map the position of all the bit-planes are permuted. The result of the several
experimental, correlation analysis and sensitivity test shows that the proposed image
encryption scheme provides an efficient and secure way for real-time image encryption and
decryption.
This paper presents a survey of Dependency Analysis of Service Oriented
Architecture (SOA) based systems. SOA presents newer aspects of dependency analysis due
to its different architectural style and programming paradigm. This paper surveys the
previous work taken on dependency analysis of service oriented systems. This study shows
the strengths and weaknesses of current approaches and tools available for dependency
analysis task in context of SOA. The main motivation of this work is to summarize the
recent approaches in this field of research, identify major issue and challenges in
dependency analysis of SOA based systems and motivate further research on this topic.
In this paper, proposed a novel implementation of a Soft-Core system using
micro-blaze processor with virtex-5 FPGA. Till now Hard-Core processors are used in
FPGA processor cores. Hard cores are a fixed gate-level IP functions within the FPGA
fabrics. Now the proposed processor is Soft-Core Processor, this is a microprocessor fully
described in software, usually in an HDL. This can be implemented by using EDK tool. In
this paper, developed a system which is having a micro-blaze processor is the combination
of both hardware & Software. By using this system, user can control and communicate all
the peripherals which are in the supported board by using Xilinx platform to develop an
embedded system. Implementing of Soft-Core process system with different peripherals like
UART interface, SPA flash interface, SRAM interface has to be designed using Xilinx
Embedded Development Kit (EDK) tools.
The article presents a simple algorithm to construct minimum spanning tree and
to find shortest path between pair of vertices in a graph. Our illustration includes the proof
of termination. The complexity analysis and simulation results have also been included.
Wimax technology has reshaped the framework of broadband wireless internet
service. It provides the internet service to unconnected or detached areas such as east South
Africa, rural areas of America and Asia region. Full duplex helpers employed with one of
the relay stations selection and indexing method that is Randomized Distributed Space Time
are used to expand the coverage area of primary Wimax station. The basic problem was
identified at cell edge due to weather conditions (rain, fog), insertion of destruction because
of multiple paths in the same communication channel and due to interference created by
other users in that communication. It is impractical task for the receiver station to decode
the transmitted signal successfully at the cell edges, which increases the high packet loss and
retransmissions. But Wimax is a outstanding technology which is used for improving the
quality of internet service and also it offers various services like Voice over Internet
Protocol, Video conferencing and Multimedia broadcast etc where a little delay in packet
transmission can cause a big loss in the communication. Even setup and initialization of
another Wimax station nearer to each other is not a good alternate, where any mobile
station can easily handover to another base station if it gets a strong signal from other one.
But in rural areas, for few numbers of customers, installation of base station nearer to each
other is costlier task. In this review article, we present a scheme using R-DSTC technique to
choose and select helpers (relay nodes) randomly to expand the coverage area and help to
mobile station as a helper to provide secure communication with base station. In this work,
we use full duplex helpers for better utilization of bandwidth.
Radio Frequency identification (RFID) technology has become emerging
technique for tracking and items identification. Depend upon the function; various RFID
technologies could be used. Drawback of passive RFID technology, associated to the range
of reading tags and assurance in difficult environmental condition, puts boundaries on
performance in the real life situation [1]. To improve the range of reading tags and
assurance, we consider implementing active backscattering tag technology. For making
mobiles of multiple radio standards in 4G network; the Software Defined Radio (SDR)
technology is used. Restrictions in Existing RFID technologies and SDR technology, can be
eliminated by the development and implementation of the Software Defined Radio (SDR)
active backscattering tag compatible with the EPC global UHF Class 1 Generation 2 (Gen2)
RFID standard. Such technology can be used for many of applications and services.
Vehicle technology has increased rapidly in recent years, particularly in relation
to braking system and sensing system. In parallel to the development of braking
technologies, sensors have been developed that are capable of detecting physical obstacles,
other vehicles or pedestrians around the vehicle. This development prevents accidents of
vehicles using Stereo Multi-Purpose cameras, Automated Emergency Braking Systems and
Ultrasonic Sensors. The stereo multi-purpose camera provides spatial intelligence of up to
50 metres in front of the vehicle and there is an environment recognition of 500 metres.
Cars can automatically brake due to obstacles or any hindrance when the sensor senses the
obstacles. The braking circuit function is to brake the car automatically after receiving
signal from the sensors. All cars are competent in applying brakes automatically to a
maximum extent of deceleration of 0.4g. Integrated safety systems are based on three
principles. They are: collision avoidance, collision mitigation braking systems and forward
collision warning.
2. 193
order ∑∆ modulator. At 0.18 μm CMOS technology, the Integrator offers a reduction in power dissipation
(compared with conventional Op-Amp-based Integrators) upto 9.8 μW with an input capacitance of 0.1 pF,
input frequency of 20 kHz and sampling frequency at 500 kHz.
In a CMOS based Op-Amp, circuit techniques that are fully compatible with low-voltage submicron CMOS
processes were addressed to solve the DC Gain issues with unity gain frequency, like Switched-Op-Amps
(SO) [11]–[15] and the Op-Amp-reset Switching Technique (ORST) [16][17]. However, SO circuits face a
tradeoff between speed and accuracy due to slow transients, while ORST stages have higher power
consumption and settling issues due to unity gain feedback during the reset phase [17][18].
Low Power Op-Amp Design with Current Compensation Technique [19] is used to implement a single
output two stage CMOS Op-Amp with at 1.8 V supply voltage and it is designed in 0.18μm CMOS
technology having very low power consumption with a high driving capabilities. The Op-Amp had open loop
gain of 73.57db, the Gain Bandwidth Product (GBW) as 1.094 MHz and 4.35μW power consumption at a
Phase Margin of 65.86º.
Another approach for designing of a low power Op-Amp could be done by using Class AB CMOS Fully
Differential technique [20] in which an Op-Amp has been designed in a low-cost 0.18 μm CMOS technology
with 0.8 V single voltage supply using Cadence Spectre with a BSIM3v3.2. The Op-Amp operates in the sub-
threshold operation which results in ultra low-power consumption and enhanced slew-rate. The Phase Margin
and DC open-loop gain of the Op-Amp with a load capacitance of 10 pF are 65º and 51 dB, while the
simulated unity gain frequency is 40 kHz, with a Phase Margin of 65º degrees. The power consumption of
the Operational Amplifier is 1 μW with a slew-rate of 0.12 V/μs [20].
This work comprises of five sections where section I presents introduction. Section II consists of the design
of two stage Operational Amplifier with an analysis on power and stability. The section II also sheds light on
the Integrator design using two stage differential amplifiers. Section III discusses the simulation of Op-Amp
and Integrator based on the various parameters like operating frequency, Gain Margin, Phase Margin, power
and bandwidth. Finally, the conclusions are presented in section IV.
II. TWO STAGE DIFFERENTIAL OP-AMP INTEGRATOR
Due to the continuous scaling of supply voltage and channel length, the Op-Amp design has started offering
the design challenges in terms of speed, power, gain, etc. and their tradeoffs. Gain Margin and Phase Margin
are the measures of stability in closed-loop, dynamic-control systems which indicates the absolute stability
and relative stability of the system [16][17]. The Phase Margin and Gain Margin of a minimum phase system
should be positive for an Op-Amp and Integrator to be stable. The schematic of two stage differential Op-
Amp having coupling capacitor and load capacitor of values 2.2pF and 10 pF respectively, is shown in Fig 1.
The Op-Amp Integrator performs the mathematical operation of integration with respect to time. It offers
output voltage proportional to the input voltage over time. The schematic of Integrator comprising of two
stage differential Op-Amp as the lower block, Fig 2. The values of resistor and capacitor used in the
Integrator design are 50kΩ and 10pF respectively.
III. SIMULATION AND RESULT
The design simulation of Op-Amp that comprises of input and output waveform with basic amplification
function is presented here, Fig 1. The transient analysis, DC and AC analysis of operation amplifier are
presented in Fig 3 and Fig 4. It also discusses the stability of Operational Amplifier. This section also
contains the simulations of Integrator with sine wave provided as input to it obtaining a cosine wave as
output verifying the mathematical operation of integration.
The transient analysis of two stage differential Op-Amp is shown in Fig 3 in which a signal of small
magnitude (mV) is amplified by the amplifier. The input voltage of Op-Amp ranges from 50mV to 100mV
which is amplified approximately to 1.85 V. When a sinusoidal wave is applied to the input terminals of the
amplifier, the amplified output waveform of a continuous sinusoidal wave is showing the AC simulations of
Op-Amp as shown in Fig 4.
In the presence of negative feedback to the amplifier, a zero or negative Phase Margin (PM), where the loop
gain exceeds unity guarantees instability. Thus, positive PM is a safety margin that ensures proper operation
of the amplifier circuit for minimum phase systems. The magnitude verses frequency curve of Op-Amp is
shown in Fig 5. The Gain Margin curve depicting the unity gain bandwidth of Op-Amp with a biasing
voltage of 0.7V is shown in Fig6 and the Phase Margin curve of Op-Amp is also shown in Fig7. The stability
3. 194
Fig1 Schematic Diagram of 2-Stage Differential Op-Amp
Fig2 Differential Two Stage Op-Amp Integrator
of the system could be concluded from Phase and Gain Margin curves by evaluating phase crossover
frequency and gain crossover frequency. The unity gain bandwidth of Operational Amplifier is measured as
15 MHz at 0.7 V biasing voltage and 21 MHz at 0.4 V biasing voltage respectively. A system is said to be
stable when the Gain and Phase Margin are positive. The Gain Margin and Phase Margin of Op-Amp are
13.096 dB and 59.582 ◦
with supply voltage as ±2.5V and 0.7V biasing voltage. Also, the Gain Margin and
Phase Margin of Op-Amp are 8.388 dB and 26.674 ◦
with supply voltage as ±2.5V and 0.4V biasing voltage.
This indicates that the Op-Amp circuit is stable. The power consumption of Op-Amp is 7.158mW and
4. 195
Fig3 Transient Analysis of Differential 2 Stage Op-Amp
Fig4 AC Analysis of Differential 2 Stage Op-Amp
6.998mW at a biasing voltage of 0.7V and 0.4V, respectively. Simulation results of Operational Amplifier
with biasing voltage of 0.7 V and 0.4 V at a supply voltage are given in Table 1 and Table 2 respectively.
Fig5 Magnitude V/S Frequency Curve
Fig6 Gain Margin
5. 196
Fig7 Phase Margin
TABLE I: SIMULATIONS OF OPERATIONAL AMPLIFIER WITH A VOLTAGE SUPPLY OF ±2.5V AND VBAIS AS 0.7V
S. No. Parameters Values
1 Biasing voltage 0.7V
2 UGB 15 MHz
3 Gain (3dB) 34.6 dB
4 Gain Margin 13.096 dB
5 Phase Margin 59.582 ◦
6 Power Dissipation 7.158 mW
TABLE II: SIMULATIONS OF OPERATIONAL AMPLIFIER WITH A VOLTAGE SUPPLY OF ±2.5V AND VBAIS AS 0.4V
S. No. Parameters Values
1 Biasing voltage 0.4 V
2 UGB 21.10 MHz
3 Gain (3dB) 60.0379 dB
4 Gain Margin 8.388 dB
5 Phase Margin 26.674 ◦
6 Power Dissipation 6.998mW
The sinusoidal signal applied across the terminals of an Integrator. Its output is a cosine function, i.e., an
integrated output of an applied signal, Fig8 and Fig9. The simulations of Integrator circuit at supply voltage
of 2.5V with biasing voltage at 0.4 V has a power dissipation of 7.844mW at operating frequency of 10kHz,
Table 3.
Fig8 Input Waveform of Integrator
IV. CONCLUSIONS
The full custom design simulation of a two stage CMOS Op-Amp and Integrator have been simulated and
analyzed. Tables and graphs of different operational parameters for Op-Amp and Integrator are presented.
The Phase and Gain Margin, both have positive values and the phase cross over frequency is seen to be more
than the gain cross over frequency of the two stage differential Op-Amp. This shows that the system is stable.
6. 197
Fig9 Output Waveform of Integrator
TABLE III: SIMULATIONS OF INTEGRATOR
S.No Parameters Values
1 Supply voltage ± 2.5 V
2 Bandwidth 15.03MHz
3 Vin+ 50mV to -50mV
4 Vin- 30mV to -30mV
5 Vbais 0.4V
6 Time Period 100μs
7 Frequency 10kHz
8 Power 7.844mW
The power of Op-Amp and Integrator is also evaluated. The unity gain bandwidth of Operational Amplifier is
15 MHz at 0.7 V biasing voltage and 21 MHz at 0.4 V biasing voltage with power consumption of 7.158mW
and 6.998mW, respectively. The power of Op-Amp is 7.158mW at 0.7V biasing voltage and 6.998mW at
0.4V and the power of Integrator circuit is 7.884mW.
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ABOUT THE AUTHORS
1
Anu, completed her B.Tech in Electronics and Communication Engineering from Ganga Institute of Technology and
Management, Kablana in 2012. She is now pursuing her Master of Technology (M.Tech) in VLSI Design at ITM
University, Gurgaon. Her interest includes Digital Design, ASIC Design, VLSI Testing and Verification.
2
Amit Kumar, received the B.E. (Hons.) degree in Electronics and Communication Engineering from C.I.T.M. Faridabad
in 2010 and the M.Tech. degree in VLSI Design from N.I.T. Kurukshetra in 2012. He joined ITM University, Gurgaon,
(Haryana) India as Asst. Professor in the Department of Electrical, Electronics & Communication Engineering during
July-December 2013. His areas of interest include VLSI domain and in particular Analog IC Design, Operational
Amplifers and Mixed signal systems.
3
Neeraj Kr. Shukla, (IETE, IE, IACSIT, IAENG, CSI, ISTE, VSI-India), an Associate Professor in the Department of
Electrical, Electronics & Communication Engineering, and Project Manager – VLSI Design at ITM University, Gurgaon,
(Haryana) India. He received his PhD from UK Technical University, Dehradun in Low-Power SRAM Design and
M.Tech. (Electronics Engineering) and B.Tech. (Electronics & Telecommunication Engineering) Degrees from the J.K.
Institute of Applied Physics & Technology, University of Allahabad, Allahabad (Uttar Pradesh) India in the year of 1998
and 2000, respectively. He has more than 50 Publications in the Journals and Conferences of National and International
repute. His main research interests are in Low-Power Digital VLSI Design and its Multimedia Applications, Digital
Hardware Design, Open Source EDA, Scripting and their role in VLSI Design, and RTL Design.