This document summarizes a tunable narrowband receiver operating from 1 GHz to 1.5 GHz. The receiver consists of a differential LNA, active mixer, and differential TIA. The LNA uses active post-distortion to improve IIP3 above +6 dBm across the frequency band. The active mixer employs a negative body-biasing topology to achieve over 7.9 dBm IIP3. Simulation results show the receiver achieves less than 3 dB NF and maintains IIP3 performance across 1-1.5 GHz to meet the design targets. Future work could include wideband input matching for the LNA and frequency-dependent bias optimization for the active mixer.
• Designed a Wilkinson Combiner at 30 GHz using microstrip transmission line and then at 60 GHz using coplanar waveguide.
• Simulated the Layout of the testbench using the EM Simulator at RF.
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
Designed a Switched Capacitor Low Pass Filter with a sampling frequency of 60 Hz.
Simulated the filter to have a ripple within 0.2 dB under 3.6 MHz and a stopband attenuation of atleast -51 dB after 7.2 MHz.
Applied dynamic range optimization, Dynamic Range Scaling and Chip Area scaling to get maximum output swing while occupying minimum area on chip.
Tested the filter with non-idealities of the amplifier, such as finite gain, bandwidth, offset voltage, charge injection, etc.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
• Designed a Wilkinson Combiner at 30 GHz using microstrip transmission line and then at 60 GHz using coplanar waveguide.
• Simulated the Layout of the testbench using the EM Simulator at RF.
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
Designed a Switched Capacitor Low Pass Filter with a sampling frequency of 60 Hz.
Simulated the filter to have a ripple within 0.2 dB under 3.6 MHz and a stopband attenuation of atleast -51 dB after 7.2 MHz.
Applied dynamic range optimization, Dynamic Range Scaling and Chip Area scaling to get maximum output swing while occupying minimum area on chip.
Tested the filter with non-idealities of the amplifier, such as finite gain, bandwidth, offset voltage, charge injection, etc.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSI...Ilango Jeyasubramanian
• Measured parasitic resistance and capacitance of two cascoded NMOS layout in LNA. Reduced down the parasitic resistance to about 1 ohm using a multi-fingered and multi-contacted layout.
• Analyzed the Q-based tuning of RFIC LNA by adding an ideal capacitor between the gate and source of CS stage of cascoded LNA and the corresponding variation of linearity using Cadence SpectreRF simulations.
Software PLL for PLI synchronization, design, modeling and simulation , sozopoldpdobrev
Power-line interference is a common disturbing
factor in almost all two-electrode biosignal acquisition
applications. Many filtering procedures for mains
interference elimination are available, but all of them are
maximally effective when the filter notches are positioned
exactly at the power-line harmonics, i. e. when the sampling rate is synchronous with the power-line frequency. Moreover, various lock-in techniques, su ch as automatic common mode input impedance balance, require precise in-phase and quadrature phase references, synchronous with the power-line interference. This paper describes in depth a design procedure of software PLL, generating synchronous reference to the common mode power-line interference, and achieved from its analog prototype using s to z backward difference transformation. The main advantage of th e presented
approach is that the synchronization is done in software, so it has no production cost. The presented PLL is intended for use in ECG signal processing, but it can be used after easy adaptation in various digital si gnal processing applications, where frequency synchronization is needed.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
Double feedback technique for reduction of Noise LNA with gain enhancementijceronline
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFBLNA included in a receiver frontend for biomedical applications (ISM and WMTS).
A New CMOS Fully Differential Low Noise Amplifier for Wideband ApplicationsTELKOMNIKA JOURNAL
In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for
wideband applications. A common-gate input stage is used to improve the input impedance matching and
linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A
shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise
amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In
frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure
(NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder
intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply
voltage of 0.8v.
Mixed Linearity Improvement Techniques for Ultra-wideband Low Noise Amplifier IJECEIAES
We present the linearization of an ultra-wideband low noise amplifier (UWB-LNA) operating from 2GHz to 11GHz through combining two linearization methods. The used linearization techniques are the combination of post-distortion cancellation and derivative-superposition linearization methods. The linearized UWB-LNA shows an improved linearity (IIP3) of +12dBm, a minimum noise figure (NF ) of 3.6dB, input and output insertion losses (S 11 and S 22 min. ) below -9dB over the entire working bandwidth, midband gain of 6dB at 5.8GHz, and overall circuit power consumption of 24mW supplied from a 1.5V voltage source. Both UWB-LNA and linearized UWB-LNA designs are verified and simulated with ADS2016.01 software using BSIM3v3 TSMC 180nm CMOS model files. In addition, the linearized UWB-LNA performance is compared with other recent state-of-the-art LNAs.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSI...Ilango Jeyasubramanian
• Measured parasitic resistance and capacitance of two cascoded NMOS layout in LNA. Reduced down the parasitic resistance to about 1 ohm using a multi-fingered and multi-contacted layout.
• Analyzed the Q-based tuning of RFIC LNA by adding an ideal capacitor between the gate and source of CS stage of cascoded LNA and the corresponding variation of linearity using Cadence SpectreRF simulations.
Software PLL for PLI synchronization, design, modeling and simulation , sozopoldpdobrev
Power-line interference is a common disturbing
factor in almost all two-electrode biosignal acquisition
applications. Many filtering procedures for mains
interference elimination are available, but all of them are
maximally effective when the filter notches are positioned
exactly at the power-line harmonics, i. e. when the sampling rate is synchronous with the power-line frequency. Moreover, various lock-in techniques, su ch as automatic common mode input impedance balance, require precise in-phase and quadrature phase references, synchronous with the power-line interference. This paper describes in depth a design procedure of software PLL, generating synchronous reference to the common mode power-line interference, and achieved from its analog prototype using s to z backward difference transformation. The main advantage of th e presented
approach is that the synchronization is done in software, so it has no production cost. The presented PLL is intended for use in ECG signal processing, but it can be used after easy adaptation in various digital si gnal processing applications, where frequency synchronization is needed.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
Double feedback technique for reduction of Noise LNA with gain enhancementijceronline
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFBLNA included in a receiver frontend for biomedical applications (ISM and WMTS).
A New CMOS Fully Differential Low Noise Amplifier for Wideband ApplicationsTELKOMNIKA JOURNAL
In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for
wideband applications. A common-gate input stage is used to improve the input impedance matching and
linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A
shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise
amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In
frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure
(NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder
intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply
voltage of 0.8v.
Mixed Linearity Improvement Techniques for Ultra-wideband Low Noise Amplifier IJECEIAES
We present the linearization of an ultra-wideband low noise amplifier (UWB-LNA) operating from 2GHz to 11GHz through combining two linearization methods. The used linearization techniques are the combination of post-distortion cancellation and derivative-superposition linearization methods. The linearized UWB-LNA shows an improved linearity (IIP3) of +12dBm, a minimum noise figure (NF ) of 3.6dB, input and output insertion losses (S 11 and S 22 min. ) below -9dB over the entire working bandwidth, midband gain of 6dB at 5.8GHz, and overall circuit power consumption of 24mW supplied from a 1.5V voltage source. Both UWB-LNA and linearized UWB-LNA designs are verified and simulated with ADS2016.01 software using BSIM3v3 TSMC 180nm CMOS model files. In addition, the linearized UWB-LNA performance is compared with other recent state-of-the-art LNAs.
This paper relates the new topology and simulations of a fully differential CMOS active filter for mm wave band applications. The advantages of the differential topology over the single ended one are discussed and the quality factor is tuned to insure application requirements, including narrow bandwidth and high selectivity due to a differential negative resistance that reuses the filter’s current. Using this topology enables independent tuning of the quality factor and low power consumption while compensating the resistive loss of the filter. Very high filter performance was obtained with the simulated active inductor based active filter that was designed using CMOS 0.35 µm technology from AMS foundry and that resonates at 30 GHz with a high quality factor of Q > 500.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
Design and Implementation of a Low Noise Amplifier for Ultra Wideband Applica...IOSRJVSP
This paper represents the design and implementation of Low Noise Amplifier for Ultra wideband application using 0.18μm CMOS Technology. The proposed two stage LNA is for a 3-5 GHz. At supply voltage of 1.8V, for the exceed limit of 50μm of width of each transistor, the power consumption is 7.22mW. Noise figure is 4.33dB, Maximum power gain i.e. S21 is 20.4dB, S12 < -20dB, S11 < -8dB, S22 < -10dB. For the required bandwidth range, LNA is unconditionally stable and have good linearity
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A Low Power down Conversion CMOS Gilbert Mixer for Wireless CommunicationsIJERA Editor
In this paper a design of low power 2.4GHz (RF) down conversion Gilbert Cell mixer, implemented in 0.18μm
CMOS technology with 1.8V supply voltage is presented. The obtained result shows a conversion gain equal to
6.7dB and third order Input intercept point -1db, power consumption of 3.86mW at 1.8V supply voltage. The
50Ω matched impedance condition is applicable. Result shows a good potential of this CMOS mixer and justify
its use for low-power wireless communications.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Similar to ECE265B_FinalReport_finished all_v1.0 (20)
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...
ECE265B_FinalReport_finished all_v1.0
1. Tunable Narrowband Receiver (1GHz-1.5GHz) with Active Mixer 1
Tunable Narrowband Receiver (1GHz -1.5GHz)
with Active Mixer
Jihang Lu, Haoran Pu, Fanyu Yang, and Nian Jiang
Abstract – Based on IBM 0.18m-CMOS
technology, an Implementation of a narrowband
receiver tunable from 1 GHz to 1.5 GHz is
reported in this paper. To achieve high
performance on NF (noise figure) and linearity,
the receiver consists of a differential source
degenerate LNA (low noise amplifier), a negative
body-biasing active mixer, and a differential TIA
(transimpedance amplifier) with CMFB (common
mode feedback). In LNA, APD (active post-
distortion) is introduced to improve IIP3.
Feedback is used in TIA to improve linearity.
Based on the simulation results, the overall
performance of the proposed receiver achieves <3
dB NF and > 8 dBm IIP3 across the frequency
band from 1GHz to 1.5GHz.
Index Terms – tunable narrow band receiver,
LNA, active mixer, TIA, APD, linearity
improvement, noise figure, resistive feedback,
CMFB.
I. Introduction
For a narrowband receiver, high linearity is critical,
as this property is essential to alleviate severe gain
compression, cross modulation and harmonic
generation [1]. This paper proposes a tunable
narrowband receiver with high performance on
linearity. The paper begins with the project target
performance and background information. Section III
to Section V describes the major components of the
receiver. The overall performance is presented at the
end of this paper.
II. Background and Project Target
High linearity receivers are significant for
communication system due to the requirement of
signal-to-interference-plus-noise ratio (SINR). Since,
in general, TIA tends to have good linearity, the LNA
and mixer of the receiver have significant impact on
overall linearity of the system. For LNA, several
linearity improvement methods has been proposed. [2]
introduces an idea of 3rd
order distortion cancellation
by using 2 different biases. In [3], the theory of active
post distortion (APD) is used to improve IIP3. For
mixer, several topologies in [4], [5], and [6] has been
used to improve the linearity of active mixer.
In previous work on tunable receiver, [7] has
proposed such a receiver with parameters shown
below:
Frequency
Range
(MHz)
Maximum
Gain (dB)
NF at
Max
gain
(dB)
IIP3 at
Max
gain
(dBm)
IIP3
(dBm)
Power
Consump
-tion
(mW)
470-862 >80 7.9 -8 +2 120
In this paper, we target to design a receiver with
following specs:
Gain
(dB)
NF
(dB)
LO Output
Power
(dBm)
IIP3
(dBm)
IIP2
(dBm)
Power
Consumption
(mW)
> 45 < 3 ~ 0 > +6 > +45 < 40
III. LNA
A. Topology
Since the receiver is a tunable narrowband receiver
and has high requirement on noise figure and
linearity, inductor source degenerated LNA is used.
Capacitors in series with switches control operation
frequency from 1 GHz to 1.5 GHz, 100 MHz per
stage. In addition, several techniques are introduced
to improve noise figure and linearity.
B. Band-Tuning
Tunable narrowband LNA has basic source
degenerated LNA structure (Figure 1), but its input
matching frequency and output tank peak frequency
are changeable from 1G Hz to 1.5G Hz. In the
tunable range, conversion gain S21 is larger than 15
dB, reflection coefficient S11 is less than -10 dB, NF
is less than 3 dB, out of band IIP2 is larger than +45
dBm and IIP3 is larger than +6 dBm. Five switches
control five capacitors in parallel with of the
common source NMOS to adjust input matching
frequency changing from 1 GHz to 1.5 GHz, 100
MHz per stage. Another five switches control the
resonance frequency of the load tank. The LNA is
designed sensitive to the added capacitors. In other
words, the added capacitors can change input
matching frequency and load tank frequency easily
2. Tunable Narrowband Receiver (1GHz-1.5GHz) with Active Mixer 2
with small capacitance values. Small capacitor is
important because large capacitor can introduce large
parasitic resistor and capacitor, and require large area.
C. NF Reduction
NF of the source degenerated LNA can be roughly
calculated as:
NF is reduced by reducing the size of the source
degenerated inductor and matching inductor .
The two inductors have the minimum line spacing in
order to have large inductance and small resistance at
the same time. In addition, is reduced as much as
possible to reduce noise figure and power
consumption, but the gain should be larger than +15
dB for all the stages.
D. Linearity Improvement
To improve linearity, the theory of active post
distortion is introduced to improve IIP3. The
structure used (Figure 2) is based on modified super-
position method. The circuit cancels third order non-
linearity by adding two current together to reduce
third order distortion term.
Fig. 1 (left). LNA Topology
Fig. 2 (right). Schematic Diagram of Active Post Distortion [3]
Under weakly nonlinear small signal condition,
higher order nonlinearities can be neglected.
Assuming only and contribute to
nonlinearities, gate voltage and drain current of
can be expressed respectively as:
Where and are the ratio of trans-conductance
as shown in Figure 2. Then we can find first and third
order terms for the output current:
The first equation shows, by adding Active Post-
Distortion, gain is reduced. In the second equation,
the first term is the third order nonlinearity
contribution from the original third order distortion
and the second term is the third order nonlinearity
contribution from the original second order distortion.
In our case, set and . Gain is
suppressed a little but total third order distortion due
to the original third order distortion is significantly
reduced. Since the second order distortion is
relatively small when compared to first order term,
the second term in the second equation can be
ignored [3].
Since a very good IIP2 (+45 dBm) is required, the
LNA need second order distortion reduction. We use
differential input differential output LNA to eliminate
second order distortion. As shown below, third order
distortion is suppressed as well by using differential
LNA. However, power consumption is doubled.
E. LNA Performance
Final result of LNA across frequency is shown as
below in Table 1.
TABLE 1.
SIMULATION RESULT OF LNA
Frequ-
ency
(GHz)
Gain
S21
(dB)
S11
(dB)
Noise
Figure
(dB)
Out of
Band
IIP3
(dBm)
Out of
Band
IIP2
(dBm)
Power
Consu-
mption
(mW)
1.0 +15.8 -12.6 2.67 +8.60 +44.1 28.88
1.1 +17.0 -14.5 2.49 +9.46 +45.3 28.88
1.2 +17.9 -16.9 2.38 +10.7 +47.4 28.88
1.3 +18.6 -19.5 2.33 +15.8 +47.5 28.88
1.4 +19.0 -22.1 2.32 +12.7 +55.9 28.88
1.5 +19.3 -28.1 2.34 +10.6 +50.1 28.88
F. Future Improvement
The circuit has best performance at 1.4GHz, while
its spec degrades as frequency moves away from
1.4GHz. The degradation is largely due to input
matching which affects all other specifications.
Instead of switching capacitors, wideband input
matching can solve the degradation problem.
3. Tunable Narrowband Receiver (1GHz-1.5GHz) with Active Mixer 3
Besides, variability over process and temperature
should be considered since the bias point of M2 and
M3 are insensitive.
IV. Active Mixer
A. Topology Selection
Active mixer is the bottleneck for linearity of the
whole system. With double balanced topology, IIP2
is cancelled with the differential output, and the main
issue is IIP3. We test several topologies with IIP3
target of 10 dBm. Eventually the topology we use is
negative body-biasing.
B. Source Degenerated Topology
In [5] a topology with modifications to the original
double balanced active mixer structure is presented.
It uses PMOS transistors as load to avoid load
resistance limit if an actual resistor were used. The
tradeoff is that flicker noise of the load transistors
shows up at baseband. We add inductors between
sources of switching pairs and source of RF input
pair to tune out large parasitic capacitance introduced
by large switches. Most importantly as presented in
the paper we use very large source degeneration
NMOS transistors
to maximize linearity. However,
instead of an IIP3 of +10 dBm as shown in the paper,
when simulating with PSS shooting we can only get -
3.5 dBm. Obviously this is too far away from our
target.
C. Negative Body Biasing Topology
The topology we eventually used is as presented in
[4]. It is a double balanced active mixer that utilizes
negative body-biasing to cancel third-order
transconductance. The NMOS input pairs for RF+
and RF- signals each provide adequate gm of 19mS
with moderate current consumption of 4.72mA. Each
input transistor is separated into two transistors to
allow negative body biasing at one of the transistor.
Negative bias voltage applied to body of one of the
transistor (TN81 as in Figure3) can increase its
threshold voltage and shift its curve right by the
same amount. Combining the new curve with the
original curve (from TN4 as in Figure 3), a flat region
can be created where is minimized.
Fig.3. Schematic of negative body biasing
The correct gate and body bias is found using
parametric sweep. is determined to be -1.16 V
and is determined to be 690 mV to give IIP3 of
7.9 dBm. As later simulation turns out, IIP3 reduces
as LO frequencies move down. This implies that
curves are frequency dependent, and the optimum
bias points shifts as frequency shifts. Luckily, the
degradation of IIP3 is compensated by gain
degradation of LNA as frequency reduces, and the
system IIP3 is largely maintained.
D. Flicker Noise Reduction
When the active mixer is tested with the receiver
chain, flicker noise shows up at input pairs of TIA.
This flicker noise comes from large current through
switching pairs at zero crossings of LO. To alleviate
this problem, a cross-coupled PMOS pair is added.
Cross-coupled pair themselves introduces flicker
noise, so is increased about 5 times until NF of
whole system reaches the specification.
E. Suggested Improvements
As mentioned above, the negative body biasing is
only optimized for a single LO frequency. To
maintain linearity over various frequencies, some
other topologies may be more suitable. However, as
shown in [6], tunable receiver generally has less than
0 dBm IIP3. New topologies are needed for active
mixers that are both highly linear and tunable.
Also IIP3 results vary a lot with simulation method
being used. PSS (including shooting and harmonic
balance) and HB give widely spread results. The
large difference makes it hard to decide the best
topology.
F. Final Results of Active Mixer
The final results of active mixer are shown below
in Table 2.
4. Tunable Narrowband Receiver (1GHz-1.5GHz) with Active Mixer 4
TABLE 2.
SIMULATION RESULT OF ACTIVE MIXER
Gain
(dB)
NF (dB) Power
(mW)
IIP3
(dBm)
IIP2
(dBm)
12.7 ±2 16.8 ±2 8 3.65 ±4 57 ±7
V. TIA
A. Topology Selection
For the last stage of receiver, which is the TIA,
two-stage differential OP-AMP with common mode
feedback (CMFB) is used. The simplified circuitry is
shown in Figure 4.
Fig.4. Circuitry of Differential OP-AMP with CMFB
The amplifier is designed with a differential first
stage and a common source second stage. CMFB is
designed using a low gain amplifier, which is added
to keep the common mode output low. The TIA is
biased at ½ VDD (0.85V).
Analysis and design procedure of the differential
OP-AMP will be briefly discussed in next two
sections.
B. Linearity Boosting
To improve linearity, input impedance needs to be
minimized without degenerating bandwidth and
phase margin. Thus, open loop gain of the OP-AMP
should not be too small. To improve the open loop
gain, for the first stage, boosting of the PMOS
common source amplifier is required, while of the
NMOS below also has to be kept large enough. For
the second stage, of the NMOS common source
amplifier should be large. The open loop gain of the
OP-AMP presented can be boosted up to 60dB in
simulation (Figure 5).
Fig.5. Open Loop Gain of the OP-AMP
Moreover, RC feedback is added between input and
output to construct a TIA, which has good linearity at
baseband.
C. Stability Optimization
In order to maintain stability at baseband, enough
phase margin (larger than 50 degrees) is critical.
Compensation RC network needs to be carefully
designed to achieve this goal. Therefore, capacitance
should be large so as to guarantee proper phase
margin. Moreover, the product of resistance and
capacitance may not be overly large to avoid
corrupting bandwidth. Phase margin of the TIA
proposed in this report is 59 degrees, which ensures
the stability of the receiver system.
After several rounds of optimization based on
system requirements, size of the transistors are
adjusted to ensure enough gain, bandwidth and phase
margin. The performance parameter of the final
design of TIA is listed in Table 2.
TABLE 3.
SIMULATION RESULT OF TIA
Power Gain Noise Figure
(Integrated, 1Hz-
5MHz)
Phase Margin
TIA 76dB 3.08 dB 59 degree
IIP3 IIP2
TIA 23 dBm 83 dBm
VI. Result Summary
Simulations are conducted in Cadence. Simulation
results for 1.5 GHz are shown in Figure 6.
5. Tunable Narrowband Receiver (1GHz-1.5GHz) with Active Mixer 5
Fig.6. Simulation results at 1.5 GHz
The overall system’s simulation result across
frequency is shown in this part.
The general performance is summarized in Table 4
.
Table 4.
General Performance of the Receiver across Frequency
Frequency
(GHz)
Power
(mW)
Gain
(dB)
Integrated NF(1Hz-
5MHz) (dB)
1
41.5
51.79 2.93
1.1 52.84 2.69
1.2 53.2 2.59
1.3 53.59 2.52
1.4 53.98 2.52
1.5 53.7 2.98
All specs except the power consumptions have met
the project target. Power consumption is 1.5mW
higher comparing with requirement.
As shown in Table 5, IIP3 of the receiver > 8dBm
across the frequency. IIP2 is ranged from 52dBm to
95dBm over frequency 1GHz and 1.5GHz, with the
best performance achieved at 1.2GHz.
Table 5.
Linearity Result of the Receiver across the Frequency
Frequency (GHz) IIP3 (dBm) IIP2 (dBm)
1 8.44 89.07
1.1 8.46 68.57
1.2 8.69 95.29
1.3 8.8 77.352
1.4 8.6 62.18
1.5 8.58 52.68
VII. Conclusion
A tunable narrow band receiver working in the
frequency 1GHz to 1.5GHz is presented in this
project report. The performance of receiver has met
the project requirements with power usage slightly
higher comparing with the target. The linearity of this
system is greatly improved with the implementation
of active post distortion theory and third-order
transconductance cancellation on LNA and active
mixer respectively.
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