This document summarizes a 175μW 100MHz-2GHz inductorless receiver front-end in 65nm CMOS. It achieves over 17dB of gain from 100MHz to 2000MHz while consuming only 175μW from a 0.9V supply. The noise figure is 11dB and third-order intercept point is -16.8dBm. It uses a completely inductorless topology with a real input impedance of 300Ω achieved through current feedback in two stages, with a common gate stage at the input and common drain stage providing feedback current. The active area is just 0.017mm2, excluding pads.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino LogicIDES Editor
Dynamic logic style is used in high performance
circuit design because of its fast speed and less transistors
requirement as compared to CMOS logic style. But it is not
widely accepted for all types of circuit implementations due
to its less noise tolerance and charge sharing problems. A
small noise at the input of the dynamic logic can change the
desired output. Domino logic uses one static CMOS inverter
at the output of dynamic node which is more noise immune
and consuming very less power as compared to other proposed
circuit. In this paper we have proposed a novel circuit for
domino logic which has less noise at the output node and has
very less power-delay product (PDP) as compared to previous
reported articles. Low PDP is achieved by using semi-dynamic
logic buffer and also reducing leakage current when PDN is
not conducting. This paper also analyses the PDP of the circuit
at very low voltage and different W/L ratio of the transistors.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Timer with audible warning with circuit Diagram Team Kuk
From detectors to automobiles, audible alarms (also known to be called buzzers) have become a part of our everyday life. Some of the uses of these alarms are innocuous such as in a microwave oven. However, in some applications such as in a smoke detector or medical equipment, a person’s life may depend upon the audible warning sound. In all cases, the equipment designer should consider the desired characteristics of the audible alarm at the initial design-planning phase to obtain satisfactory performance and avoid costly redesign. The first characteristic for a designer to consider is the type of sound such as a continuous, intermittent or specialty sound. Other critical criteria include sound level, frequency, current draw, quality, mounting configuration, cost, and availability
LEDs are of interest for fibre optics because of five inherent characteristics..
How it works?
Spectrum of an LED
Modulation of LED
LED Vs. Laser diode
disadvantages of LED
A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino LogicIDES Editor
Dynamic logic style is used in high performance
circuit design because of its fast speed and less transistors
requirement as compared to CMOS logic style. But it is not
widely accepted for all types of circuit implementations due
to its less noise tolerance and charge sharing problems. A
small noise at the input of the dynamic logic can change the
desired output. Domino logic uses one static CMOS inverter
at the output of dynamic node which is more noise immune
and consuming very less power as compared to other proposed
circuit. In this paper we have proposed a novel circuit for
domino logic which has less noise at the output node and has
very less power-delay product (PDP) as compared to previous
reported articles. Low PDP is achieved by using semi-dynamic
logic buffer and also reducing leakage current when PDN is
not conducting. This paper also analyses the PDP of the circuit
at very low voltage and different W/L ratio of the transistors.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Timer with audible warning with circuit Diagram Team Kuk
From detectors to automobiles, audible alarms (also known to be called buzzers) have become a part of our everyday life. Some of the uses of these alarms are innocuous such as in a microwave oven. However, in some applications such as in a smoke detector or medical equipment, a person’s life may depend upon the audible warning sound. In all cases, the equipment designer should consider the desired characteristics of the audible alarm at the initial design-planning phase to obtain satisfactory performance and avoid costly redesign. The first characteristic for a designer to consider is the type of sound such as a continuous, intermittent or specialty sound. Other critical criteria include sound level, frequency, current draw, quality, mounting configuration, cost, and availability
LEDs are of interest for fibre optics because of five inherent characteristics..
How it works?
Spectrum of an LED
Modulation of LED
LED Vs. Laser diode
disadvantages of LED
ITAC InfoCast - IT&IFRS - The Euro-Experience Part 1Malik Datardina
In the first installment of a two part series, we explore the IT issues related to IFRS. We are joined by two experts, Mahmoud Safavi of KPMG and Steen Skorstengaard of Deloitte (see below for their bios), who were in Europe in 2005 where they experienced the IT issues associated with the conversion to IFRS first hand.
In this episode, Mahmoud and Steen share their overall experiences with IT and IFRS in Europe. Also, they examine the IT implications of the IFRS rules around Plant, Property, and Equipment (PPE) and Leases. They also share some advice to those organizations that have already completed the gap-analysis between their current accounting rules and IFRS.
Please, visit us at:
http://www.cica.ca/research-and-guidance/it-advisory-committee/item23749.aspx
Design of a Low Power Low Voltage CMOS Opamp VLSICS Design
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.
Design of A Low Power Low Voltage CMOS OpampVLSICS Design
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um
technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2 ) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor ...journalBEEI
This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.
Design and Implementation of a Low Noise Amplifier for Ultra Wideband Applica...IOSRJVSP
This paper represents the design and implementation of Low Noise Amplifier for Ultra wideband application using 0.18μm CMOS Technology. The proposed two stage LNA is for a 3-5 GHz. At supply voltage of 1.8V, for the exceed limit of 50μm of width of each transistor, the power consumption is 7.22mW. Noise figure is 4.33dB, Maximum power gain i.e. S21 is 20.4dB, S12 < -20dB, S11 < -8dB, S22 < -10dB. For the required bandwidth range, LNA is unconditionally stable and have good linearity
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
A New CMOS Fully Differential Low Noise Amplifier for Wideband ApplicationsTELKOMNIKA JOURNAL
In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for
wideband applications. A common-gate input stage is used to improve the input impedance matching and
linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A
shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise
amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In
frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure
(NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder
intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply
voltage of 0.8v.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sinewave Generation 1. Problem Statement The goal of t.docxjennifer822
Sinewave Generation
1. Problem Statement
The goal of this project is to generate a sinusoidal waveform with the Arduino. Software is
provided that outputs a binary sinewave signal on pins D8-D11 which is converted to an
analogue voltage using a special type of digital to analogue converter (DAC), called an R-2R
ladder. The sinewave's frequency is roughly 200 Hz. Your task is to design and construct
both the R-2R ladder and a reconstruction filter which converts the “staircase” output of the
R-2R DAC into a “smooth” sinusoidal signal of amplitude 3 Vpk-pk and mean value zero.
2. Background
Many modern devices utilise digital circuits for analysing and processing data but still require
an interface to the analogue world, for example, to drive a speaker or control a motor's speed.
The conversion of digital data to analogue voltages is performed with a circuit known as a
digital to analogue converter, or DAC. In this project you will be implementing a simple
DAC circuit built solely of resistors, called the R-2R ladder.
To generate an analogue signal DACs will update their output at a specified frequency known
as the sample rate. The DAC's output voltage will only change value once per sample,
resulting in a “staircase” looking waveform. In order to produce a smooth waveform a circuit
known as a reconstruction filter is used. There are many different ways of implementing this
filter but in this project you will use a combination of active (op-amp based) low-pass and
high-pass filters.
2.1. R-2R ladder
The R-2R ladder DAC uses a network of resistors to convert a binary number to an analogue
voltage. The digital number is given from the Arduino by the digital output pins. In fact
these pins act as a controlled voltage source. If a bit in the 4-bit binary represented number is
1, the corresponding output pin is set HIGH and acts as a voltage source. If the bit is 0 on the
other hand, the corresponding output pin is set LOW and acts as a ground connection.
Although simple this circuit has several limitations. Specifically, it has a high output
impedance (ie: the Thevenin equivalent resistance is high) and the precision of the output
voltage is limited by the low number of bits and the precision of the resistors chosen. The
1% tolerance resistors available in the lab become the limiting factor beyond 6 bits so this
DAC architecture is rarely used for high precision DACs (10+ bits).
In this project you can use op-amp circuits to act as buffers to compensate for the high output
impedance of the R-2R ladder. The precision of the output will be limited by the chosen 4-bit
bit depth and will result in “noise” on the output (ie: random voltage amplitude errors) which
are impractical to remove. Nonetheless a smooth-looking waveform should still be possible
to generate.
The basic circuit is shown in Figure 1.
Exercise 1. Find expressions for the output (Vout) in terms o.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
1. A 175μW 100MHz-2GHz inductorless receiver front-
end in 65nm CMOS
Carl Bryant, Henrik Sjöland
Department of Electrical and Information Technology, Lund University, Box 118, 221 00 Lund
Abstract—This paper presents an inductorless ultra-low power of current consumption, has a limited usefulness due to the
frontend for applications such as sensor networks and medical resulting noise [2].
implants. By using a completely inductorless topology the chip Providing the input impedance using a feedback structure
area is just 0.017mm2, excluding pads. A real input impedance of such as a common gate or shunt feedback stage requires gain,
300Ω is achieved with current feedback. Manufactured in 65nm
and thus power to provide the match. If we assume that the
CMOS, it measures more than 17dB gain from 100MHz to
2000MHz while consuming only 175μW from a 0.9V supply (The resistance is provided by feedback of current from a
LNA consumes 115μW). The measured noise figure and IIP 3 is transconductance stage as illustrated by Fig. 1 the input
11dB and -16.8dBm respectively. impedance becomes
Rin 1 g m . (1)
Index Terms—CMOS, Low Noise Amplifier, LNA, Mixer, The resulting input impedance is inversely proportional to
Front-end, ultra low power, impedance matching, inductorless
the gain, which is proportional to the power consumption. By
designing for a higher than normal termination impedance we
I. INTRODUCTION should thus be able to reduce the power consumption. High
With the advances in communications technology we are impedances are, however, more sensitive to parasitic
regularly finding new applications that benefit from being capacitance from the pad, package and ESD-protection. As a
attached to wireless data networks. For a range of these compromise we have chosen an impedance of 300Ω.
applications, such as sensor networks, medical implants,
active RFID, etcetera. Devices should be cheap, compact and
have very long battery life. Suitable radio circuits should thus
have the same properties of being low cost, small, and Rin - gm
consuming a minimum amount of power. Circuits to be v i
manufactured in quantity should preferably be designed in
Figure 1. Impedance from current feedback
CMOS for cheapness and the possibility of integration
together with digital blocks. As CMOS is made smaller and An impedance of 300Ω requires a total gm of 3.33mS.
smaller it is today not just suitable for RF applications in Although this is a significant improvement over an equivalent
general; the performance offered by the latest process nodes 50Ω circuit requiring 20mS, even this is tricky to achieve at
means that it is now also suitable for ultra-low power radio. the current consumption we are aiming for. Apart from biasing
Really pushing the power consumption is a challenge in the devices in moderate to weak inversion we can also trade
itself, requiring any current consumed to be used efficiently. speed for gain by using complementary devices. Without
With MOS devices it is possible to achieve more gain for the inductors we can’t practically use very low supply voltages
same power consumption by biasing them in the medium or anyway without losing too much linearity. Even with
low inversion regions [1]. Unfortunately the speed quickly complementary stages, however, a single stage struggles to
falls off at low bias currents, but with modern CMOS achieve the sought matching impedance.
processes we have fast devices to begin with, and so we can In [2] cross coupling techniques are used to increase the
hope to trade some of this speed for improved gain. gain from each stage. A differential input LNA however
To minimize external components the receiver should be requires some form of balun, which means an additional
able to provide acceptable matching on chip. Though an external component as well as a limitation on the available
inductorless design is the most compact, providing a real bandwidth. Since we want to avoid unnecessary external
impedance without excessive noise or power consumption is a components the input should therefore be single ended.
challenge. To achieve negative feedback with two stages (more are
II. CIRCUIT DESIGN impractical when pushing the current consumption this low)
one stage should be inverting and the other non-inverting. A
To provide a real input impedance with an inductorless common way of constructing an inductorless LNA is with a
MOS based LNA design, we require either a resistive common source stage to provide voltage gain, and a common
termination, i.e. a resistor shunted to ground, or some form of drain stage to provide the feedback current such as in [3].
feedback structure to provide the correct current to voltage This paper suggests instead using a common gate stage as
ratio. Resistive termination, although practically free in terms the non-inverting stage, see Fig. 2. The input is the point of the
978-1-4244-8971-8/10$26.00 c 2010 IEEE
2. circuit with the lowest impedance. Because of this a common Although the circuit is intended for use with a 300Ω
gate stage at the input can provide voltage gain as well as the source, it is quite possible to use it with a 50Ω source with an
common source output stage, but non-inverting. Furthermore external matching network. The wide bandwidth and small
the signal current through the input stage will also contribute size makes this circuit quite flexible. The impedance
to the input matching. The output stage has been split to transformation will then provide an additional voltage gain of
provide high isolation and voltage gain. All devices are biased roughly 8dB.
close to their threshold voltage. A single balanced mixer, Fig. 4, completes the front-end.
The devices are small to reduce the load of the LNA and LO
drivers.
Figure 2. LNA schematic (biasing details not shown)
Figure 4. Mixer (biasing not shown)
As the parasitic extraction tool wasn’t working during
layout, the pad capacitance was assumed to be about 50fF, The relatively high LNA gain suppresses the mixer noise well.
based on [4, 5], both of which are based on 65nm processes, The simulated LNA noise figure is 8dB, and the total frontend
one from ST Microelectronics, the same as this circuit. Since noise figure 9.5dB.
very recently it has been possible to make parasitic
III. RESULTS
extractions, and as it turns out the pad capacitance is around
100fF, leading to worse than expected input impedance. Since The circuits were mounted in QFN40 packages, and
no RF pads were available in the design kit, an analog pad was soldered to PCBs. To measure S11 a TRL (Through-Reflect-
modified by reducing the size of the pad and ESD diodes as Match) kit was constructed using the same type of circuit
well as some rerouting of metal conductors. The reduced ESD board as the chip was attached to. This kit allows calibration
devices still dominate the input capacitance with just over to the end of the PCB input conductor.
100fF in total. With all that parasitic capacitance, the LNA As can be seen in Fig. 5 (normalized to 300Ω) the
input devices have to be quite small so as not to hurt the measured input impedance differs notably from simulations.
matching any more. This unfortunately limits the design The squares mark 470MHz and the rings 2GHz, to help
freedom, with a high noise figure as a result. compare the two traces. The grey ring around the centre marks
The circuit operates to some extent as an active inductor the boundary where S11 is better than -10dB.
which helps cancel some of the input capacitance. The gates of
the second stage load the first stage, see Fig. 3. The impedance
contribution of the feedback loop ignoring the first stage input
impedance becomes
g ds1 jC gs2
Z in,loop . (2)
g m1 g m 2
As we can see the negative reactance at the intermediate
node translates to a positive reactance (i.e. inductance) at the
input. Measured
Simulated
Figure 5. Input impedance. Z0 = 300Ω
It looks much like there is some additional capacitance
somewhere. Some of it is explained by the package, but there
still appears to be notably more than expected.
Figure 3. Input matching of circuit
3. There are several possible explanations to this error. The close to simulations, it appears that the circuit itself is
first is that the renormalization to 300Ω amplifies any functioning.
measurement error (The TRL kit has a reference impedance of Fig. 8 shows the noise figure versus source impedance at
100Ω). It is also possible that the extensive modification of the 1GHz. A Maury MT982EU32 automatic impedance tuner
pad frame has caused some unexpected problem. The design system was used to perform this source pull measurement. The
kit pads have their active layers added prior to manufacture measurement is made on a packaged chip and is not
and it is conceivable that the modified pad was mistaken for compensated.
the original pad, and had its ESD assembly modified.
Another explanation is that there is a large uncertainty of
the components or their models, however a later circuit that is
not dissimilar to this one has come back from manufacturing,
and initial measurements show little or no extra capacitance.
The main difference is that the RF pad used for this circuit
was modified from a non-RF pad in the design kit, while the
newer circuit has a fully custom made pad frame. The pad and
diode dimensions should be approximately the same.
To find out how well the circuit itself is functioning we’ll
attempt to remove the effect of the package and the additional
capacitance from the measurements. The package impedance
is estimated using [6] (50fF self capacitance and 2nH bond
wire inductance). After that we have to remove another 75fF
before the measured S11 is similar to simulations. The Figure 8. Source pull noise measurement, Z0 = 50Ω
compensated impedance can be seen in Fig. 6.
The lowest noise figure is achieved close to the conjugate
match (gain not shown) and is 11.1dB. This corresponds well
with measurements taken with a 50Ω matching network.
Two tone linearity measurements were performed at 1GHz
with an LC matching network at the input to provide a 50Ω
match. The result can be seen in Fig. 9. The 1dB compression
Measured point is measured to -27.5dBm and the third order intercept
(compensated)
point to -16.8dBm.
Simulated
Figure 6. Input impedance after compensation, Z0 = 300Ω
Figure 9. Linearity measurements
Table 1 compares the circuit performance to that of other
publications with ultra-low power consumption. The second
column shows how the performance is affected when
including an external 50Ω matching net.
The areas have been estimated from chip photographs to
not include pads or unused space. A photograph of the
Figure 7. Input matching manufactured circuit is included as Fig. 11. The area shown is
approximately 0.5x0.5mm. The active area of the front-end is
Fig. 7 shows S11 before and after compensation, with
comparison to simulation. Though there is still some about 0.017mm2.
uncertainty as to what should and shouldn’t be there, the
compensated input impedance is similar to simulations.
Combined with the fact that the DC operating points are very
4. Design This Work W/ 50Ω matching [7] [8] [9] [11] [10]1 [2]1
Technology 65nm CMOS 0.13μm 0.13μm 0.18μm 0.18μm 0.18μm 0.13μm
CMOS CMOS CMOS CMOS CMOS CMOS
Inductorless Yes - No No No No No Yes
Single ended Yes Yes Yes Yes No Yes No
f (MHz) 100-2000 - 2400 2450 2400 400 820-1070 100-930
Gain (dB) >17 >25 15.7 20 30.5 25 15.6 13
NF (dB) 11 (101) 18.3 7.5 10.2 3 4.9 4
Pcons (μW) 175 (1151) 500 600 500 500 100 720
CP1dB (dBm) -27.5 -28 -19 -31 -21.8 -18
IIP3 (dBm) -16.8 -9 -10 -13.7 -10
Area (mm2) 0.017 0.09 0.5 2.1 0.22 0.27
Z0 (Ω) 300 50 50 50 50 8000 50 50
Table 1. Summary of measurement results, and comparisons to other published receivers and LNAs
1
LNA only
Fig. 10 shows the voltage gain of the receiver. A circuit
with a matching network to operate with 50Ω input impedance ACKNOWLEDGMENT
would have 8dB additional voltage gain. The measurements Thanks to Fredrik Ahlberg for sorting out the software for
are close to expected. the source pull measurement.
This circuit has been manufactured within the project for
Wireless Communication for Ultra Portable Devices, funded by
SSF – Swedish Foundation for Strategic Research.
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A single ended input front-end with an ultra-low power [10] A Shameli, P Heyclari, "A Novel Power Optimization Technique for
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