High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.

1. 1
Design of Two CMOS Differential Amplifiers
Abstract- Two high-performance differential
amplifiers were designed in 0.6 μm CMOS
technology and tested in Cadence. Waveforms
generated from the ADE simulator are provided
in this report to prove that each of the
specifications was achieved.
I. INTRODUCTION
ifferential amplifiers are an essential
element of modern electronics, finding use
in a broad range of applications. Audio
amplifiers are required to drive loudspeakers and
headphones, and are used to create low-pass, high-
pass, and band-pass filters. Amplifers serve medical
purposes such as providing the measuring apparatus
for the Electrocardiogram (EKG). In this particular
application, a differential amplifier is used to amplify
the tiny electrical potential difference produced by
the electrical charges on the skin. The ability to
reject the common mode signal and amplify only the
differential mode signal is essential if an accurate
reading is to be obtained. A measure of this
quantity, the common-mode rejection ratio (CMRR),
is one of the many specifications defining a high-
performance amplifier. Other critical design
specifications include phase margin, differential gain,
output swing, CMRR, input-common mode range,
power consumption, and slew rate.
II. PROBLEM 1
Design a fully-differential operational amplifier
(differential output) for the following specifications:
Parameter Required Value
Supply Voltage (VDD) 4 V
Differential Gain > 60 dB for the
temperature range of 0-80
Input Common-Mode
(DC) Voltage
4 V
Phase Margin > 60 degrees
The circuit must have a common- mode feedback
(CMFB).
A. Circuit Topology
B. Circuit Design
The chosen topology was a folded cascode with
NMOS inputs, differential output, and a two-
transistor common-mode feedback circuit. This
topology was required to meet a key design
specification: the input common common-mode (DC)
voltage = 4 V. NMOS input transistors in the folded
cascode topology enable the ICMR to equal or
exceed the supply voltage, which is required in the
design specifications. Furthermore, the folded
cascode topology provides a higher gain than other
simpler topologies such as the five transistor op-amp.
Since there was no total static power consumption
requirement, there was freedom in selecting the
biasing current. However, upon noting that the
differential gain was relatively high (> 60 dB), a
small current of ID = 1 mA was used to bias the input
transistors since gain is proportional to 1/I.
Overdrive voltages were assigned to each of the
transistors. NMOS transistors were given an
overdrive voltage of 0.2 V, PMOS transistors 0.4 V,
and current source transistors 0.3 V. From the
biasing currents and overdrive voltages, the W/L
ratios were obtained for each transistor. The
calculation results are summarized in the following
table:
D
Michael Gordon, Student Member, IEEE
Figure 1: Amplifier #1 Topology
Figure 2: Problem 1 Requirements Specification

2. 2
Transistor(s) Overdrive
Voltage
Biasing
Current
W/L
Mb1,Mb11 0.3 V 1 mA 159
Mb2 0.4 V 0.5 mA 156.25
Mb3 0.2 V 0.5 mA 179
M 3-6 0.4 V 0.5 mA 156.25
M 7-10 0.2 V 0.5 mA 179
M 1,2 0.2 V 0.5 mA 179
The values of Vb1 and Vb2 were assigned to
maximize output swing:
Vb1 = VOD9 + VGS7 = 0.2 + 1.2 = 1.4 V
Vb2 = VDD-VOD5-VGS3 = 4 –0.4 –1.2 = 2.4 V
The initial theoretical value for the gain (without
adjustments) was calculated using the folded cascode
gain formula:
Ad = gm1,2[(r04gm4(ro6//r02) // r08gm8r010]
= (5 mA/V)[(10*2.5*(10//20) // 20*5 *20]
= (5 mA/V)[167 k // 2000k]
= 770.65 V/V = 57.74 dB
To increase the gain to > 60 dB, the lengths of the
transistors were increased from 0.6u, while the W/L
ratios were preserved. The length values were
optimized in Cadence to provide adequate gain.
The predicted output swing was calculated as
follows:
Vo, max = VDD-VOD5-VOD4 = 4 – 0.4 – 0.4 = 3.2 V
Vo, min = VOD8 + VOD10 = 0.2 + 0.2 = 0.4 V
The output DC voltage was selected as
VODC = 1.8 V to maximize the peak-to-peak
symmetric output swing.
This value of VODC was set using a two-transistor
common-mode feedback (CMFB) circuit.
Since no ideal voltage sources other than the supply
voltage were permitted, voltage divider networks
were created to provide the required voltages on the
gates of the nmos and pmos cascoded transistors. A
current mirror was used to bias the input transistors.
A 10pF capacitor was inserted between the
differential outputs to improve the phase margin.
Transistor(s) W/L Width(u) Length(u)
NMOS M0, M1 159 95.4 0.6
Telescopic NMOS 179 644.4 3.6
NMOS Inputs 179 107.4 0.6
PMOS M10, M14 156.25 562.5 3.6
PMOS M9, M15 156.25 93.75 0.6
CMFB M12, M13 179 107.4 0.6
D. Simulation Results
CMFB
Voltage Divider
Current Mirror Biasing
Figure 3: Calculated W/L Ratios
Figure 4: Amplifier #1 Schematic
Figure 5: Optimized W/L in Cadence
Figure 5: Differential Gain over Temperature Sweep. This simulation was
performed using an AC analysis with temperature sweep. As the
temperature increased from 0-80 degrees Celsius, the gain increased from
approximately 60-70 dB.
C. Cadence Schematic

3. 3
Differential Gain and Phase Margin
ICMR
Summary of Results
Parameter Design Result
Supply Voltage (VDD) 4 V
Differential Gain 60.1669 dB – 70 dB (0-80
degrees Celsius)
Input Common-Mode
(DC) Voltage
4 V *
Phase Margin 72.7 degrees
CMFB sets the DC output voltage to 2 V.
Satisfied
Failed
* ICMR: 1 V - 4.2 V
III. PROBLEM 2
Design an operational amplifier for the following
specifications:
Parameter Required Value
Supply Voltage 4 V
Total Static
Power
Consumption
< 2 mW
Differential gain > 100 dB
Output Swing
(peak to peak)
3.6 V
Loading
(CL || RL)
1 pF || 50 k
Slew Rate (SR) 100 V/μs
Phase margin > 60 degrees
ICMR * 0 – 3.3 V
CMRR * > 100 dB
-3dB bandwidth * 1 kHz
* Optional for Improved Performance
A. Circuit Topology
Figure 6: Differential Gain and Phase Margin
Simulation Plot. The phase margin is -107.291 +
180 = 72.7 degrees at a unity gain frequency of
18.4822 MHz.
Figure 7: ICMR Simulation Plot. The input
common mode (DC) voltage of 4.0 V is
within the ICMR of this amplfier.
Figure 8: Summary of Results for Problem 1 Figure 9: Problem 2 Requirements Specification
Figure 10: Amplifier #2 Topology: A Two-Stage
Amplifier Design was selected. The 1st stage is a Gain
Boosted Telescopic Amplifier. The second stage is a
Common Source Amplifier, with a single-ended output.

4. 4
B. Circuit Design
A two stage amplifier design was selected in order to
provide high gain with a load resistor of 50 kΩ on the
output. The 1st stage consists of a single-ended
telescopic amplifier with current mirror, and gain
boosting on transistors M3 and M4. The second stage
is a simple common source amplifier. The circuit
required compensation, and therefore a coupling
capacitor was inserted between the output and M2 and
M4.
Since the required output swing was less than the
supply voltage, a single-ended output amplifier was
preferred since it allowed the DC output voltage to be
set without the need for common-mode feedback.
The output swing was dependent on the second stage
transistors, M9 and the current source transistor.
Obtaining the slew rate of 100 V/us required that the
minimum saturation current of the second stage equal
at least 100 μA. The 1st stage Iss current source
provides 100 μA, and therefore, M1 and M2 are each
biased at 50 μA. A biasing current of 100 μA ensures
that the total static power dissipation is less than 2
mW.
In order to provide a very high differential gain of
100 dB, gain boosting was used on transistors M3 and
M4. In addition, the lengths of all telescopic
transistors were increased, and their values optimized
in Cadence.
The remainder of this section summarizes the design
calculations and predictions before simulating the
circuit in Cadence:
Iss biasing current = 100 μA
The overdrive voltages were assigned as follows:
VOD, NMOS = 0.2 V
VOD, PMOS = 0.4 V
VOD, CS = 0.2 V
Slew Rate:
SR Iss/ CL
100 μA / 1 pF
μs
Differential Gain (Without Gain Boosting):
Ad = (1st stage gain) * (2nd stage gain)
= [gm1,2*(ro4gm4ro2) // (gm6r06ro8)] *
[(r09//rcs//RL]
Power Consumption
P = VDD * Itot = 4 V * 0.28 mA + 4 V * 0.1 mA
+ 4 V * 0.1 mA
= 1.92 mW < 2 mW
Output Swing:
Vo,max = VDD – VOD9 = 4-0.2 = 3.8 V
Vo, min = VOD,CS = 0.2 V
Compensation Capacitor:
The optimal value for the compensation capacitor
was determined through Cadence simulations of the
phase margin and -3dB bandwidth. Its value was
selected as 860 fF to maximize these two parameters.
C. Cadence Schematic
2nd Stage
Loading
Voltage Divider to
Set Gate Voltages
Gain-Boosting Stage
Figure 11: Problem 2 Circuit Schematic

5. 5
Transistor(s) W/L Width(μ) Length(μ)
Current Source 15.25 9.15 0.6
NMOS Inputs 179 322.05 1.8
Telescopic PMOS
P12, P13
15.75 340.2 21.6
Telescopic PMOS
P14, P15
15.75 9.45 0.6
Telescopic
NMOS N16,N17
179 322.05 1.8
Gain-Boosting
NMOS
180 108 0.6
P11 125 75 0.6
N15 35.75 21.45 0.6
D. Simulation Results
Differential Gain and Phase
Output Swing
Slew Rate
CMRR
-3dB Bandwidth
Figure 16: CMRR Simulation. The red curve is the differential
gain, the yellow curve is the common mode gain, and the green
curve is the CMRR. At low frequencies, the CMRR is greater than
100 dB.
Figure 15: Slew Rate Simulation. To measure the slew rate, one
of the differential inputs was connected to the single-ended
output. A large step function was applied to the other input. In
Cadence, the step function was created using a v-pulse function
with a 15 fs rise time and a pulse width of 1 ms. A 1 μs
transisent analysis was run on the output. The value of its
derivative immediately after 15 fs was recorded as the slew rate.
For this amplifier, SR = 407 V/μs.
Figure 14: Output Swing Simulation. The output swing was found
by running a DC analysis where the input DC value was swept from
0 to 5 V. The output swing for this amplifier was 3.77 Vp-p (413.4
μV – 3.775 V).
Figure 17: -3dB Bandwidth Simulation. The -3dB bandwidth is
slightly greater than 1 kHz. The -3dB point is located at
(1.00781 kHz, 97.0 dB).
Figure 13: Differential Gain & Phase Simulation
Results. Differential gain, Ad, = 104.68 dB. Phase
margin, φM, = -107.463 + 180 = 72.5 degrees.
Figure 12: Summary of Transistor Widths and Lengths

6. 6
Summary of Results
Parameter Design Result
Supply Voltage 4 V
Total Static
Power
Consumption
1.92 mW
Differential gain 100.892 dB
Output Swing
(peak to peak)
3.77 V
Loading
(CL || RL)
1 pF || 50 k
Slew Rate (SR) 407 V/μs
Phase margin 72.5 degrees
ICMR << 0-3.3 V
CMRR 101.817 dB
-3dB bandwidth 1.00781 kHz
Satisfied
Failed
IV. CONCLUSION
The specifications for the amplifier of problem one
were achieved. For problem two, all specifications
were achieved except for the ICMR requirement of
0 – 3.3 V. In the design of these high-performance
amplifiers, there were many tradeoffs between
specifications─ sometimes, one specification was
sacrificed in order to achieve another. Optimizing
each amplifier required that various circuit
parameters be assigned optimal values. For example,
in problem 2, a compensation capacitor was needed
to increase the phase margin to greater than 60
degrees. However, adding capacitance to the circuit
reduced the -3dB bandwidth. Cadence simulations
showed that by choosing an 860 fF capacitor, both
specifications could still be achieved. During the
design process of Amplifier #2, the ICMR
specification was neglected since it was deemed less
essential than the other required specifications. To
achieve this design specification, folded NMOS and
PMOS inputs could be added to the circuit. Since
these inputs would increase the total static power
consumption, the biasing currents would need to be
reduced. Although the ICMR was not achieved, the
designed amplifier greatly exceeds other design
specifications. The simulation results predict high
phase margin (φM = 72.5 degrees) and fast slew rate
(SR = 407 V/μs).
REFERENCES
[1] Behzad Razavi, "Design of Analog CMOS Integrated Circuits."
McGraw-Hill International Edition, 2001.
[2] Zihong Liu, Chao Bian, Zhihua Wang, and Chun Zhang, "Full
custom design of a two-stage fully differential CMOS
amplifier with high unity-gain bandwidth and large dynamic
range at output." ResearchGate, August 2005.
[3] Michael H. Perrott, "Analysis and Design of Analog
Integrated Circuits, Lecture 20: Advanced Opamp Topologies
(Part II)." 15 April 2012.
[4] Shopan din Ahmad Hafiz , Md. Shafiullah , Shamsul Azam
Chowdhury, "Design of a Simple CMOS Bandgap Reference."
International Journal of Electrical & Computer Sciences
IJECS-IJENS Vol:10 No:05, 2010.
[5] Alessandro Trifileti, "0.9-V CMOS cascode amplifier with
body-driven gain boosting." International Journal of Circuit
Theory and Applications, 19 August 2008.
Figure 18: Summary of Results for Problem 2. All
specifications were achieved except for the ICMR.