The document describes the design of a folded cascode operational amplifier. Key points: - The goal is to design an op-amp with over 80dB gain, 10MHz bandwidth, 5V/us slew rate, and other specs using a folded cascode topology. - Hand calculations are shown for determining device sizes to meet the gain, bandwidth, and slew rate specs. - Simulation results show a gain of 17.5k, 604.7Hz bandwidth, and 3.5V/us slew rate, meeting most but not all specs. - Analysis discusses the pros and cons of this topology, noting the difficulty of achieving high slew rate and the narrow input/

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SABANCI UNIVERSITY
EL 303
LAB 6:
FOLDED CASCODE OPERATIONAL
AMPLIFIER DESIGN
2012-2013 FALL
Meric Isgenc

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1)Introduction
For experiment six, we are expected to design an operational amplifier
using folded cascode topology.
When compared with the previous laboratory assignment; designing a
single stage amplifier will be eaisier in the sense of setting stability of the system
due to smaller amount of poles.
On the other hand swing voltages and slewrate may become a problematic
issue when considered with 80dB gain which is the same with the previous
assignment.
Problems occured with the design, comparison of multistage and single
stage amplifier designs will be done in further sections of the report.
2)Experiment Description
A)Goal Of Experiment:
Goal of the experiment is to design an op-amp, using folded cascode topology,
therefore one stage amplifier. Even the topology consists of two stages, first stage
,which is a "differential input-output", provides transconductance as the second
stage takes role as active load.
Expected specs are same as the previous experiment:
 Avo >80dB
 GBW >10MHz
 SR >5V/us
 PM >60deg
 Ptot <500uW (includes biasing currents)
 PSRRdd >40dB (for f<200kHz)
 PSRRss>40dB (for f<200kHz)

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B)Setup Of Experiment
Setup of the experiment with sizes
Setup of the experiment with currents and voltages;
total power consumption is approximately 308.7 uWatts

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Topology used in the experiment basically consists of three main elements.
First stage, as a fully differential amplifier focuses on "differentiation" of input
signals and filters the noise. Second stage, since it is connected to the output of
each end of the first stage, is used as an active load stage. Since transistors of the
second stage are used in saturation region and cascoded to each other, they form
great resistivity which is an important component of the gain.
Another advantage of the topology comes from single stage of gain
concept. The only transconductance which is effective on the gain is the
differential transistors'(M1 and M2 as seen on the schematic). Therefore there
occurs two poles which are the mirror and load poles of the differential amplifier.
Since load pole's time constant is way too greater than the mirror, 3dB point will
be determined by the load pole. Absence of a third pole, annihilates any probable
problems due to instability of the system. As a result, with this topology, we will
not be doing any calculations to stabilize the system. However due to great output
resistance, midband of the amplifier is narrow which makes it hard to set 10 MHz
Gain-Bandwidth frequency.
Current sources used in this topology are cascode or single transistor
sources. To provide IB, I used a pair of cascode transistors on each side of the
differential amplifier. The reason is receiving approximately constant current of
15uA which is desired to be realized in my design. On the other hand, "I-current"
provider, 5th transistor which is an NMOS, is kept as a single transistor. The
reason is settling:
 gm1
 Gain (by changing I/2-IB)
 Slewrate
by changing the current flowing on this transistor. Cons of this flexibility will be
explained in detail at hand calculation part with comparison of different
combinations of the variables listed above.
Third stage, or part, of the amplifier, consists of bias circuitry. Due to need
of three different bias voltages in my design, I used simple PMOS and NMOS

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voltage dividers with respectively long channel length to drive small amount of
current for less power consumption.
All bias voltages are set considering the "post-production" cases. I
considered any change that my occur within threshold voltages. I tried to provide
at least 0.3 Volts of overdrive voltage to each transistor. Detailed calculations will
be explained in hand calculations section.
C)Measured Values And Graphs
Schematic Simulation Results:
Gain of the amplifier is 17.5k and the 3dB point is at 604.7 Hz

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Slewrate is approximately 3.5 V/usec
at discharge, 1.3 V/usec at charge
Phase margin graphic of the final version of the amplifier. Phase margin is approximately 87
degree by 0dB of amplification.

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AC Gain simulation result of the VDD source. Amplifier is connected as buffer and VDD is given
AC magnitude of unity. Also, AC components on input sources are zeroed.
AC Gain simulation result when GND is serially connected to a AC Source with 1 Volt magnitude.
𝑃𝑆𝑅𝑅+
100𝐻𝑧 =
17.5𝑘
78.83𝑚
= 106.92𝑑𝐵
𝑃𝑆𝑅𝑅−
100𝐻𝑧 =
10𝑘
100𝑚
= 100𝑑𝐵

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ICMR is approximately [0.43 , 1.05] Volts
c)Handcalculations:
In this part of the report I will explain the hand calculations I followed,
device sizes and bias voltages/currents I determined. Also I will indicate the
resultant graphics of gain of the handcalculated device and show the iterations I
followed and explain the possible reasons that forced me to such changes in the
circuit.
A very fundamental point in my following hand calculations is that all device
lengths are taken 0,5 um at the beggining. Taking devices approximately one and a
half times longer than the minimum technology is less risky for production
matters and decreases the possible malfunctioning phenomenas. Therefore, my
design, aims to produce a circuit that is possible to function not only within
simulations but also in post production circumstances.

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Steps followed:
1)Each gate is applied approximately 300mV voltage at least due to a
possible treshold change for post-production
To provide -300mV Vov to M3,4;
VS4,3= 3.3 V
VGS4,3=2.3 V to provide approximately 0.3V of overdrive voltage.
Size of MP4 and MP3 will be calculated in the light of the calculation
above.
After 0.3 V of overdrive drop, drain of transistor 3 and 4 gets 3 Volts
approximately. Therefore I tried to provide 2 Volts of gate voltage for
transistors MP0 and MP1 as seen on the schematic.
As a result of 2 portions of overdrive voltage drop from VDD to source
of M5 and M6, VS5,6 = 2.7 V. Thus, VBIAS2 = 1.7 V for 0.3 V of
overdrive voltage for M5 and M6.
2) CL=10pF,
Since there is no concern about phase margin no calculations similar
to multistage amplifier design will be followed.
However Slewrate is an important factor to be set;
Since:
𝑆𝑙𝑒𝑤𝑟𝑎𝑡𝑒 =
𝐼11
𝐶𝑐
> 5𝑉/𝑢𝑠
I took I5 50 uAmperes, at its minimum limit for the smallest power
consumption. Of course, the current is to be updated to a higher
value in the case that it does not provide 5V/us slewrate. To avoid an
abundance of bias voltages, I used the same bias voltage for I11 and
I5,6.
𝐼1,2 = 25𝑢𝐴
𝐼 𝐷 =
1
2
𝜇 𝑛 𝐶𝑜𝑥
𝑊
𝐿 ( 𝑉 𝑂𝑉)
2

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𝑊
𝐿 𝑓𝑜𝑟 𝑀11 ≅ 0.5
𝐺𝐵𝑊 =
𝑔𝑚𝐼
𝐶𝑙
≥ 10𝑀𝐻𝑧
𝑔𝑚𝐼 ≥ 0.6 𝑚𝑍𝑖𝑒𝑚𝑒𝑛𝑠
We can decide the gain of the amplifier using the identities above.
3)Overall gain is to be 10k.
𝐴 𝑣0 = −𝑔𝑚𝐼[ 𝑟𝑜1 𝐼𝐼 𝑟𝑜4 ∗ 𝑔𝑚 𝑀𝑃0 ∗ 𝑟𝑜 𝑀𝑃0 ∗ 𝑔𝑚5 ∗ 𝑟𝑜5 𝐼𝐼 (𝑟𝑜10 ∗ 𝑔𝑚8 ∗ 𝑟𝑜8)]
I decided to take I5,6 as 15 uA. Therefore IB must be fixed at 40uA for a stable system.
𝐼 𝐷 =
1
2
𝜇 𝑝 𝐶𝑜𝑥
𝑊
𝐿 ( 𝑉 𝑂𝑉3,4,𝑀𝑃0,𝑀𝑃1 = 0.3𝑉)
2
( 𝑊
𝐿)3,4,𝑀𝑃0,𝑀𝑃1 = 16.16
However, after measurements I increased the size ratios since transistors could not
manage to flow a current of 40uA.
In the case the currents are fixed like that (channel lengths are taken as 0.5 um,
therefore VA = 3.125 Volts):
𝐴 𝑣0 = −𝑔𝑚𝐼[(~26𝑀Ω ∗ 𝑔𝑚5) 𝐼𝐼 (43.4𝑀Ω ∗ 𝑔𝑚8)]
I decided to take gmI = 1.5mZiemens, which means (W/L)1,2 = 150
As a result the rest is expected to have an approximate resistance value of ~7Mohms
𝑔𝑚 = 2 ∗ 𝐼𝑑 ∗ µ𝐶𝑜𝑥
𝑊
𝐿
Equation can be used to determine the sizes of the transistors
To have approximately 14Mohms for both sides of the parallel combination of
resistances, I took
 gm5 ~ 0.6mZiemens, therefore first component of resistance above is
approximately 16Mohms and (W/L)5,6 = 230

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 gm8 ~ 0.32 mZiemens, therefore we approximately get 15Mohms and
(W/L)7,8,9,10= 16
4)Bias circuitry; transistor based voltage dividers:
In this part, I aimed to form a divider made of transistors to avoid
area and power consumption. To lessen the currents driven, I
extended the channel as much as possible.
I used diode connected transistors to not to use any extra bias
voltage and to guarantee saturation. Necessary width and length for
the devices used in bias circuitry are determined using equation:
𝐼 𝐷 =
1
2
𝜇 𝑛 𝐶𝑜𝑥
𝑊
𝐿 ( 𝑉 𝑂𝑉)
2
Of course, I iteratively changed the sizes if small unexpected
deviations occured at the bias voltages.
Disadvantage of the divider ->: Since it is made of only simple diode
connected transistors used as resistors, the temperature dependency
of the system is high. However in ideal, decreasing the dependecy of
the divider from temperature and any outter noise is necessary for a
more stable and robust circuit.
Handcalculated circuit before any iterations:

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Overall gain of the system is much below the expected. In this case there are two
possible options to increase the gain:
1)Increasing gmI
2)Increasing output resistance via longer channel lengths at the fold stage
Since I obtained approximately 8MHz of GBW frequency and a very
small amount of slewrate, I decided to increase the current flowing on
M1 and M2 to have a greater transconductivity. I also doubled the
channel lengths of all six fold transistors to increase the output
resistance. As a result I obtained a more robust circuit with
approximately 17.5 k gain and 10MHz of GBW. However as a critique
to my circuit, I could not manage to provide the requested slewrate
with the design given above.
Therefore, I decided to provide the requested slewrate spec, which
seemed to be a challenging one. Since I could only get 2.5-3 V/us with
80 uA, I decided to increase the I11 current to 1.5 times greater. If this
current increment performed without any other size changes, major
components of the amplifier goes in to triode or off since nearly no
current can flow to the fold. Hence, I also enlarged the size ratio of the

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PMOS IB providing current sources nearly up to 65 uA. Therefore I was
to have 5uA at fold part which forms a great resistance at output that
increases the gain. Also, as I aimed for this iteration, I also managed
5V/us of slewrate for both charge and discharge.

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d)Analysis and Discussion
As seen from the handcalculations and measurement results above,
Folded Cascode Topology is a useful topology due to abscence of multiple
interacting poles. Also, providing gain is not such a hard issue since there is
a great resistive load at output. However, as a result of that great resistance
at output swing for both input and output is a problematic issue. Luckily,
connecting another folded cascode, which is symmetric of this circuit to the
bottom of this one and taking differential output is useful since it provides
rail to rail swing.
Another problematic issue here is slewrate since there is great deviation
between the theoratical and measured values. However, as a trade-off,
power consumption is what we need to sacrifice to provide greater gain,
therefore greater slewrate.
4)Conclusion
All in all, this experiment was a good example for designing a folded
operational amplifier and seeing the cons and pros. When compared with
the previous laboratory assignment's amplifier, multistage op-amp, this one
seems to be a bit harder to provide Slewrate and GBW issues. Another pro
which worths mentioning is narrower ICMR and Vout swing range which
decreases the functionality of the system.