• Designed a Wilkinson Combiner at 30 GHz using microstrip transmission line and then at 60 GHz using coplanar waveguide.
• Simulated the Layout of the testbench using the EM Simulator at RF.
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
Designed a Switched Capacitor Low Pass Filter with a sampling frequency of 60 Hz.
Simulated the filter to have a ripple within 0.2 dB under 3.6 MHz and a stopband attenuation of atleast -51 dB after 7.2 MHz.
Applied dynamic range optimization, Dynamic Range Scaling and Chip Area scaling to get maximum output swing while occupying minimum area on chip.
Tested the filter with non-idealities of the amplifier, such as finite gain, bandwidth, offset voltage, charge injection, etc.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
Designed a two stage Differential Input to Single Ended Output Op-amp in Cadence. The following Simulated specifications were achieved:-
Open loop gain = 67.97 dB
Phase Margin = 75.3°
Unity Gain Frequency = 15.29 MHz
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
Designed a Switched Capacitor Low Pass Filter with a sampling frequency of 60 Hz.
Simulated the filter to have a ripple within 0.2 dB under 3.6 MHz and a stopband attenuation of atleast -51 dB after 7.2 MHz.
Applied dynamic range optimization, Dynamic Range Scaling and Chip Area scaling to get maximum output swing while occupying minimum area on chip.
Tested the filter with non-idealities of the amplifier, such as finite gain, bandwidth, offset voltage, charge injection, etc.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
Designed a two stage Differential Input to Single Ended Output Op-amp in Cadence. The following Simulated specifications were achieved:-
Open loop gain = 67.97 dB
Phase Margin = 75.3°
Unity Gain Frequency = 15.29 MHz
• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
Double feedback technique for reduction of Noise LNA with gain enhancementijceronline
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFBLNA included in a receiver frontend for biomedical applications (ISM and WMTS).
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
Double feedback technique for reduction of Noise LNA with gain enhancementijceronline
In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW-1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFBLNA included in a receiver frontend for biomedical applications (ISM and WMTS).
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Two CMOS Differential Amplifiersbastrikov
High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
Non-radiative wireless energy transfer with single layer dual-band printed sp...journalBEEI
Accomplishing equilibrium in terms of transfer efficiency for dual-band wireless energy transfer (WET) system remains as one of key concerns particularly in the implementation of a single transmitter device which supports simultaneous energy and data transfer functionality. Three stages of design method are discussed in addressing the aforementioned concern. A single layer dual-band printed spiral resonator for non-radiative wireless energy transfer operating at 6.78 MHz and 13.56 MHz is presented. By employing multi-coil approach, measured power transfer efficiency for a symmetrical link separated at axial distance of 30 mm are 72.34% and 74.02% at the respective frequency bands. When operating distance is varied between 30 mm to 38 mm, consistency of simulated peak transfer efficiency above 50% is achievable.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
HFSS ANTENNA FOR KU BAND WITH DEFECTED GROUND STRUCTURESAKSHAT GANGWAR
A wide band Microstrip antenna is proposed for Ku band applications with defected groundd structure. A circular shape defect is integrated in the ground plane. A novel equivalent circuit model is proposed for Microstrip patch antenna with defected ground structure. Accurate design equations are presented for the wideband Microstrip antenna and theoretical analysis is done for the proposed structure. The proposed antenna has an impedance bandwidth of 56.67% ranging from 9.8 GHz to 17.55 GHz, which covers Ku-band and partially X-band. The antenna shows good radiation characteristics within the entire band, and has a gain ranging from 5 dBi to 12.08 dBi. Minimum isolation between co-polar and cross-polarization level of 20 dB and 15 dB is achieved in H-plane and E-plane respectively. The simulation of the proposed antenna is done on HFSS v.13, and measured results of fabricated antenna are in good agreement with the theoretical and simulated results
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
Digital Voltmeter displaying voltage level on a seven segment display and com...Karthik Rathinavel
• Coded an Altera FPGA board in System Verilog such that it could use the on board ADC to convert the voltage signal into a digital signal, that was displayed on a seven segment display as well as on a computer screen.
• Utilized a UART (USB to serial) to receive the voltage signal that was to be displayed on a computer.
• Controlled the selection of channel for analog input by transmitting the serial data through the UART from the computer keyboard.
Sine Wave Generator with controllable frequency displayed on a seven segment ...Karthik Rathinavel
• Designed a Sine Wave Generator Hardware, whose frequency could be controlled using a quadrature encoder.
• Coded the FPGA board in System Verilog to display a count (going from 0 to 9999) on to a seven segment board. This count that was displayed, was same as the frequency of the sine wave generated.
• Incorporated a brightness control feature for all the digits being displayed. This was done by changing the duty cycle using a push button for the PWM control.
• Included an additional feature of increasing the count and the frequency by tens, hundreds or thousands, instead of increasing by just one.
Continuous Low Pass Filter Realization using Cascaded stages of Tow-Thomas Bi...Karthik Rathinavel
Designed a Continuous Low Pass Filter using three stages of cascaded Tow-Thomas Bi-quads which met the following specifications:-
Pass band: DC to fp = 20 kHz, gain between 0 dB & 1 dB.
Stop band: f > fs = 40 kHz, gain below -50 dB
Found the transfer function, poles and zeros of the required filter using MATLAB. Used Cadence to plot the frequency response of the gain of the overall transfer function using ideal op-amps and non-ideal op-amps.Used dynamic optimization and dynamic range scaling of the elements (resistors and capacitors) such that the output of each stage had a good output swing.
Optical communication between two computers was achieved by using a LED connected to a microcontroller in the transmitting end. A photodiode in the receiving end was used to collect the light pulses transmitted by the LED. A microcontroller at the receiving end was used to encode the data received by the photodiode.
A computer at the transmitting end compiled a recursive program that generated digital pulses. This data was given a DC offset voltage and sent to one of the output pins of the microcontroller. At the receiving side, another computer was used to graphically plot the data received from the receiving side microcontroller.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
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Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
1. ECE 593 Project 1 By: Chien Chun Yao and Karthikvel Rathinavel
Introduction:
This report describes a method to design and layout a Wilkinson combiner by first using a microstip transmission line and
then using a coplanar waveguide. A two way Wilkinson power divider works by dividing the power coming from one port
and splitting it equally into two parts if it splits into a quarter wavelength in both sides and a shunted resistor between the
ports. It can be shown that if the input characteristic impedance is 50 ohms, then for a shunted resistor of 100 ohms the
output transmission lines should have 70.7106 ohms of characteristic impedance.
Final Simulated Results:
Simulated Results Microstrip TL Coplanar Waveguide
Bandwidth (-10dB) Very High 76.8 GHz
Loss -2.415 dB -5.445 dB
Minimum Metal Width (W) 6.187 um 8.038 um
Minimum Metal Spacing (G) - 10 um
Design Approach: The simulated results for our initial design from the EM layout extracted symbol was tested by
constructing a testbench which comprised of a 100 ohm resistor between the open ports and also by adding terminations.
Next we fine-tuned the values of W and L (in the case of microstrip) in order to look at the impact it has to our bandwidth
and loss. Decreasing W and L results in decreasing the overall area of the layout while keeping maintaining the same
impedance of the different parts of the line. Similarly decreasing the metal spacing (G) in the case of coplanar waveguide,
will reduce the area.
Bandwidth Calculation:
To determine the bandwidth of the Wilkinson combiner, the plots of S-parameters, , , , are observed at the
intersection points with -10dB. In fact we can appropriately select certain attenuation (in dB) such that we observe
bandwidth. Since the S parameters for input and output reflection coefficients ( , , never cross -10 dB for
Microstrip Transmission Line, its bandwidth cannot be ascertained. However, if we select -18 dB compression for all
three reflection coefficients, we can estimate bandwidth.
Power Loss Calculation:
The total power loss is calculated by adding the magnitude of insertion loss, isolation loss and the return loss in the
combiner. This is calculated at the center frequency for each case. Using the following equation.
Loss
3. A. A single-ended 30GHz Wilkinson Combiner using a mircrostrip transmission line.
Schematic:
Layout:
4. Simulations for loss and bandwidth from extracted EM simulation for Microstrip Transmission Line:
Discussion
To increase the bandwidth, the number of input ports could be increased; stepped multiple sections (Pozar). Increasing
numbers of input ports leads to high power loss, which implies larger bandwidth. Area could be further decreased by
decreasing the length of each MLIN. This could be done by decreasing the angle while for the same line impedance by
performing lincalc.
5. B. A single-ended 60GHz Wilkinson Combiner using a coplanar waveguide transmission line.
Schematic
Layout
6. Simulations for loss and bandwidth
Discussion
In order to further decrease the area, the metal spacing can be reduced. As a result our bandwidth will increase. In
addition we can increase the bandwidth with a series of coupling holes (Pozar) ie. By increasing the number of input
coupling ports. By reducing the phase of the input CPWGs we can reduce the length of the transmission line for the same
impedance which reduces the area.
References:
(1) Pozar