• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
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• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
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• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
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Designed a two stage Differential Input to Single Ended Output Op-amp in Cadence. The following Simulated specifications were achieved:-
Open loop gain = 67.97 dB
Phase Margin = 75.3°
Unity Gain Frequency = 15.29 MHz
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
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The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
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• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
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• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
An experiment to determine the value of current gain (Beta) of a transistor using voltmeter. The experiment also includes building a constant current source using bjt and zener diode.
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
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Designed a two stage Differential Input to Single Ended Output Op-amp in Cadence. The following Simulated specifications were achieved:-
Open loop gain = 67.97 dB
Phase Margin = 75.3°
Unity Gain Frequency = 15.29 MHz
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
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The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
Design of 17-Bit Audio Band Delta-Sigma Analog to Digital ConverterKarthik Rathinavel
Â
• Systematically designed a delta sigma ADC with CIFF modular architecture in MATLAB Simulink with an ENOB of 19-bits.
• Designed a decimation filter to remove noise in the digital output of the delta sigma modulator.
• Observed the effect of non-idealities on the modulator such as finite gain, finite bandwidth, slew rate, analog noise and capacitor mismatch.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
Â
• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
An experiment to determine the value of current gain (Beta) of a transistor using voltmeter. The experiment also includes building a constant current source using bjt and zener diode.
Capacitors have a self-resonance frequency (SRF), newer SMPS have switching frequencies above the SRF. We show strategies, how to choose the right components and what impacts SRF on capacitors.
Techniques and Challenges in Designing Wideband Power Amplifiers Using GaN an...NXP Admin
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At EDI CON USA 2016, Jeff Ho from NXP presented a workshop on the benefits and challenges in designing wideband power amplifiers using GaN and LDMOS technologies. Click through to explore the great potential of wideband power amplifier designs due to excellent power and efficiency characteristics at RF and microwave frequencies.
Techniques and Challenges in Designing Wideband Power Amplifiers Using GaN an...Lisa Bradley
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At EDI CON USA 2016, Jeff Ho from NXP presented a workshop on the benefits and challenges in designing wideband power amplifiers using GaN and LDMOS technologies. Click through to explore the great potential of wideband power amplifier designs due to excellent power and efficiency characteristics at RF and microwave frequencies.
A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V supply in ...aiclab
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Pushed by the ever-increasing demand of high-speed connectivity, next generation 400Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits FFE, and allows tuning the output impedance to ensure good source termination. Implemented in 28nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >>2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s, while drawing 120mA only from 1V supply. The power efficiency is ~2 times better than previously reported PAM-4 transmitters.
7. EXPERIMENTAL SET UP
• Problems with noise.
• Switched boards
• Rebuilt circuit
• Changed probes
8. RESULTS 1MA ICQ
• Best results around 100kHz
• Vmax=7.5V
• 37.5dB at 80kHz-100kHz
• -3dB 5.25V
• This happened at 320kHz
9. RESULTS 10UA ICQ
• Best results around 20kHz
• Vmax=0.788V
• 17.9dB at 20kHz
• -3dB 0.56V
• This happened at 50kHz
10. ANALYSIS OF RESULTS 1MA ICQ VS EXPERIMENT
• Simulation max = 40.4dB at 188kHz with -3dB at 7.5MHz
• Actual results 37.5dB at 80kHz-100kHz with -3dB at 320kHz
• -7.18% difference for max vout
• -95.7% difference for upper frequency
11. ANALYSIS OF RESULTS 10UA ICQ VS EXPERIMENT
• Simulation max = 25.8dB at 253kHz with -3dB at 1.12MHz
• Actual results 17.9dB at 20kHz with -3dB at 50kHz
• -30.6% difference for max vout
• -92.1% difference for upper frequency
12. ANALYSIS OF RESULTS 1MA VS 10UA LTSPICE
40.4
25.8
37.5
17.9
0
5
10
15
20
25
30
35
40
45
1mA 10uA
Comparison of dB Results for Vout/Vin
Simulated Experimental
188
253
100
20
0
50
100
150
200
250
300
1mA 10uA
Comparison of Max Vout/Vin kHz
Simulation Experimental
7.5
1.12
0.32
0.05
0
1
2
3
4
5
6
7
8
1mA 10uA
Upper Half-Power Frequency
MHz
Simulation Experimental
14. SERVICEABILITY
• There was no most critical resistor
• Changed all values +/-5% as shown
• 40.4dB dropped to 39dB
• -3.47% difference in operation
15. COST
• $50 Labor is the only item to pay for and once designed, it can be built in less
than an hour by one person.