Understanding Xilinx OFFSET constraints

1. Xilinx OFFSET IN and OFFSET OUT
Constraints
Reference: Xilinx WP237

2.  OFFSET constraints are used to define the timing relationship between an
external clock pad and its data in or data out.
 The relationship is also known as constraining the pad-to-setup or clock-to-out
paths on the device. These constraints are very important for specifying timing
interfaces with external components.
 Pad to Setup or OFFSET IN BEFORE constraint is used to ensure that the
external clock and external input data meet the setup time on the internal flip-
flop which latches the external data input.
 Clock-to-Out or OFFSET OUT AFTER constraint is used to control the setup/hold
requirement of the downstream devices.
What are OFFSET Constraints?

3. What Paths are Covered by OFFSET Constraints?
The OFFSET constraints cover the following paths:
From input pads to synchronous elements (OFFSET IN)
From synchronous elements to output pads (OFFSET OUT)
If the clock that clocks a synchronous element does not come through an input
pad – for example, it is derived from another clock – then the OFFSET constraint
will fail to return any paths during timing analysis.

5.  The OFFSET IN BEFORE constraint defines the time available for data to
propagate from the pad and setup at the synchronous element.
 You can visualize this as the time that the data arrives at the edge of the device
before the next clock edge arrives at the device.
 “OFFSET = IN 2 ns BEFORE clock_pad” constraint implies that the external data
is available at input data pad just 2ns before the next active clock edge arrives.
In this case tool has only 2 ns to route the data from pad to the synchronous
element.
OFFSET IN BEFORE

6.  The following equation defines the setup relationship:
TData + TSetup - TClock <= Toffset_IN_BEFORE
OFFSET IN BEFORE
 In the equation clock delay (Tclock) is
subtracted from the data delay (TData)
because data and clock are in series.
 As depicted in timing waveform below,
with the same data delay we have two
different Toffset_IN_BEFORE value
because of different clock delays.
 TIMEGRP DATA_IN OFFSET IN = 3ns
BEFORE CLK TIMEGRP FF_RISING;
 TIMEGRP DATA_IN OFFSET IN = 5ns
BEFORE CLK_DELAYED TIMEGRP
FF_RAISING;

7. The following is example of the OFFSET IN with the VALID keyword:
 TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK TIMEGRP FF_RISING;
 In the above constraint setup requirement is 1 ns and the hold time
requirement is 2 ns (VALID – OFFSET IN VALUE).
 The OFFSET IN requirement value is used as a setup time requirement of the
FPGA during the setup time analysis. The VALID keyword is used in conjunction
with the requirement to create a hold-time requirement during a hold-time
analysis.
OFFSET IN BEFORE Constraint With Valid Keyword

8. SIMPLE EXAMPLE
Slack = (Requirement - (Data Path - Clock Path - Clock Arrival))

10. OFFSET IN EXAMPLE WITH PLL INVOLVED
FPGA
FF
OSCILL
ATOR
PHY
OSCILL
ATOR
50 MHz
25 MHz
DATA

11.  For the design shown in the previous slide, suppose the pad clock is clk25, the
internal sample clock is clk50 and the output clock to PHY is clk50.
 The OFFSET IN requirement with regards to clk50 is
TIMEGRP “DATA" OFFSET IN = 2 ns BEFORE clk50 RISING
 As clk50 clocks the incoming data on every rising edge, both rising and falling
edges of clk25 will be used as reference to specify the OFFSET IN at the input
pad clock. Please refer timing diagram in the previous slide to understand it
better.
 Since OFFSET constraints works only with external clocks, we have to define
OFFSET constraints with respect to CLK_25MHz.
 The OFFSET IN requirement with regards to CLK_25MHz is
TIMEGRP “DATA" OFFSET IN =12 ns BEFORE "<<input 25MHz pad clock>"
RISING";
TIMEGRP “DATA" OFFSET IN =12 ns BEFORE "<<input 25MHz pad clock>"
FALLING";
OFFSET IN BEFORE Constrain For The Above Example