Virtual clocks can be defined for all input and output clocks in a design. This separates the clock domains for the I/O and core, allowing for separate and distinct clock uncertainty constraints. Virtual clocks provide unique clock transfers for I/O versus internal transfers, ensuring the correct uncertainty values are set.

1. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks
 Virtual clocks could be defined for all input clocks and
output clocks in current design
 Virtual input clock for external launch clock in the constraint for the input
case
 Virtual output clock for external latch clock in the constraint for the output
case.
 This will separate the clock domains for the IO and core.
 This is required to set the correct clock uncertainty
numbers in the clock uncertainty constraints, which differ
for the core and the IO transfers
 Main benefit is it allows for separate and distinct clock
uncertainty constraints to be made for each unique clock
transfer.

2. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clock Examples
D Q
clk_in
data_in
D Q
data_out
PLL
clk_in
D Q
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
D Q
virt_clk_in
D Q
virt_clk_out
Case A
Case B

3. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case A: No PLL Involved
 Traditionally, you'd set input delay and output delay with
clk_in as the reference clock
 This intra-clock transfer would appear the same as the IO clock transfer
 Incorrect clock uncertainty would be applied for IO transfers
 Virtual clocks for input transfer and output transfer
provide separate and distinct clock transfers from clk_in
core intra-clock transfer.
D Q
clk_in
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case A

4. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case A: No PLL Involved
 Old Constraints:
create_clock -period 10 -name clk_in [get_ports {clk_in}]
set_input_delay -clock [get_clocks {clk_in}] -max 2 [get_ports {data_in}]
set_input_delay -clock [get_clocks {clk_in}] -min 0 [get_ports {data_in}]
set_output_delay -clock [get_clocks {clk_in}] -max 2 [get_ports {data_out}]
set_output_delay -clock [get_clocks {clk_in}] -min 0 [get_ports {data_out}]
 Clock Transfers
From clk_in to clk_in only
 Resultant Clock Uncertainty
From clk_in to clk_in Setup: 150ps Hold: 50ps
D Q
clk_in
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case A

5. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case A: No PLL Involved
 New Constraints:
create_clock -period 10 -name clk_in [get_ports {clk_in}]
create_clock -period 10 -name virt_clk_in
create_clock -period 10 -name virt_clk_out
set_input_delay -clock [get_clocks {virt_clk_in}] -max 2 [get_ports {data_in}]
set_input_delay -clock [get_clocks {virt_clk_in}] -min 0 [get_ports {data_in}]
set_output_delay -clock [get_clocks {virt_clk_out}] -max 2 [get_ports {data_out}]
set_output_delay -clock [get_clocks {virt_clk_out}] -min 0 [get_ports {data_out}]
 Clock Transfers
From clk_in to clk_in
From virt_clk_in to clk_in
From clk_in to virt_clk_out
 Resultant Clock Uncertainty
From clk_in to clk_in Setup: 150ps Hold: 50ps
From virt_clk_in to clk_in Setup: 130ps Hold: 130ps
From clk_in to virt_clk_out Setup: 130ps Hold: 130ps
D Q
clk_in
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case A

6. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case B: PLL Involved
 Traditionally, you'd set input delay and output delay with clk_in as the
reference clock
 Separate transfers would happen in this case
 Transfers: clk_in to PLL, PLL to PLL, PLL to clk_in
 Virtual clocks for input transfer and output transfer provide separate
and distinct clock transfers from clk_in to core, intra-clock transfer of
core PLL clock, and core PLL clock to output.
 The use of virtual clocks will separate a presumed inter-clock core
transfer from clk_in to PLL from an IO transfer to/from the PLL.
PLL
clk_in
D Q
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case B

7. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case B: PLL Involved
 Old Constraints:
create_clock -period 10 -name clk_in [get_ports {clk_in}]
set_input_delay -clock [get_clocks {clk_in}] -max 2 [get_ports {data_in}]
set_input_delay -clock [get_clocks {clk_in}] -min 0 [get_ports {data_in}]
set_output_delay -clock [get_clocks {clk_in}] -max 2 [get_ports {data_out}]
set_output_delay -clock [get_clocks {clk_in}] -min 0 [get_ports {data_out}]
derive_pll_clocks
 Clock Transfers
From clk_in to pll_clk0
From pll_clk0 to pll_clk0
From pll_clk0 to clk_in
 Resultant Clock Uncertainty (based on example design PLL settings)
From clk_in to pll_clk0 Setup: 270ps Hold: 230ps
From pll_clk0 to pll_clk0 Setup: 100ps Hold: 50ps
From pll_clk0 to clk_in Setup: 230ps Hold: 270ps
PLL
clk_in
D Q
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case B

8. © 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
Virtual Clocks - Case B: PLL Involved
 Old Constraints:
create_clock -period 10 -name clk_in [get_ports {clk_in}]
create_clock -period 10 -name virt_clk_in
create_clock -period 10 -name virt_clk_out
set_input_delay -clock [get_clocks {virt_in_refclk }] -max 1 [get_ports {data_in_a* data_in_b* }]
set_input_delay -clock [get_clocks {virt_in_refclk }] -min 0 [get_ports {data_in_a* data_in_b* }]
set_output_delay -clock [get_clocks {virt_out_refclk }] -max 1 [get_ports {data_out* }]
set_output_delay -clock [get_clocks {virt_out_refclk }] -min 0 [get_ports {data_out* }]
derive_pll_clocks
 Clock Transfers
From virt_clk_in to pll_clk0
From pll_clk0 to pll_clk0
From pll_clk0 to virt_clk_out
 Resultant Clock Uncertainty (based on example design PLL settings)
From virt_clk_in to pll_clk0 Setup: 150ps Hold: 100ps
From pll_clk0 to pll_clk0 Setup: 100ps Hold: 50ps
From pll_clk0 to virt_clk_out Setup: 100ps Hold: 150ps
PLL
clk_in
D Q
data_in
D Q
data_out
D Q
virt_clk_in
D Q
virt_clk_out
Case B