FPGA Timing analysis basic

1. TIMING ANALYSIS

2. Circuit delay

3. Propagation and Contamination Delay
• The propagation delay tpd : is the maximum time from when an input
changes until the output or outputs reach their final value.
• The contamination delay tcd : is the minimum time from when an
input changes until any output starts to change its value.

4. Propagation and Contamination Delay

5. Propagation and Contamination Delay

6. Propagation and Contamination Delay

7. Propagation and Contamination Delay
• The propagation delay of a combinational circuit is the sum of
the propagation delays through each element on the critical path.
• The contamination delay is the sum of the contamination delays through
each element on the short path.
tpd = 2tpd_AND + tpd_OR
tcd = tcd_AND

8. Glitches

9. Glitches

10. Glitches

11. Glitches

12. Glitches

13. TIMING OF SEQUENTIAL LOGIC

14. System Timing

15. Setup Time Constraint
Tc ≥ tpcq + tpd + tsetup

16. Hold Time Constraint
tccq + tcd ≥ thold

17. EXAMPLE

18. Solution

19. Solution

20. Clock Skew
Tc≥ tpcq + tpd + tsetup + tskew
tpd ≤ Tc−(tpcq + tsetup + tskew)

21. Clock Skew
tccq + tcd ≥ thold + tskew
tcd ≥ thold + tskew−tccq

22. Metastability

23. TimeQuest Timing analyzer
SDC is the acronym for Synopsys Design Constraints. This is the
industry standard language for timing constraints that has been
adopted by most FPGA vendors and EDA tools that support FPGA
devices.

24. Timing Analysis Terminology

25. Timing Analysis Terminology

26. Timing Analysis Terminology

27. Timing Analysis Terminology

28. Timing Analysis Terminology

29. Timing Analysis Terminology

30. Timing Analysis Terminology