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Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

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During placement and routing, most of the placement tools, place/move logic cells based on floorplan specifications. Some of the important or critical cell's locations has to be pre-defined before actual placement and routing stages. The critical cells are mostly the cells related to clocks, viz. clock buffers, clock mux, etc. and also few other cells such as RAM's, ROM,s etc. Since, these cells are placed in to core before placement and routing stage, they are called 'preplaced cells'.

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Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)

  1. 1. Let us assume, the below are the dimensions of the chip Die Core www.vlsisystemdesign.com
  2. 2. Let’s explore how a city is planned www.vlsisystemdesign.com
  3. 3. Let’s explore how a city is planned Railway Hospital Station WaterPlayground Storage Tank www.vlsisystemdesign.com
  4. 4. Basic necessities and utilities are pre-planned and positioned,in a manner to have the best reachability by each citizen Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
  5. 5. In a similar fashion, we start planning the chip area, by prioritizing the locationof critical cells. Die Core www.vlsisystemdesign.com
  6. 6. Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc ) Die Core www.vlsisystemdesign.com
  7. 7. Let us understand, what are IP’s, std cells and their architecture? Die Core www.vlsisystemdesign.com
  8. 8. IP is a reusable unit of logic, cell, or chip layout design that is the intellectualproperty designed by any individual. IP are also sometimes offered as generic gate-level netlist. i.e. standard cells, and complex cells. It consists of transistor level layout for logical cells and complex cells, which are implemented using layout tools. Lets have a look into internal of IP’s www.vlsisystemdesign.com
  9. 9. Consider one of the most commonly used IP i.e. CMOS Inverter Vdd Vdd In Inverter Out In Out Vss Vss www.vlsisystemdesign.com
  10. 10. CMOS Inverter consist of P-MOS Transistor Vdd PMOS – P DiffIn Out Vss www.vlsisystemdesign.com
  11. 11. CMOS Inverter consist of N-MOS Transistor Vdd PMOS – P DiffIn Out NMOS – N Diff Vss www.vlsisystemdesign.com
  12. 12. CMOS Inverter consist of Polysilicon Gate. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff VssNote : At the component level, polysilicon has been used as the conducting gatematerial in MOSFET and CMOS processing technologies. www.vlsisystemdesign.com
  13. 13. CMOS Inverter IN/ OUT Lines Vdd Poly Gate PMOS – P DiffIn Out In NMOS – N Diff Vss www.vlsisystemdesign.com
  14. 14. CMOS Inverter IN/ OUT Ports Vdd Poly Gate PMOS – P DiffIn Out In Out NMOS – N Diff Vss www.vlsisystemdesign.com
  15. 15. CMOS Inverter Vdd & Vss Ports. Vdd Vdd Poly Gate PMOS – P DiffIn Out In Out NMOS – N Diff Vss Vss www.vlsisystemdesign.com
  16. 16. Lets draw preliminary layout of inverter using stick diagram www.vlsisystemdesign.com
  17. 17. Lets draw preliminary layout of inverter using stick diagramStick Diagrams are useful for planning the layout and routing of integrated circuits.Every Line of a conducting material layer is represented by a line of a distinct color. www.vlsisystemdesign.com
  18. 18. Lets draw preliminary layout of inverter using stick diagramStick Diagrams are useful for planning the layout and routing of integrated circuits.Every Line of a conducting material layer is represented by a line of a distinct color. Polysilicon Gate P Diffusion N Diffusion Metal Contact www.vlsisystemdesign.com
  19. 19. P-MOS Transistor represented by Bottle Green Color line PMOS – P Diff P Diff www.vlsisystemdesign.com
  20. 20. N-MOS Transistor represented by a Apple Green Color line PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  21. 21. Polysilicon gates represented by Brown Color linePoly Gate Poly PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  22. 22. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P DiffIn In NMOS – N Diff N Diff www.vlsisystemdesign.com
  23. 23. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P DiffIn In NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  24. 24. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P DiffIn Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  25. 25. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P DiffIn Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  26. 26. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P DiffIn Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  27. 27. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P DiffIn Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  28. 28. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Vdd Poly Poly P Diff P DiffIn Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  29. 29. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  30. 30. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Length (L) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  31. 31. Cell Layout is a Black Box for IP User. Vdd Vdd Width (w) Length (L) Poly Poly P Diff P DiffIn Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  32. 32. In Black Box, internal architecture counts less compared to IP Functionality Vdd Vdd Poly Poly P Diff P DiffIn Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  33. 33. IP’s serves the purpose of the Circuit design i.e. Inverter in this case Vdd Vdd Poly P DiffIn Out In Out N Diff Vss Vss = Contact www.vlsisystemdesign.com
  34. 34. Similarly, other IP’s available as blocks : www.vlsisystemdesign.com
  35. 35. Similarly, other IP’s available as blocks : VddIn1 AND OutIn2 Vss www.vlsisystemdesign.com
  36. 36. Similarly, other IP’s available as blocks : Vdd VddIn1 In1 AND Out OR OutIn2 In2 Vss Vss www.vlsisystemdesign.com
  37. 37. Similarly, other IP’s available as blocks : Vdd Vdd VddIn1 In1 In1 AND Out OR Out NAND OutIn2 In2 In2 Vss Vss Vss www.vlsisystemdesign.com
  38. 38. Complex blocks are also offered as IP’s www.vlsisystemdesign.com
  39. 39. Complex blocks are also offered as IP’s VddIn Out Vss www.vlsisystemdesign.com
  40. 40. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back VddIn Out Vss www.vlsisystemdesign.com
  41. 41. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd VddIn Out In Out Vss Vss Vss www.vlsisystemdesign.com
  42. 42. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd VddIn Out Vss Vss www.vlsisystemdesign.com
  43. 43. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd Vdd Poly Poly P Diff P DiffIn Out In In Out Out N Diff N Diff Vss Vss www.vlsisystemdesign.com
  44. 44. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd VddIn Out In Buffer Out Vss Vss Vss www.vlsisystemdesign.com
  45. 45. IP’s are offered in form of rectangular/square boxes www.vlsisystemdesign.com
  46. 46. IP’s are offered in form of rectangular/square boxesFor E.g. The Buffer IP, will be represented as below www.vlsisystemdesign.com
  47. 47. IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below VddIn Buffer Out Buffer Vss www.vlsisystemdesign.com
  48. 48. IP’s are offered in form of rectangular/square boxesFor E.g. The AND Gate IP, will be represented as below www.vlsisystemdesign.com
  49. 49. IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below VddIn1 AND Out ANDIn2 Vss www.vlsisystemdesign.com
  50. 50. Commonly asked QuestionHow do we differentiate between Vdd and Vss ? www.vlsisystemdesign.com
  51. 51. Commonly asked QuestionHow do we differentiate between Vdd and Vss ?It is represented in below pattern.A Cross line on the bottom left of the Block represents Vss and top corner Vdd www.vlsisystemdesign.com
  52. 52. Commonly asked QuestionHow do we differentiate between Vdd and Vss ?It is represented in below pattern.A Cross line on the bottom left of the Block represents Vss and top corner Vdd Vdd Buffer Buffer Vss Vdd AND AND Vss www.vlsisystemdesign.com
  53. 53. Complex blocks e.g. ALU ALU www.vlsisystemdesign.com
  54. 54. Complex blocks e.g. ALU will be represented as below IP Block ALU www.vlsisystemdesign.com
  55. 55. • Memory is also a Complex IP used commonly.• It is necessary to pre-define the geometrical location of these IP’s on a chip, so that the automated PNR tools do not modify their locations• These cells are referred to as Pre-placed cells www.vlsisystemdesign.com
  56. 56. Die Corewww.vlsisystemdesign.com
  57. 57. Block a Die Core www.vlsisystemdesign.com
  58. 58. Block a Block b Die Core www.vlsisystemdesign.com
  59. 59. Block a Block b Block c Die Core www.vlsisystemdesign.com
  60. 60. Block a Block bPre-placed Cells Block c Die Core www.vlsisystemdesign.com
  61. 61. Thus we have defined the Location of Pre-placed Cell in Chip Block a Block bPre-placed Cells Block c Die Core www.vlsisystemdesign.com

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