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Planning critical cells and IP layout in chip design

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VLSI SYSTEM Design
VLSI SYSTEM Design

https://www.udemy.com/vlsi-academy During placement and routing, most of the placement tools, place/move logic cells based on floorplan specifications. Some of the important or critical cell's locations has to be pre-defined before actual placement and routing stages. The critical cells are mostly the cells related to clocks, viz. clock buffers, clock mux, etc. and also few other cells such as RAM's, ROM,s etc. Since, these cells are placed in to core before placement and routing stage, they are called 'preplaced cells'.

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Let us assume, the below are the dimensions of the chip Die Core www.vlsisystemdesign.com
Let’s explore how a city is planned www.vlsisystemdesign.com
Let’s explore how a city is planned Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
Basic necessities and utilities are pre-planned and positioned, in a manner to have the best reachability by each citizen Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
In a similar fashion, we start planning the chip area, by prioritizing the location of critical cells. Die Core www.vlsisystemdesign.com
Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc ) Die Core www.vlsisystemdesign.com
Let us understand, what are IP’s, std cells and their architecture? Die Core www.vlsisystemdesign.com
IP is a reusable unit of logic, cell, or chip layout design that is the intellectual property designed by any individual.  IP are also sometimes offered as generic gate-level netlist. i.e. standard cells, and complex cells.  It consists of transistor level layout for logical cells and complex cells, which are implemented using layout tools.  Lets have a look into internal of IP’s www.vlsisystemdesign.com
Consider one of the most commonly used IP i.e. CMOS Inverter Vdd Vdd In Inverter Out In Out Vss Vss www.vlsisystemdesign.com
CMOS Inverter consist of P-MOS Transistor Vdd PMOS – P Diff In Out Vss www.vlsisystemdesign.com
CMOS Inverter consist of N-MOS Transistor Vdd PMOS – P Diff In Out NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter consist of Polysilicon Gate. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff Vss Note : At the component level, polysilicon has been used as the conducting gate material in MOSFET and CMOS processing technologies. www.vlsisystemdesign.com
CMOS Inverter IN/ OUT Lines Vdd Poly Gate PMOS – P Diff In Out In NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter IN/ OUT Ports Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss www.vlsisystemdesign.com
CMOS Inverter Vdd & Vss Ports. Vdd Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss Vss www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. www.vlsisystemdesign.com
Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. Polysilicon Gate P Diffusion N Diffusion Metal Contact www.vlsisystemdesign.com
P-MOS Transistor represented by Bottle Green Color line PMOS – P Diff P Diff www.vlsisystemdesign.com
N-MOS Transistor represented by a Apple Green Color line PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
Polysilicon gates represented by Brown Color line Poly Gate Poly PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff www.vlsisystemdesign.com
Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Length (L) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
Cell Layout is a Black Box for IP User. Vdd Vdd Width (w) Length (L) Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
In Black Box, internal architecture counts less compared to IP Functionality Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
IP’s serves the purpose of the Circuit design i.e. Inverter in this case Vdd Vdd Poly P Diff In Out In Out N Diff Vss Vss = Contact www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd In1 AND Out In2 Vss www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd Vdd In1 In1 AND Out OR Out In2 In2 Vss Vss www.vlsisystemdesign.com
Similarly, other IP’s available as blocks : Vdd Vdd Vdd In1 In1 In1 AND Out OR Out NAND Out In2 In2 In2 Vss Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Vdd In Out Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd In Out Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Out Vss Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd In Out Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd Vdd Poly Poly P Diff P Diff In Out In In Out Out N Diff N Diff Vss Vss www.vlsisystemdesign.com
Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Buffer Out Vss Vss Vss www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below Vdd In Buffer Out Buffer Vss www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below www.vlsisystemdesign.com
IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below Vdd In1 AND Out AND In2 Vss www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd www.vlsisystemdesign.com
Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd Vdd Buffer Buffer Vss Vdd AND AND Vss www.vlsisystemdesign.com
Complex blocks e.g. ALU ALU www.vlsisystemdesign.com
Complex blocks e.g. ALU will be represented as below IP Block ALU www.vlsisystemdesign.com
• Memory is also a Complex IP used commonly. • It is necessary to pre-define the geometrical location of these IP’s on a chip, so that the automated PNR tools do not modify their locations • These cells are referred to as Pre-placed cells www.vlsisystemdesign.com
Die Core www.vlsisystemdesign.com
Block a Die Core www.vlsisystemdesign.com
Block a Block b Die Core www.vlsisystemdesign.com
Block a Block b Block c Die Core www.vlsisystemdesign.com
Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com
Thus we have defined the Location of Pre-placed Cell in Chip Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com

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Planning critical cells and IP layout in chip design

  • 1. Let us assume, the below are the dimensions of the chip Die Core www.vlsisystemdesign.com
  • 2. Let’s explore how a city is planned www.vlsisystemdesign.com
  • 3. Let’s explore how a city is planned Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
  • 4. Basic necessities and utilities are pre-planned and positioned, in a manner to have the best reachability by each citizen Railway Hospital Station Water Playground Storage Tank www.vlsisystemdesign.com
  • 5. In a similar fashion, we start planning the chip area, by prioritizing the location of critical cells. Die Core www.vlsisystemdesign.com
  • 6. Crtical cells can be IP’s (memories, ALU, etc.) or std cells (clock Buffer, clock inverter, etc ) Die Core www.vlsisystemdesign.com
  • 7. Let us understand, what are IP’s, std cells and their architecture? Die Core www.vlsisystemdesign.com
  • 8. IP is a reusable unit of logic, cell, or chip layout design that is the intellectual property designed by any individual.  IP are also sometimes offered as generic gate-level netlist. i.e. standard cells, and complex cells.  It consists of transistor level layout for logical cells and complex cells, which are implemented using layout tools.  Lets have a look into internal of IP’s www.vlsisystemdesign.com
  • 9. Consider one of the most commonly used IP i.e. CMOS Inverter Vdd Vdd In Inverter Out In Out Vss Vss www.vlsisystemdesign.com
  • 10. CMOS Inverter consist of P-MOS Transistor Vdd PMOS – P Diff In Out Vss www.vlsisystemdesign.com
  • 11. CMOS Inverter consist of N-MOS Transistor Vdd PMOS – P Diff In Out NMOS – N Diff Vss www.vlsisystemdesign.com
  • 12. CMOS Inverter consist of Polysilicon Gate. Vdd Poly Gate PMOS – P Diff In Out NMOS – N Diff Vss Note : At the component level, polysilicon has been used as the conducting gate material in MOSFET and CMOS processing technologies. www.vlsisystemdesign.com
  • 13. CMOS Inverter IN/ OUT Lines Vdd Poly Gate PMOS – P Diff In Out In NMOS – N Diff Vss www.vlsisystemdesign.com
  • 14. CMOS Inverter IN/ OUT Ports Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss www.vlsisystemdesign.com
  • 15. CMOS Inverter Vdd & Vss Ports. Vdd Vdd Poly Gate PMOS – P Diff In Out In Out NMOS – N Diff Vss Vss www.vlsisystemdesign.com
  • 16. Lets draw preliminary layout of inverter using stick diagram www.vlsisystemdesign.com
  • 17. Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. www.vlsisystemdesign.com
  • 18. Lets draw preliminary layout of inverter using stick diagram Stick Diagrams are useful for planning the layout and routing of integrated circuits. Every Line of a conducting material layer is represented by a line of a distinct color. Polysilicon Gate P Diffusion N Diffusion Metal Contact www.vlsisystemdesign.com
  • 19. P-MOS Transistor represented by Bottle Green Color line PMOS – P Diff P Diff www.vlsisystemdesign.com
  • 20. N-MOS Transistor represented by a Apple Green Color line PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 21. Polysilicon gates represented by Brown Color line Poly Gate Poly PMOS – P Diff P Diff NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 22. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff www.vlsisystemdesign.com
  • 23. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In In NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 24. Metal is represented by Bottle Blue Color line Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 25. Contacts are represented by Black Cross Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff = Contact www.vlsisystemdesign.com
  • 26. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 27. Metal is represented by Bottle Blue Color line Vdd Vdd Poly Gate Poly PMOS – P Diff P Diff In Out In Out NMOS – N Diff N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 28. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 29. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  • 30. Stick Diagrams are converted to Cell Layout by assigning length and width to the Wire Vdd Width (w) Length (L) Poly P Diff In Out N Diff Vss = Contact www.vlsisystemdesign.com
  • 31. Cell Layout is a Black Box for IP User. Vdd Vdd Width (w) Length (L) Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 32. In Black Box, internal architecture counts less compared to IP Functionality Vdd Vdd Poly Poly P Diff P Diff In Out In Out N Diff N Diff Vss Vss = Contact = Contact www.vlsisystemdesign.com
  • 33. IP’s serves the purpose of the Circuit design i.e. Inverter in this case Vdd Vdd Poly P Diff In Out In Out N Diff Vss Vss = Contact www.vlsisystemdesign.com
  • 34. Similarly, other IP’s available as blocks : www.vlsisystemdesign.com
  • 35. Similarly, other IP’s available as blocks : Vdd In1 AND Out In2 Vss www.vlsisystemdesign.com
  • 36. Similarly, other IP’s available as blocks : Vdd Vdd In1 In1 AND Out OR Out In2 In2 Vss Vss www.vlsisystemdesign.com
  • 37. Similarly, other IP’s available as blocks : Vdd Vdd Vdd In1 In1 In1 AND Out OR Out NAND Out In2 In2 In2 Vss Vss Vss www.vlsisystemdesign.com
  • 38. Complex blocks are also offered as IP’s www.vlsisystemdesign.com
  • 39. Complex blocks are also offered as IP’s Vdd In Out Vss www.vlsisystemdesign.com
  • 40. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd In Out Vss www.vlsisystemdesign.com
  • 41. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Out Vss Vss Vss www.vlsisystemdesign.com
  • 42. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd In Out Vss Vss www.vlsisystemdesign.com
  • 43. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd Vdd Poly Poly P Diff P Diff In Out In In Out Out N Diff N Diff Vss Vss www.vlsisystemdesign.com
  • 44. Complex blocks are also offered as IP’s Buffer is nothing but two inverters connected back-to-back Vdd Vdd Vdd In Out In Buffer Out Vss Vss Vss www.vlsisystemdesign.com
  • 45. IP’s are offered in form of rectangular/square boxes www.vlsisystemdesign.com
  • 46. IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below www.vlsisystemdesign.com
  • 47. IP’s are offered in form of rectangular/square boxes For E.g. The Buffer IP, will be represented as below Vdd In Buffer Out Buffer Vss www.vlsisystemdesign.com
  • 48. IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below www.vlsisystemdesign.com
  • 49. IP’s are offered in form of rectangular/square boxes For E.g. The AND Gate IP, will be represented as below Vdd In1 AND Out AND In2 Vss www.vlsisystemdesign.com
  • 50. Commonly asked Question How do we differentiate between Vdd and Vss ? www.vlsisystemdesign.com
  • 51. Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd www.vlsisystemdesign.com
  • 52. Commonly asked Question How do we differentiate between Vdd and Vss ? It is represented in below pattern. A Cross line on the bottom left of the Block represents Vss and top corner Vdd Vdd Buffer Buffer Vss Vdd AND AND Vss www.vlsisystemdesign.com
  • 53. Complex blocks e.g. ALU ALU www.vlsisystemdesign.com
  • 54. Complex blocks e.g. ALU will be represented as below IP Block ALU www.vlsisystemdesign.com
  • 55. • Memory is also a Complex IP used commonly. • It is necessary to pre-define the geometrical location of these IP’s on a chip, so that the automated PNR tools do not modify their locations • These cells are referred to as Pre-placed cells www.vlsisystemdesign.com
  • 56. Die Core www.vlsisystemdesign.com
  • 57. Block a Die Core www.vlsisystemdesign.com
  • 58. Block a Block b Die Core www.vlsisystemdesign.com
  • 59. Block a Block b Block c Die Core www.vlsisystemdesign.com
  • 60. Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com
  • 61. Thus we have defined the Location of Pre-placed Cell in Chip Block a Block b Pre-placed Cells Block c Die Core www.vlsisystemdesign.com