PCI Express Verification
        using
 Reference Modeling

Asad Khan and Scott Morrison
          January 23, 2007

    T...
Purpose
                                                      CPU
                                                      CP...
Outline
•   The Device Under Test (DUT)
•   Reference Model Example: Ingress Port Logic
•   Reference Model Example: Route...
What is a Reference Model?
• A model that is independent of DUT implementation
• Coded in high-level, human-readable langu...
PCI Express Switch
                                                        RX       TX
                                   ...
The DUT
• The DUT (or DUTs, depending how we slice it up)
• Customer deliverable: 4-port Switch ASIC
• Large building bloc...
Design for Verification (DFV)
• Minimize side band controls
• Use a standard bus for module interfaces
   • Standard BFM n...
Module and Chip Verification Strategy

• Bottom-up methodology
   • Reusable
   • Constrained-random stimulus
   • Referen...
A Look at Chip-level Prediction Model

          DUT stimulus              Switch reference model      Scoreboards



    ...
Chip-level Prediction Model: Closer look
                                                        TX TLP

                 ...
IPL: Verification Challenges
• All incoming packets buffered at input
• Infinite memory space challenge
    • Dynamic link...
IPL DUT: How to verify?
DLL TLP Interface                                Internal TLP Interface
                          ...
IPL Reference Model Architecture

e-Code High Level RFM Data Flow
                                          e Link-List Mo...
Reference Model Features
• Cycle and Packet Accuracy (Hybrid Modeling)
   • Cycle accurate route token modeling for chip-l...
IPL Reference Model Architecture (cont.)

e-Code High Level RFM
                                          e Link-List Mode...
Reference Modeling Techniques
• Sub-function blocks coded as a high level units
• Communication between units done through...
Reference Modeling Techniques (cont.)

• Generic data collection monitors for all speeds
• Units coded under eRM guideline...
Coverage and Debug Messages




      IPL RFM
functional coverage




                                     18
Coverage and Debug Messages (cont.)

                 [2712 ns]   IPL_RFM_IAP_GEMN_SCOREBOARD:   =========================...
Cadence vPlan used for IPL Verification

• Verification Planning
   • Preparation
       • Analyze all the relevant docume...
Distributed Routers: “SuperRouter”
 TLP              Upstream Port and Global Control Logic (GCL)                         ...
Router RFM: Why?
1724 pages of specifications

                  PCI Literature
  +
                  PCI Local Bus Specif...
Router RFM: Why? (cont.)
                                     Cycle accurate comparison




                   e coding   ...
Router eRM Architecture
                  Upstream Port and Global Control Logic (GCL)                                   I...
Router eRM Architecture (cont.)



              UPSTREAM’mode                                          MULTIFUNCTION’mode...
Downstream Port Router “e” Environment




                                                                               ...
Router RFM Comparison Logic

   env        : pexrtr_env_u;                     “e” RFM Token Comparison Unit
   bus_name  ...
Techniques of Router RFM
   •   Cycle accurate
   •   when inheritance       plug-in rule sets
   •   Simulation of pseudo...
Moving to chip level
• Building blocks
   •   Multiple RFMs
   •   4 instances of TI PCIe eVC
   •   Top-level register mo...
PCIe Port Reference Model
                   TX TLP                         Example: Downstream Port                      ...
Finished Chip-Level Prediction Model

                                                                                    ...
Conclusions
• Architecture definition to facilitate Design for
  Verification
• RFM methodology requires dedicated and
  s...
Conclusions (cont.)
• RFM will provide dual, independent interpretation of
  specification
• RFM styles: Choose wisely
   ...
Let’s talk




     Questions? Thoughts?




                            34
About the Authors

• Asad Khan (a-khan1@ti.com)
   • Lead Design Verification Engineer for 1394 and PCI Express
     produ...
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Khan and morrison_dq207

  1. 1. PCI Express Verification using Reference Modeling Asad Khan and Scott Morrison January 23, 2007 Texas Instruments Incorporated ASIC / Backplane IP Development
  2. 2. Purpose CPU CPU • We will present – Modeling techniques for the complete verification of a PCI Root Complex Root Complex Express® Switch – Our use of Specman eRM – Block-level to chip-level re-use DUT 4-port PCI Express Switch PCI Express to PCI Express to PCI Bridge PCI Bridge PCIe Endpoint PCIe Endpoint PCIe™ Endpoint PCIe™ Endpoint 2
  3. 3. Outline • The Device Under Test (DUT) • Reference Model Example: Ingress Port Logic • Reference Model Example: Router • Integration of Reference Models at chip-level • Conclusions 3
  4. 4. What is a Reference Model? • A model that is independent of DUT implementation • Coded in high-level, human-readable language • Cycle-accurate prediction where necessary • Because of maintenance overhead • Able to be co-simulated with the DUT to predict and check the runtime behavior • The auto-checking RFM+DUT simulation environment makes use of directed-random stimulus • “Let the machine do the work” 4
  5. 5. PCI Express Switch RX TX PCIe PHY PIPE PCIe PCIe Switch DL / MAC Upstream Port PCIe Switch S Global IPL EPL Control R Router Crossbar De-queue Crossbar Packet Crossbar Legend R PCIe Switch PCIe Switch IPL Ingress Port Logic EPL IPL Downstream Downstream S TL TL PCIe Switch S Scheduler Downstream Port PCIe PCIe PCIe R Router DL / MAC DL / MAC DL / MAC PIPE PIPE PIPE EPL Egress Port Logic PCIe PHY PCIe PHY PCIe PHY TX RX TX RX TX RX 5
  6. 6. The DUT • The DUT (or DUTs, depending how we slice it up) • Customer deliverable: 4-port Switch ASIC • Large building blocks (verified at module level) • Data Link Layer • Ingress Port Memory • Router • Scheduler • Small building blocks • Power management • GPIO • Hot plug • Advanced Error Reporting • And more… 6
  7. 7. Design for Verification (DFV) • Minimize side band controls • Use a standard bus for module interfaces • Standard BFM needed for module simulations • Add DFV signals to reduce verification complexity • Limited variability of pipe-line timing • Limit the number of building blocks • Re-use some blocks even though it is overkill 7
  8. 8. Module and Chip Verification Strategy • Bottom-up methodology • Reusable • Constrained-random stimulus • Reference Models (RFMs) for automated checking • Hybrid approach • Control paths: cycle-accurate modeling • Data paths: packet-accurate modeling • Integration of models for chip-level prediction • Rigorous testing of linked list management, data link layer, routing, and arbitration logic • Some directed testing required 8
  9. 9. A Look at Chip-level Prediction Model DUT stimulus Switch reference model Scoreboards TI PCIe eVC Root Complex Up Up Port Port RFM Switch Prediction Model Supporting PCIe Switch DUT Chip-level Cycle-accurate and Packet-accurate Scoreboard Down Down Down Down Down Down Port 0 Port 1 Port 2 Port 0 Port 1 Port 2 RFM RFM RFM TI TI TI PCIe eVC PCIe eVC PCIe eVC Endpoint Endpoint Endpoint 9
  10. 10. Chip-level Prediction Model: Closer look TX TLP EPL RFM PCIe Switch Port Reference Model Predictor Scheduler RFM Egress TLP Cycle accurate control path Router RFM e Down Port 0 RFM IPL RFM Packet-accurate data path DL RFM RX TLP 10
  11. 11. IPL: Verification Challenges • All incoming packets buffered at input • Infinite memory space challenge • Dynamic link list for en-queue/de-queue of packets • Dual mode support with dynamic behaviors • Cut-through & Store-and-Forward • Aggregation of traffic without back-pressure • Support for normal as well as error packets • Scalability for up to 9 simultaneous de-queues • Support for all permutations of throughputs • Among available ports (x1, x2 and x4) 11
  12. 12. IPL DUT: How to verify? DLL TLP Interface Internal TLP Interface 9 egress ports DLL Mixed traffic DLL TLP Internal TLP SYNC FIFO Processor Processor Dual mode TLP Arbiter TLP TLP TLP Status TLP Memory Memory Status List List Memory Ingress Access Port (IAP) TLP Processor Memory Slot Controller Route Data Buffer Master Broadcast Credit Count Counters Memory Route Crossbar DLL Credit Interface TLP Crossbar De-Queue Crossbar 12
  13. 13. IPL Reference Model Architecture e-Code High Level RFM Data Flow e Link-List Model PORT1 u_epreproc u_erx EXT-PACKET EXT PREPROCESSOR u_ellm u_dq_mgr PKT External-Packet u_pkt_sorter (CYCLE-ACCURATE) DQ PORT2 RX + Link List Manager Packet Manager ERROR DETECTOR SORTER PORT3 u_irx u_illm u_ipreproc INT Internal-Packet INT-PKT PKT Link List Manager PREPROCESSOR RX F G E M N PORT1 PORT9 u_cfr F G E M N PORT2 CTRL ECRC MALF MISC REG u_rab CFR u_rthdr_drv ERROR HEADER SCOREBOARDS RT I/F ROUTE HEADER F G E M N PORT9 HDR DRIVER ARB DATA SCOREBOARDS u_rthdr_scb ROUTE HEADER CYCLE ACCURATE SCOREBOARD 13
  14. 14. Reference Model Features • Cycle and Packet Accuracy (Hybrid Modeling) • Cycle accurate route token modeling for chip-level DV • Packet accurate modeling for packet transmission path • Modular Verification Architecture • Scalability for switch derivatives • Pointer Management Scheme • Independent of Hardware Implementation • Re-usable 14
  15. 15. IPL Reference Model Architecture (cont.) e-Code High Level RFM e Link-List Model PORT1 u_epreproc u_erx EXT-PACKET EXT PREPROCESSOR u_ellm u_dq_mgr PKT External-Packet u_pkt_sorter (CYCLE-ACCURATE) DQ PORT2 RX + Link List Manager Packet Manager ERROR DETECTOR SORTER PORT3 u_irx u_illm u_ipreproc INT Internal-Packet INT-PKT PKT Link List Manager PREPROCESSOR RX F G E M N PORT1 PORT9 u_cfr F G E M N PORT2 CTRL ECRC MALF MISC REG u_rab CFR u_rthdr_drv ERROR HEADER SCOREBOARDS RT I/F ROUTE HEADER F G E M N PORT9 HDR DRIVER ARB DATA SCOREBOARDS u_rthdr_scb ROUTE HEADER CYCLE ACCURATE SCOREBOARD 15
  16. 16. Reference Modeling Techniques • Sub-function blocks coded as a high level units • Communication between units done through ports • A top-level unit binds all the sub-units through ports • Data communicated using structs through ports • Simulator callbacks reduced by using single event from top-level unit fanned out to sub-units • Cycle-accurate information driven through HDL signals between RFMs 16
  17. 17. Reference Modeling Techniques (cont.) • Generic data collection monitors for all speeds • Units coded under eRM guidelines • Design for Verification signals to avoid redundant modeling • Hybrid modeling to reduce maintenance overhead 17
  18. 18. Coverage and Debug Messages IPL RFM functional coverage 18
  19. 19. Coverage and Debug Messages (cont.) [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ================================= [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: DUT TLP : MWr DW4_WD [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: RFM TLP : MWr DW4_WD [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ================================= [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ============================= [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: RFM POINTER 2 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ============================= [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: IAP4 FULL LIST SCOREBOARD IPL RFM [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ============================= debug messages [2712 ns] [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: IPL_RFM_IAP_GEMN_SCOREBOARD: RFM byte DUT byte [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ============================= [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 60 60 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 0 0 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: b0 b0 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: a a [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 1 1 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 0 0 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 2 2 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ff ff [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 12 12 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 34 34 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 56 56 [2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 78 78 19
  20. 20. Cadence vPlan used for IPL Verification • Verification Planning • Preparation • Analyze all the relevant documents • Make sure you have the right people invited to the meeting • Brainstorming session • Capture non-specification coverage • Clarify specification ambiguities/issues Functional / Design Specifications DUT DUT 20
  21. 21. Distributed Routers: “SuperRouter” TLP Upstream Port and Global Control Logic (GCL) Internal Endpoint Function Internal Endpoint Function OHCI USB EHCI USB GCL Upstream Upstream GCL Ingress Ingress Egress Egress Ingress Egress Ingress Egress Port Port Port Port Port Port Port Port Scheduler Scheduler Scheduler Route Token RR0 RS0 RS2 RS2 RS2 RS1 RS1 RS7 RR1A RS3A RS8 RR1B RS3B RS8 RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 Scheduler Scheduler Scheduler Scheduler token Downstream Downstream Downstream Ingress Egress Ingress Egress Ingress Egress PCIe Port 0 PCIe Port 1 PCIe Port 2 Port Port Port Port Port Port 21
  22. 22. Router RFM: Why? 1724 pages of specifications PCI Literature + PCI Local Bus Specification PCI-to-PCI Bridge Specification PCI Bus Power Management Specification + PCI Express Literature PCI Express Base Specification PCI Express to PCI Bridge Specification + TI Functional Specifications Functional Spec for PCIe Switch Functional Spec for Multifunction PCIe Device + RTL Specifications PCI Express Switch Implementation Specification Router Implementation Specification Directed test overload! 22
  23. 23. Router RFM: Why? (cont.) Cycle accurate comparison e coding High level RFM Specifications Interpretation Co-Simulation Compare (1724 pages) Verilog coding RTL DUT 23
  24. 24. Router eRM Architecture Upstream Port and Global Control Logic (GCL) Internal Endpoint Function Internal Endpoint Function OHCI USB EHCI USB GCL Upstream Upstream GCL Ingress Ingress Egress Egress Ingress Egress Ingress Egress Port Port Port Port Port Port Port Port Scheduler Scheduler Scheduler RR0 RS0 RS2 RS2 RS2 RS1 RS1 RS7 RR1A RS3A RS8 RR1B RS3B RS8 RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 Scheduler Scheduler Scheduler Downstream Downstream Downstream Ingress Egress Ingress Egress Ingress Egress PCIe Port 0 PCIe Port 1 PCIe Port 2 Port Port Port Port Port Port 24
  25. 25. Router eRM Architecture (cont.) UPSTREAM’mode MULTIFUNCTION’mode pexrtr_env_u pexrtr_env_u RR0 RS0 RS2 RS2 RS2 RS1 RS1 RS7 RR1 RS3 RS8 RR1 RS3A RS8 A A A TYPE1’hdr_type TYPE0_EHCI’ TYPE0_OHCI’ hdr_type hdr_type DOWNSTREAM’mode pexrtr_env_u RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 RR2 RS4 RS5 RS6 RS6 RS9 TYPE1’hdr_type 25
  26. 26. Downstream Port Router “e” Environment dn_to_self’ 26 slave_type dn_to_dn’ slave_type dn_to_dn’ TRUE’has_reference_model pexrtr_env_u slave_type up_to_dn’ slave_type DOWNSTREAM’kind TYPE1’hdr_type Router eRM Environment TYPE1’ hdr_type e RFM reg_u Config BFM Sideband Signal BFMs Verilog DUT Registers Token Slave Token BFM DN Self SB Token Slave Token BFM DN Peer 0 SB Token Slave Token BFM DN Peer 1 SB Token Slave Token BFM UP Peer SB
  27. 27. Router RFM Comparison Logic env : pexrtr_env_u; “e” RFM Token Comparison Unit bus_name : pexrtr_bus_name_t; pexrtr_rfm_compare_u slave_type : pexrtr_rfm_slave_t; in_token : pexrtr_token_s; From input event in_token_done_e; monitor 1) Daisy chain pre-processing sequential logic. Plug-in 2) Call compare_<type>_token() based on Memory, IO, etc. rule sets 3) Daisy chain post-processing sequential logic. To output scoreboard rfm_token : pexrtr_sch_token_s; event rfm_token_done_e; 27
  28. 28. Techniques of Router RFM • Cycle accurate • when inheritance plug-in rule sets • Simulation of pseudo chip-level SuperRouter • Detailed log files of each transaction • RFM includes text comments explaining expected behavior: Bus mastering disabled, so ignore all Memory TLPs. Previously deemed Malformed. Ignore. In IO window. Blocked. Previously deemed UR. Completion is outside sec-to-sub window, and sec!=0, so claim it. Ignore all internally generated Vendor_Type1 MsgD messages. 28
  29. 29. Moving to chip level • Building blocks • Multiple RFMs • 4 instances of TI PCIe eVC • Top-level register model • Top-level predictor • Top-level scoreboard • Connect the dots • Using TLP ID • Uniquely identify every packet in the entire system for the entire simulation 29
  30. 30. PCIe Port Reference Model TX TLP Example: Downstream Port TX TLP EPL DUT EPL RFM TLP EPL Token ID Scheduler DUT Scheduler RFM TLP ID Egress TLP DQ Token Egress TLP TLP ID Scheduling Token RTL Router DUT Router RFM e TLP ID Route Token IPL DUT IPL RFM RX TLP DL DUT DL RFM RX Data 30
  31. 31. Finished Chip-Level Prediction Model 1) TLP Ingress TI 2) TLP Switching Configuration PCIe eVC Space Register Model Root Complex And 3) TLP Egress Completion Predictor Up Ingress TLP Up Up Port Up Port TLP Up TLP Ingr List TLP Pred FIFO Check Port Port RFM search algorithm Egress TLPs Down Port 0 Down Port 0 TLP Ingress List Switch Prediction Model Ingress TLPs PCIe Switch DUT TLP Ingr List TLP Pred FIFO Check Cycle-accurate and packet-accurate Down Down Down Down Port 1 Down Port 1 TLP Down Down Down TLP Ingr List TLP Pred FIFO Check Port 0 Port 1 Port 2 Port 0 Port 1 Port 2 RFM RFM RFM Down Port 2 Down Port 2 TLP TLP Ingr List TLP Pred FIFO Check TI TI TI PCIe eVC PCIe eVC PCIe eVC Endpoint Endpoint Endpoint TLP ID from each Port Scheduler RFM 31
  32. 32. Conclusions • Architecture definition to facilitate Design for Verification • RFM methodology requires dedicated and specialized Verification Engineer resources • Rigorous block-level simulation permitted 2 days from integration to first chip-level simulation • 2-weeks of chip-level simulations put robust FPGA build in the lab for emulation • “SuperRouter” simulations eliminated lost/misdirected packets at chip-level • Silicon had outstanding performance at Plug Fests and has shown no bugs in RFM features 32
  33. 33. Conclusions (cont.) • RFM will provide dual, independent interpretation of specification • RFM styles: Choose wisely • cycle accurate, packet accurate, hybrid • Muscle of Specman random generation is only as good as the auto-checking features of testbench • RFM hookup at chip-level: • Identify hookup issues, interface violations • Check for chip-level stimulus that was missed at module- level • Chip-level debug acceleration 33
  34. 34. Let’s talk Questions? Thoughts? 34
  35. 35. About the Authors • Asad Khan (a-khan1@ti.com) • Lead Design Verification Engineer for 1394 and PCI Express products • Scott Morrison (scott@ti.com) • Lead Design Verification Engineer for Mixed Signal IP, including high-speed SERDES, USB 2.0 PHY, and 1394 PHY We would appreciate feedback. Feel free to contact us. 35

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