Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)

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Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer, AND, OR gates, buffers) on silicon chip.

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Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)

  1. 1. Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer,AND, OR gates, buffers) on silicon chip. www.vlsisystemdesign.com
  2. 2. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Partition and synthesize larger designs into smaller modules consisting of IP’s and std cells www.vlsisystemdesign.com
  3. 3. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Define width and Height of ‘core’ and ‘Die’ using the physical area of synthesized netlist, utilization factor and aspect ratio www.vlsisystemdesign.com
  4. 4. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Define locations of pre-placed cells www.vlsisystemdesign.com
  5. 5. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Place de-coupling capacitors surrounding pre-placed cells www.vlsisystemdesign.com
  6. 6. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• Power Planning www.vlsisystemdesign.com
  7. 7. Floorplanning is basically the arrangement of logical blocks (i.e.multiplexer, AND, OR gates, buffers) on silicon chip.It is attained by following steps:• IO Pin/Pad placement www.vlsisystemdesign.com
  8. 8. Partition and Synthesize larger designs into smaller modules consisting of IP’s and std cells Can Be any connection or combinationCombinational logic Of logical cells www.vlsisystemdesign.com
  9. 9. Can Be any connection or combinationCombinational logic Of logical cells For Eg. www.vlsisystemdesign.com
  10. 10. Can Be any connection or combinationCombinational logic Of logical cells For Eg. A6 A1 A4Combinational A2 A5 A7 logic A3 www.vlsisystemdesign.com
  11. 11. Can Be any connection or combinationCombinational logic Of logical cells For Eg. www.vlsisystemdesign.com
  12. 12. Can Be any connection or combinationCombinational logic Of logical cells For Eg. A1 A5 A2Combinational A7 A8 logic A3 A6 A4 www.vlsisystemdesign.com
  13. 13. A6 A1 A4Combinational A2 A5 A7 logic A3 www.vlsisystemdesign.com
  14. 14. A6 A1 A4 Combinational A2 A5 A7 logic A3 cut1 A6A1 A4A2 A5 A7 A3 cut2 www.vlsisystemdesign.com
  15. 15. A6 A1 A4 Combinational A2 A5 A7 logic A3 cut1 Block 1 Block 2 A6 A1 A4 A5 A6A1 A4A2 A5 A7 A2 A3 A7 A3 cut2 www.vlsisystemdesign.com
  16. 16. A6 A1 A4 Combinational A2 A5 A7 logic A3 cut1 Block 1 Block 2 A6 A1 A4 A5 A6 A1 A4 A2 A5 A7 A2 A3 A7 A3 cut2Therefore, Block1 and Block2 can be called as IP’s, which are implemented separately,and can be used multiple times in design. www.vlsisystemdesign.com
  17. 17. A6 A1 A4 Combinational A2 A5 A7 logic A3 cut1 Block 1 Block 2 A6 A1 A4 A5 A6A1 A4A2 A5 A7 A2 A3 A7 A3 cut2 www.vlsisystemdesign.com
  18. 18. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 www.vlsisystemdesign.com
  19. 19. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Extend IO pins A1 A4 A5 A6 A2 A3 A7 www.vlsisystemdesign.com
  20. 20. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Extend IO pins A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 www.vlsisystemdesign.com
  21. 21. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 www.vlsisystemdesign.com
  22. 22. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 Separate the Black Boxes as two different IP’s or modules A1 A4 A2 www.vlsisystemdesign.com
  23. 23. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 Separate the Black Boxes as two different IP’s or modules A1 A4 A2 Assign names to Pins and IP’s www.vlsisystemdesign.com
  24. 24. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 Separate the Black Boxes as two different IP’s or modules a A1 A4 o1 b o a c A2 o2 d Assign names to Pins and IP’s www.vlsisystemdesign.com
  25. 25. This is explained as below Block 1 Block 2 A1 A4 A5 A6 A2 A3 A7 Black Box the boxes A1 A4 A5 A6 A2 A3 A7 Separate the Black Boxes as two different IP’s or modules a A1 A4 o1 b Block 1 o a Block 2 c A2 o2 d Assign names to Pins and IP’s www.vlsisystemdesign.com
  26. 26. Let’s Try Another example www.vlsisystemdesign.com
  27. 27. Let’s Try Another example A1 A5 A2Combinational A7 A8 logic A3 A6 A4 www.vlsisystemdesign.com
  28. 28. Let’s Try Another example A1 A5 A2 Combinational A7 A8 logic A3 A6 A4cut1 cut2 A1 A5 A2 A7 A8 A3 A6 A4 www.vlsisystemdesign.com
  29. 29. Let’s Try Another example A1 A5 A2 Combinational A7 A8 logic A3 A6 A4cut1 cut2 Block 1 Block 2 A1 A5 A2 A1 A2 A5 A6 A7 A8 A3 A6 A3 A4 A7 A8 A4 www.vlsisystemdesign.com
  30. 30. A1 A5 A2 Combinational A7 A8 logic A3 A6 A4 cut1 cut2 Block 1 Block 2 A1 A5 A2 A1 A2 A5 A6 A7 A8 A3 A6 A3 A4 A7 A8 A4Therefore, Block1 and Block2 can be called as IP’s, which are implemented separately,and can be used multiple times in design. www.vlsisystemdesign.com
  31. 31. Block 1 Block 2A1 A2 A5 A6A3 A4 A7 A8 www.vlsisystemdesign.com
  32. 32. Block 1 Block 2A1 A2 A5 A6A3 A4 A7 A8 Extend IO pinsA1 A2 A5 A6A3 A4 A7 A8 www.vlsisystemdesign.com
  33. 33. Block 1 Block 2A1 A2 A5 A6A3 A4 A7 A8 Extend IO pinsA1 A2 A5 A6A3 A4 A7 A8 Black Box the boxesA1 A2 A5 A6A3 A4 A7 A8 www.vlsisystemdesign.com
  34. 34. Block 1 Block 2A1 A2 A5 A6A3 A4 A7 A8 Black Box the boxesA1 A2 A5 A6A3 A4 A7 A8 www.vlsisystemdesign.com
  35. 35. Block 1 Block 2 A1 A2 A5 A6 A3 A4 A7 A8 Black Box the boxes A1 A2 A5 A6 A3 A4 A7 A8 Separate the Black Boxes as two different IP’s or modules o1 aa A1 A2 A6b Block 1 o2 b A5 Block 2c o3 c A3 A4 A7 A8 od o4 d Assign names to Pins and IP’s www.vlsisystemdesign.com
  36. 36. • Other combinational logic blocks which have directly offered as IP are Mux, Clock-gating cells, ALU, etc.• These above logical blocks are called as Re-usable blocks, i.e. they are implemented only once, and instantiated in designs where-ever needed as a module or IP. www.vlsisystemdesign.com
  37. 37. www.vlsisystemdesign.com
  38. 38. • ALU is available as a re-usable block (commonly called as IP), which means, this part of the design, need not be re-implemented, but can be instantiated multiple times in design. www.vlsisystemdesign.com
  39. 39. • Similarly, there are other IP’s also available, for eg. Clock – Mux Memory Comparator gating cell• The arrangement of these IP’s in a chip is referred as Floorplanning• These IP’s/blocks have user-defined locations, and hence are placed in chip before automated placement-and-routing and are called as pre-placed cells.• Automated placement and routing tools places the remaining logical cells in the design onto chip www.vlsisystemdesign.com
  40. 40. Block a Block b Block cwww.vlsisystemdesign.com
  41. 41. Block a Block b Block c Block a Block b Block cwww.vlsisystemdesign.com
  42. 42. Block a Block b• The arrangement shown on top occupies Block c minimum area, whereas the one on the bottom occupies larger area on chip, and hence facilitates the user to add more Block a Block b blocks (i.e. additional functionality) in to the chip. Block c www.vlsisystemdesign.com
  43. 43. Block a Block b• The arrangement shown on top occupies Block c minimum area, whereas the one on the bottom occupies larger area on chip, and hence facilitates the user to add more Block a Block b blocks (i.e. additional functionality) in to the chip.• If, the specifications demands for minimum area, the top arrangement is selected, Block c whereas, if the specification demands decent area as well as additional functionality, the bottom arrangement is selected. www.vlsisystemdesign.com
  44. 44. • The abstract level behavioral description of the processor is written using an RTL program.• Large designs (e.g. microprocessor in our case) are usually synthesized into small modules.• These modules are the basic building blocks of a microprocessor e.g. memory unit, adder/subtractor (ALU) unit, multiplexer unit, etc. www.vlsisystemdesign.com
  45. 45. • This is how the floorplan will look like www.vlsisystemdesign.com
  46. 46. • This is how the floorplan will look like• First, we will define the width and height of the core www.vlsisystemdesign.com
  47. 47. • This is how the floorplan will look like• First, we will define the width and height of the core • Then, we will define locations of pre-placed cells www.vlsisystemdesign.com
  48. 48. www.vlsisystemdesign.com
  49. 49. Corewww.vlsisystemdesign.com
  50. 50. Corewww.vlsisystemdesign.com
  51. 51. H Die Core www.vlsisystemdesign.com W
  52. 52. Block a Die Core www.vlsisystemdesign.com
  53. 53. Block a Block b Die Core www.vlsisystemdesign.com
  54. 54. Block a Block b Block c Die Core www.vlsisystemdesign.com
  55. 55. Block a Block bPre-placed Cells Block c Die Core www.vlsisystemdesign.com
  56. 56. Block a Block bPre-placed Cells Block c Die Core www.vlsisystemdesign.com
  57. 57. Block a Block bPre-placed Cells Block c H Die Core www.vlsisystemdesign.com W

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