Interfacing ics for microprocessor

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Interfacing ics for microprocessor

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Interfacing ics for microprocessor

  1. 1. PERIPHERALS AND INTERFACING Prepared By,R-THANDAIAH PRABU M.E., Lecturer - ECE thandaiah@gmail.com
  2. 2. Introduction (cont’d)65,536 possible I/O portsData transfer between ports and the processor is over data bus8088 uses address bus A[15:0] to locate an I/O portAL (or AX) is the processor register that takes input data (or provideoutput data) Data bus AL AX I/O I/O I/O 8088 Address bus A[15:0]
  3. 3. Introduction• I/O devices serve two main purposes – To communicate with outside world – To store data• I/O controller acts as an interface between the systems bus and I/O device – Relieves the processor of low-level details – Takes care of electrical interface• I/O controllers have three types of registers – Data – Command – Status
  4. 4. Introduction (cont’d)
  5. 5. Introduction (cont’d)• To communicate with an I/O device, we need – Access to various registers (data, status,…) • This access depends on I/O mapping – Two basic ways » Memory-mapped I/O » Isolated I/O – A protocol to communicate (to send data, …) • Three types – Programmed I/O – Direct memory access (DMA) – Interrupt-driven I/O
  6. 6. Accessing I/O Devices• I/O address mapping – Memory-mapped I/O • Reading and writing are similar to memory read/write • Uses same memory read and write signals • Most processors use this I/O mapping – Isolated I/O • Separate I/O address space • Separate I/O read and write signals are needed • Pentium supports isolated I/O – 64 KB address space » Can be any combination of 8-, 16- and 32-bit I/O ports – Also supports memory-mapped I/O FFFFF FFFFF Memory addressing I/O space FFFF I/O addressing Memory addressing space space 00000 00000 0000 Direct I/O Memory-mapped I/O
  7. 7. Accessing I/O Devices (cont’d)• Accessing I/O ports in 80x86 – Register I/O instructions in accumulator, port8 ; direct format – Useful to access first 256 ports in accumulator,DX ; indirect format – DX gives the port address – Block I/O instructions • ins and outs – Both take no operands---as in string instructions • ins: port address in DX, memory address in ES:(E)DI • outs: port address in DX, memory address in ES:(E)SI
  8. 8. 8088 Port Addressing SpaceAddressing Space  Accessing directly by instructions FFFF IN AL, 80H IN AX, 6H OUT 3CH, AL OUT 0A0H, AX Accessed through DX  Accessing through DX 00FF 00F8 Accessed IN AL, DX directly by IN AX, DX instructions OUT DX, AL 0000 OUT DX, AX
  9. 9. Input Port Implementation Data Bus Gating Input 8088 device Address bus Decoder Other control signals— The outputs of the gating device are high impedance when the processor is not accessing the input port— When the processor is accessing the input port, the gating device transfers input data to CPU data bus— The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus
  10. 10. Input Port Implementation  Circuit ImplementationA7 Tri-stateA6 Data bus buffer Input dataA5A4A3 CEA2A1A0 RD IO/M
  11. 11. Input Port Implementation
  12. 12. Output Port Implementation Circuit Implementation A7 A6 Data bus Latch Output data A5 A4 A3 CLK A2 A1 A0 WR IO/M
  13. 13. Output Port Implementation
  14. 14. An Example I/O Device• Keyboard – Keyboard controller scans and reports – Key depressions and releases • Supplies key identity as a scan code – Scan code is like a sequence number of the key » Key’s scan code depends on its position on the keyboard » No relation to the ASCII value of the key
  15. 15. Interfacing the Keyboard to 8051 microcontroller• The key board here we are interfacing is a matrix keyboard. This key board is designed with a particular rows and columns. These rows and columns are connected to the microcontroller through its ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 can be easily connected to the rows and columns of the key board.• When ever a key is pressed, a row and a column gets shorted through that pressed key and all the other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates microcontroller that the key is pressed. By this high on the bit key in the corresponding column is identified. SJCET
  16. 16. • Once we are sure that one of key in the key board is pressed next our aim is to identify that key. To do this we firstly check for particular row and then we check the corresponding column the key board.• To check the row of the pressed key in the keyboard, one of the row is made high by making one of bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next out job is to find out the column of the pressed key. The column is detected by contents in the input ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is set.• The contents of the counter is then compared and displayed in the display. This display is designed using a seven segment display and a BCD to seven segment decoder IC 7447.• The BCD equivalent number of counter is sent through output part of 8051 displays the number of pressed key. SJCET
  17. 17.           Circuit diagram of INTERFACING  KEY BOARD TO 8051. SJCET
  18. 18. Circuit diagram of INTERFACING  KEY BOARD TO 8051. SJCET
  19. 19. SJCET
  20. 20. SJCET
  21. 21. • Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller accesses both rows and columns through the port.• The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7,P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of microcontroller 8051 and port P2 is used for displaying the number of pressed key.• Make all rows of port P0 high so that it gives high signal when key is pressed.• See if any key is pressed by scanning the port P1 by checking all columns for non zero condition.• If any key is pressed, to identify which key is pressed make one row high at a time.• Initiate a counter to hold the count so that each key is counted. SJCET
  22. 22. • Check port P1 for nonzero condition. If any nonzero number is there in [accumulator], start column scanning by following step 9.• Otherwise make next row high in port P1.• Add a count of 08h to the counter to move to the next row by repeating steps from step 6.• If any key pressed is found, the [accumulator] content is rotated right through the carry until carry bit sets, while doing this increment the count in the counter till carry is found.• Move the content in the counter to display in data field or to memory location• To repeat the procedures go to step 2. SJCET
  23. 23. A “short list” of embedded systems Anti-lock brakes Modems Auto-focus cameras MPEG decoders Automatic teller machines Network cards Automatic toll systems Network switches/routers Automatic transmission On-board navigation Avionic systems Pagers Battery chargers Photocopiers Camcorders Point-of-sale systems Cell phones Portable video games Printers Cell-phone base stations Satellite phones Cordless phones Scanners Cruise control Smart ovens/dishwashers Curbside check-in systems Speech recognizers Digital cameras Stereo systems Disk drives Teleconferencing systems Electronic card readers Televisions Temperature controllers Electronic instruments Theft tracking systems Electronic toys/games TV set-top boxes Factory control VCR’s, DVD players Fax machines Video game consoles And the list goes Fingerprint identifiers Video phones Home security systems Life-support systems Washers and dryers on and on Medical testing systems
  24. 24. Programmable Keyboard/Display Interface - 8279• A programmable keyboard and display interfacing chip.• Scans and encodes up to a 64-key keyboard. And Controls up to a 16-digit numerical display.• Keyboard section has a built-in FIFO 8 character buffer.• The display is controlled from an internal 16x8 RAM that stores the codeddisplay information.• 8279 has 8 control words to be considered before It is programmed SJCET
  25. 25. PIN DESCRIPTION RETURN LINE RETURN LINE 3 Mhz Interrupt request CONTROL STROB SHIFT KEY RETURN LINE Scan line OUTPUT DISPLAYDATA BUS BLANK DISPLAY CHIP SELECT SJCET 0 DATA 1 CONTROL
  26. 26. Interfacing the 8279 to the Microprocessor • The 8279 is decoded to function at 8-bit I/O address 10H & 11H • 10H – data port • 11H – control port • PAL16l8 is used to decode the I/O address for 8279 • A0 selects either the data or control port • IRQ, since it is a interrupt pin, this signal is not connected to microprocessor. SJCET
  27. 27. 8279 interfaced to 8088 microprocessor : SJCET
  28. 28. Keyboard Interface:• The keyboard matrix can be any size from 2x2 to 8x8.• The I/O port number decoded is the same, 10H & 11H• The 74LS138 drives active low column strobe signals for the keyboard on one line at a time .• Selection Pins SL2-SL0 sequentially scan each column of the keyboard• The internal circuitry of 8279 scans RL pins, searches for key closure.• RL pins incorporate internal pull-ups, no need for external resistor pull-ups. SJCET
  29. 29. Programming the Keyboard Interface :• before any keystroke is detected, the 8279 must be programmed• the first 3 bits of the number sent to the control port (11H) select one of the 8 different control words SJCET
  30. 30. Programming the Keyboard Interface : SJCET
  31. 31. Control Word Description:• First three bits given below select one of 8 control registers (opcode). 000DDMMM• Mode set: Opcode 000. DD sets displays mode. MMM sets keyboard mode.• DD field selects either:• 8- or 16-digit display• Whether new data are entered to the rightmost or leftmost display position. SJCET
  32. 32. I/O Interface• Control Word Description:• MMM field:• Encoded Mode: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15 depending on 8 or 16 digit display.• Decoded Mode: SL outputs are active-low (only one of the four outputs will be low at any time).Pattern output: 1110, 1101, 1011, 0111. SJCET
  33. 33. I/O Interface FIFO status register•Code given in text for reading keyboard.•Data returned from 8279 contains row data that need to betranslated to ASCII: SJCET
  34. 34. I/O InterfaceDisplay Interface• Six Digit Display Interface of 8279• The Interface uses a PAL16L8 to decode the 8279 at I/O Ports• 20H for Data• 21H for Control/Status• The Segment data are supplied to the displays thru the OUTA & OUTB of 8279• Bits are buffered by a segment driver (2003A) to drive the segment inputs to the display SJCET
  35. 35. I/O InterfaceSix Digit Display Interface of 8279 SJCET
  36. 36. 8251 UART• Universal asynchronous receiver transmitter (UART) : provides serial communication.• 8251 functions are integrated into standard PC interface chip. – 8255 used to a be a parallel interface• Allows many communication parameters to be programmed.
  37. 37. Serial communication• Characters are transmitted separately:No char start bit 0 bit 1 ... bit n-1 stop time
  38. 38. Serial communication parameters• Baud (bit) rate.• Number of bits per character.• Parity/no parity.• Even/odd parity.• Length of stop bit (1, 1.5, 2 bits).
  39. 39. 8251 CPU interface status (8 bit)CPU Tx / 8251 Rx data serial (8 bit) port
  40. 40. Programming I/O• Two types of instructions can support I/O: – special-purpose I/O instructions; – memory-mapped load/store instructions.• Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O.• I/O instructions do not preclude memory- mapped I/O.
  41. 41. 8251 USART Interface 8251 RS232D[7:0] TxD RD RD RxD WR WR A0 C/D TxC CLK CLK RxC A7 A6 A5 A4 A3 A2 A1 IO/M
  42. 42. Programming 82518251 mode register 7 6 5 4 3 2 1 0 Mode register Number of Baud Rate Stop bits Parity enable 0: disable 00: Syn. Mode 00: invalid 1: enable 01: x1 clock 01: 1 bit 10: x16 clock 10: 1.5 bits Character length 11: x64 clock 11: 2 bits 00: 5 bits 01: 6 bits Parity 10: 7 bits 0: odd 11: 8 bits 1: even
  43. 43. Programming 82518251 command register EH IR RTS ER SBRK RxE DTR TxE command register TxE: transmit enable DTR: data terminal ready, DTR pin will be low RxE: receiver enable SBPRK: send break character, TxD pin will be low ER: error reset RTS: request to send, CTS pin will be low IR: internal reset EH: enter hunt mode
  44. 44. Programming 8251 8251 status register DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register TxRDY: transmit ready RxRDY: receiver ready TxEMPTY: transmitter empty PE: parity error OE: overrun error FE: framing error SYNDET: sync. character detected DSR: data set ready
  45. 45. PROGRAMMABLE DMA CONTROLLER 8257 SJCET
  46. 46. DMA• Direct memory access (DMA) – Problems with programmed I/O • Processor wastes time polling – In our example » Waiting for a key to be pressed, » Waiting for it to be released • May not satisfy timing constraints associated with some devices – Disk read or write – DMA • Frees the processor of the data transfer responsibility
  47. 47. DMA Example• A hard disk data transfer rate of 5MB/s – One byte every 200 ns !!• A microprocessor hardly can execute even one instruction in 200 ns. – Multiple instructions would be required to accomplish data transfer • read the byte from the hard disk • place it in memory • increment a memory pointer • test for another byte to read
  48. 48. DMA
  49. 49. DMA• DMA is implemented using a DMA controller – DMA controller • Acts as slave to processor • Receives instructions from processor • Example: Reading from an I/O device – Processor gives details to the DMA controller » I/O device number » Main memory buffer address » Number of bytes to transfer » Direction of transfer (memory → I/O device, or vice versa)
  50. 50. DMA• Steps in a DMA operation – Processor initiates the DMA controller • Gives device number, memory buffer pointer, … – Called channel initialization • Once initialized, it is ready for data transfer – When ready, I/O device informs the DMA controller • DMA controller starts the data transfer process – Obtains bus by going through bus arbitration – Places memory address and appropriate control signals – Completes transfer and releases the bus – Updates memory address and count value – If more to read, loops back to repeat the process – Notify the processor when done • Typically uses an interrupt
  51. 51. I/O Data Transfer (cont’d)DMA controller details
  52. 52. 8255 Programmable Peripheral Interface
  53. 53. 8255 Programmable Peripheral Interface
  54. 54. SJCET
  55. 55. • 8255 PPI has three 8-bit registers • Port A (PA) • Port B (PB) • Port C (PC) – These ports are mapped as follows 8255 register Port address PA (input port) 60H PB (output port) 61H PC (input port) 62H Command register 63H
  56. 56. 8255 Programmable Peripheral Interface Data bus D[7:0] PA[7:0] A0 8088 A1 PB[7:0] RD Control port WR PC[7:0] RESET A7 CS A6 A5 A4 A3 A2 A1 A0 Port IO/M 0 0 PA 0 1 PB 1 0 PC 1 1 Control
  57. 57. • Mapping I/O ports is similar to mapping memory – Partial mapping – Full mapping• Keyboard scan code and status can be read from port 60H – 7-bit scan code is available from • PA0 – PA6 – Key status is available from PA7 • PA7 = 0 – key depressed • PA0 = 1 – key released
  58. 58. I/O Data Transfer• Data transfer involves two phases – A data transfer phase • It can be done either by – Programmed I/O – DMA – An end-notification phase • Programmed I/O • Interrupt• Three basic techniques – Programmed I/O – DMA – Interrupt-driven I/O
  59. 59. I/O Data Transfer (cont’d)• Programmed I/O – Done by busy-waiting • This process is called polling• Example – Reading a key from the keyboard involves • Waiting for PA7 bit to go low – Indicates that a key is pressed • Reading the key scan code • Translating it to the ASCII value • Waiting until the key is released
  60. 60. Programming 8255 8255 has three operation modes: mode 0, mode 1, and mode 2
  61. 61. Programming 8255 Mode 0: — Ports A, B, and C can be individually programmed as input or output ports — Port C is divided into two 4-bit ports which are independent from each other Mode 1: — Ports A and B are programmed as input or output ports — Port C is used for handshaking PA[7:0] PA[7:0] PC4 STBA PC7 OBFA PC5 IBFA PC6 ACKA PC3 INTRA PC3 INTRA 8255 PB[7:0] 8255 PB[7:0] PC2 STBB PC2 OBFB PC1 IBFB PC1 ACKB PC0 INTRB PC0 INTRB PC6, 7 PC4, 5
  62. 62. Programming 8255 Mode 2:— PortA is programmed to be bi-directional— Port C is for handshaking— Port B can be either input or output in mode 0 or mode 1 PA[7:0] PC7 OBFA PC6 ACKA PC4 STBA 8255 PC5 IBFA PC3 INTRA PC2 In Out STBB OBFB PC1 In Out IBFB ACKB PC0 In Out INTRB INTRB PB[7:0] Mode 0 Mode 1
  63. 63. INTERRUPT INTRODUCTION • An interrupt is an event which informs the CPU that its service (action) is needed. • Sources of interrupts: – internal fault (e.g.. divide by zero, overflow) – software – external hardware : • maskable • nonmaskable – reset
  64. 64. Basic Procedure for Processing Interrupts • When an interrupt is executed, the mp: – finishes executing its current instruction (if any). – saves (PUSH) the flag register, IP and CS register in the stack. – goes to a fixed memory location. – reads the address of the associated ISR. – Jumps to that address and executes the ISR. – gets (PULL) the flag register, CS:IP register from the stack. – continues executing the previous job (if any).
  65. 65. 8088/86 Hardware Interrupts pins INTR: Interrupt Request. – Input signal into the CPU – If it is activated, the CPU will finish the current instruction and respond with the interrupt acknowledge operation • NMI: NonMaskable interrupt. – Input signal – Examples of use: power failed. Memory error • INTA: Interrupt Acknowledge. – Output signal
  66. 66. Programmable Interrupt Controllers (PIC) SJCET
  67. 67. 8259 Chip• The Intel 8259 is a family of Programmable Interrupt Controllers (PIC) designed and developed for use with the Intel 8085 and Intel 8086 microprocessors. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device.
  68. 68. Pin description• 8-bit bi-directional data bus, one address line is needed, PIC has two control registers to be programmed• The direction of data flow is controlled by RD and WR.• CS is as usual connected to the output of the address decoder.• Interrupt requests are output on INT which is connected to the INTR of the processor. Int. acknowledgment is received by INTA.• IR0-IR7 allow 8 separate interrupt requests to be inputted to the PIC.• sp/en=1 for master , sp/en=0 for slave.• CAS0-3 inputs/outputs are used when more than one PIC to cascaded.
  69. 69. • It is a tool for managing the interrupt requests.• 8259 is a very flexible peripheral controller chip: – PIC can deal with up to 64 interrupt inputs – interrupts can be masked – various priority schemes can also programmed.• originally (in PC ) it is available as a separate IC• Later the functionality of (two PICs) is in the motherboards chipset.• In some of the modern processors, the functionality of the PIC is built in.
  70. 70. • A Programmable Interrupt Controller (PIC) is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities. PIC often allow the cascading of their outputs to inputs between each other.• PIC typically have a common set of registers:• Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask Register (IMR). – The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. – The ISR register specifies which interrupts have been acknowledged, but are still waiting for an End Of Interrupt (EOI). – The IMR specifies which interrupts are to be ignored and not acknowledged.
  71. 71. All interrupt requests must pass through the PIC’s interrupt request register (IRR) and interrupt mask register (IMR). If put in service, the appropriate bit of the in-service (IS) register is set.
  72. 72. 8259 Internal Diagram
  73. 73. Basic Interrupt Event• External device sends an interrupt signal, to one of the Interrupt Request (IR) pin, or an internal interrupt occurs.• The 8259 Chip signal to the CPU the interrupt via the INT pin.• The CPU finishes the present instruction and sends Interrupt Acknowledge (INTA).• The interrupt type is sent to the CPU via the Data bus.• The contents of the flag registers are pushed onto the stack.• Both the interrupt and flags are cleared. This disables the IR pin.• The contents of the code segment register (CS) are pushed onto the Stack.• The contents of the instruction pointer (IP) are pushed onto the Stack.• The interrupt vector contents are fetched, from and then placed into the IP and into the CS so that the next instruction executes at the Interrupt Service Routine (ISR) addressed by the interrupt vector.• While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS and Flag registers are popped from the Stack and return to their state prior to the interrupt.
  74. 74. Modes• Fully Nested mode• Special Fully Nested mode• Nonspecific Rotating• Specific Rotating• Special Mask• Polling
  75. 75. Control Word (initialization)
  76. 76. Operation Command Words• After the Initialization Command Words (ICWs) are programmed into the 8259, the chip is ready to accept interrupt requests at its input lines. However, during the 8259 operation, a selection of algorithms can command the 8259 to operate in various modes through the Operation Command Words.
  77. 77. Example of two cascaded PICs
  78. 78. OPERATION• PIC is to be initialized and programmed to control its operation.• The operation in simple words: when an interrupt occurs , the PIC determines the highest priority, activates the processor via its INTR input, and sends the type number onto the data bus when the processor acknowledges the interrupt.•Priority:What is used in PC is fully nested mode. That is the lowest numbered IRQ input has highest priority. Lower priority interrupts will not be forwarded to the processor until the higher priority interrupts have been serviced.
  79. 79. ICW1, ICW2
  80. 80. ICW3, ICW4
  81. 81. 8259 in PC XTICW1: 13HICW2: 08HICW3: 09H
  82. 82. Interrupt Sources in PC
  83. 83. ADC & DAC SJCET
  84. 84. Why ADC ?• Digital Signal Processing is more popular – Easy to implement, modify – Low cost• Data from real world are typically Analog• Needs conversion system – from raw measurements to digital data – Consists of • Amplifier, Filters • Sample and Hold Circuit, Multiplexer
  85. 85. ADC• Analog-to-Digital converter (ADC): A circuit that converts an analog voltage to digital.
  86. 86. Analog to Digital Conversion ADC V+ref •Input voltage = V) output code = N (MAX) bit n ADC 0110001 0100010 0100100 0101011 : : V-ref :
  87. 87. ADC Major characteristics• n=converted code, V=input voltage,  V − V− ref 1  V+ ref − V− ref n= +  , where ∆V = ,  ∆V 2 −1 N 2  integer e.g V− ref = 0, ∆V = 10mV , see the figure on next page.• The linearity measures how well the transition voltages lie on a straight line.• The differential linearity measures the equality of the step size.
  88. 88. Analog to digital converter example • Convert an analog level to digital output • e.g. V-ref=0V, ∆ V=10mV.
  89. 89. ADC• Conversion Time: The time required to convert an analog voltage to digital.• For an 8-bit ADC: Output = Vin x 255 VrefConversion rate=inverse of conversion time
  90. 90. Converter Errors• Offset Error • Integral Linearity Error• Gain Error • Differential Linearity Error• Can be eliminated by initial • Nonlinear Error adjustments – Hard to remove
  91. 91. Terminologies• Converter Resolution • Conversion Time – The smallest change – Required time (tc) before required in the analog the converter can input of an ADC to provide valid output data change its output code by one level • Converter Throughput Rate• Converter Accuracy – The number of times the – The difference between input signal can be the actual input voltage sampled maintaining full and the full-scale accuracy weighted equivalent of the binary output code – Inverse of the total time – Maximum sum of all required for one successful conversion converter errors including quantization – Inverse of Conversion error time if No S/H(Sample and Hold) circuit is used
  92. 92. S/H increase Performance• S/H (Sample and Hold) – Analog circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversion – Aperture time (ta) • Time delay occurs in S/H circuits between the time the hold command is received and the instant the actual transition to the hold mode takes place • Typically, few nsec
  93. 93. Converting bipolar to unipolar• Using unipolar converter when input signal is bipolar • Input signal is scaled and an offset is added – Scaling down the Add offset input – Adding an offset scaled• Bipolar Converter – If polarity information in output is desired – Bipolar input range • Typically, 0 ~ ± 5V – Bipolar Output • 2’s Complement • Offset Binary • Sign Magnitude
  94. 94. ADC Various Approaches• 3 Basic Types• Digital-Ramp ADC• Successive Approximation ADC• Flash ADC
  95. 95. Digital-Ramp ADC• The output of the DAC is applied to the other terminal of the comparator.• Since the output of the DAC is increasing with the counter, it will trigger the comparator at some point when its voltage exceeds the analog input.• The transition of the comparator stops the binary counter, which at that point holds the digital value corresponding to the analog voltage.
  96. 96. Digital-Ramp ADC• Conversion from analog to digital form inherently involves comparator action where the value of the analog voltage at some point in time is compared with some standard.• A common way to do that is to apply the analog voltage to one terminal of a comparator and trigger a binary counter which drives a DAC.
  97. 97. Counter Type ADC• Block diagram • Operation – Reset and Start Counter – DAC convert Digital output of Counter to Analog signal – Compare Analog input and Output of DAC • Vi < VDAC – Continue counting • Vi = VDAC – Stop counting• Waveform – Digital Output = Output of Counter • Disadvantage – Conversion time is varied • 2n Clock Period for Full Scale input
  98. 98. Tracking Type ADC• Tracking or Servo Type • Can be used as S/H circuit – Using Up/Down – By stopping desired Counter to track input instant signal continuously – Digital Output • For slow varying – Long Hold Time input • Disabling UP (Down) control, Converter generate – Minimum (Maximum) value reached by input signal over a given period
  99. 99. Successive Approximation ADC • Most Commonly used in • Block Diagram medium to high speed Converters • Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved • SAR(Successive Approximation Register) holds the current binary value
  100. 100. Successive Approximation ADC • Circuit waveform • Conversion Time – n clock for n-bit ADC – Fixed conversion time • Serial Output is easily generated – Bit decision are made in serial order
  101. 101. Dual Slope Integrating ADC• Operation – Integrate • Excellent Noise Rejection – Reset and integrate – High frequency noise cancelled out by integration• Applications – Proper T1 eliminates line noise – DPM(Digital Panel Meter), – Easy to obtain good resolution DMM(Digital Multimeter)
  102. 102. Voltage to Frequency ADC• VFC (Voltage to Frequency • Low Speed Converter) • Good Noise Immunity – Convert analog input • High resolution voltage to train of pulses – For slow varying• Counter signal – Generates Digital output – With long conversion by counting pulses over time a fixed interval of time • Applicable to remote data sensing in noisy environments – Digital transmission over a long distance
  103. 103. Flash ADC• The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence.
  104. 104. Parallel or Flash ADC• Very High speed conversion – Up to 100MHz for 8 bit resolution – Video, Radar, Digital Oscilloscope• Single Step Conversion – 2n –1 comparator – Precision Resistive Network – Encoder• Resolution is limited – Large number of comparator in IC
  105. 105. ADC080x, 8-Bit µP Compatible A/D Converters• CMOS 8-bit successive approximation A/D converters that use a differential potentiometer ladder—similar to the 256R products.• These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed.• Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value.• In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
  106. 106. • Compatible with 8080 µP derivatives —no interfacing logic needed - access ADC080x Features time - 135 ns• Easy interface to all microprocessors, or operates “stand alone”• Differential analog voltage inputs• Logic inputs and outputs meet both MOS and TTL voltage level specifications• Works with 2.5V (LM336) voltage reference• On-chip clock generator• 0V to 5V analog input voltage range with single 5V supply• No zero adjust required
  107. 107. ADC080x, interfacing
  108. 108. DACSJCET
  109. 109. Digital-to-Analog Conversion• When data is in binary form, the 0s and 1s may be of several forms such as the TTL form where the logic zero may be a value up to 0.8 volts and the 1 may be a voltage from 2 to 5 volts.• The data can be converted to clean digital form using gates which are designed to be on or off depending on the value of the incoming signal.
  110. 110. Digital-to-Analog Conversion• Data in clean binary digital form can be converted to an analog form by using a summing amplifier.• For example, a simple 4-bit D/A converter can be made with a four-input summing amplifier.
  111. 111. DAC• Parallel Interface: Transfers 8-bits (or more) at once.• Digital-to-Analog Converter (DAC) converts 8-digital data to analog.
  112. 112. Digital to analog converter (DAC) V+ref ( High Reference Voltage) • Output voltage = Vout(n)Input code n(NMAX bit Binary code)0110001 NMAX0100010 (bit length)0100100 DAC0101011:: V-ref (Low Reference Voltage) AD/DA (v.9a) 116
  113. 113. DAC Formula & Resolution• Vout = Input x Vref 256 (for 8-bit)• Vout = DAC output analog voltage• Input = Decimal value of binary input• Vref = Reference DC voltageResolution The worst case error introduced when converting. In an 8-bit DAC, there are 255 possible steps. The resolution is the smallest step size, or 1/255, 0.39%.
  114. 114. Digital-to-analog conversion  x0 20 + x1 21 + x2 22 + K + xn −1 2 n −1  Vout =k n ÷  2  reference voltage in “multiplying” DAC i.e., 00...0 => 0 volts; 11....1 => k volts (slightly less) k / 2n = “step size”
  115. 115. DAC: basic equation DAC output V + ref −V −ref  V+ref Vout (n) = V +n  −ref  NMAX   2  =V + n∆V ∆V −ref V-ref• At n=0, Vout(0) = V-ref• At max. n= 2NMAX -1, – Vout cannot reach V+ref , a kind of tree-planting problem – E.g. NMAX=4, n=0, 1, 2, … 15• Some DACs have internal reference voltage settings, some can be set externally.
  116. 116. DAC: characteristics• Glitch: A transient spike in the output of a DAC that occurs when more than one bit changes in the input code. – Use a low pass filter to reduce the magnitude – Use sample and hold circuit is a better solution• Settling time: Time for the output to settle to typically 1/4 LSB after a change in DA output.
  117. 117. Digital-to-Analog Conversion• 2 Basic Approaches – Weighted Summing Amplifier – R-2R Network Approach
  118. 118. Weighted Sum DAC• One way to achieve D/A conversion is to use a summing amplifier.• This approach is not satisfactory for a large number of bits because it requires too much precision in the summing resistors.• This problem is overcome in the R-2R network DAC.
  119. 119. Weighted Sum DAC
  120. 120. R-2R Ladder DAC
  121. 121. Typical Application

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