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![Ex2
• The number of the core power pad required for each side of the chip
• = total core power / [number of side*core voltage*maximum allowable current for a
I/O pad]
• = 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)
• = 2.278
• ~ 2
• Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.](https://image.slidesharecdn.com/floorplanning-241126141658-46aa8831/75/floor-planning-in-digital-vlsi-design-ppt-42-2048.jpg)
![• Pad to core trunk width (µm)
• = total dynamic core current / number of sides * Jmax where Jmax is the maximum
current density of metal layer used
• = 218.71 mA / [4 * 49.5 mA/µm]
• = 1.104596 µm
• Hence pad to trunk width is kept as 2µm.](https://image.slidesharecdn.com/floorplanning-241126141658-46aa8831/75/floor-planning-in-digital-vlsi-design-ppt-44-2048.jpg)
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floor planning in digital vlsi design .ppt
- 1. 3 AdamTeman, 2018 So, what’s next? • We’ve basically finished the Front-End of the design process and we will now start the Back-End: • To start, we will move between tools with a logical approach to ones with a physical approach to design implementation. • Then, we will make a physical foundation for our design by drawing up a floorplan. • This will include making decisions where “big” or “important” pieces will sit, such as IPs, I/Os, Power grids, special routes, etc. • After that, we can place our gates taking into account congestion and timing. • With our flip-flops in place, we can go about designing a clock-tree. • And finally, we can route all our nets, according to DRCs, timing, noise, etc. • Before tapeout, we will clean things up, verify, etc. Definition and Planning Design and Verification Logic Synthesis Physical Design Signoff and Tapeout Silicon Validation
- 2.
- 3. VLSI Physical Design:From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig
- 4. An illustrative viewof Physical Design 4 Definition and Planning Design and Verification Logic Synthesis Physical Design Signoff and Tapeout Silicon Validation move to P&R tool Initial floorpl and Pad ri ement e Synthes is Prepare an out Detailed Route Clock Tre Design Import Floorplan Placement CTS Route Finish Design
- 5. An illustrative viewof Physical Design 4 Definition and Planning Design and Verification Logic Synthesis Physical Design Signoff and Tapeout Silicon Validation move to P&R tool Initial floorpl and Pad ri ement e Synthes is Prepare an out Detailed Route Clock Tre Design Import Floorplan Placement CTS Route Finish Design
- 6. 5 AdamTeman, 2018 Moving from Logical to Physical • Define design (.v) • Define design constraints/targets (.sdc) • Define operating conditions/modes (MMMC) • Define technology and libraries (.lef) • Define physical properties (Floorplan) Physical Design Flow Verilog netlist SDC constraints GDSII Design Import Floorplan Placement CTS Route Finish Design
- 7. 6 AdamTeman, 2018 Moving from Logical to Physical • During synthesis, our world view was a bit idealistic. • We didn’t care about power supplies. • We didn’t care about physical connections/entities. • We didn’t care about clock non-idealities. • Therefore, in order to start physical implementation: • Define “global nets” and how they connect to physical instances. • Provide technology rules and cell abstracts (.lef files) • Provide physical cells, unnecessary for logical functionality: • Tie cells, P/G Pads, DeCaps, Filler cells, etc. • Define hold constraints and all operating modes and conditions (MMMC) • Hold was “easy to meet” with an ideal clock, so we didn’t really check it… • Set up “low power” definitions, such as voltage domains, power gates, body taps, etc. MV with power gating (shut down) 0.9V 0.7V OFF 0.9V Design Import Floorplan Placement CTS Route Finish Design
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- 9. 9 Introduction ENTITY test is porta: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis
- 10. Floorplanning Goals andObjectives 10 • Floorplanning is a mapping between the logical description (the netlist) and the physical description (the floorplan). • Goals of floorplanning: • Arrange the blocks on a chip. • Decide the location of the I/O pads. • Decide the location and number of the power pads. • Decide the type of power distribution. • Decide the location and type of clock distribution. • Objectives of floorplanning are: • Minimize the chip area • Minimize delay • Minimize routing congestion Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 11. Basic Floorplanning Inputs forfloorplan: Netlist (.v) Technology file (techlef) Timing Library files (.lib) Physical library (.lef) floorplan control parameter: Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio between horizontal routing resources to vertical routing resources (or) ratio of height and width. Aspect ratio = width/height Core utilization:- Utilization will define the area occupied by the standard cells, macros, and other cells.If core utilization is 0.8 (80%) that means 80% of the core area is used for placing the standard cells, macros, and other cells, and the remaining 20% is used for routing purposes. core utilization = (macros area + std cell area +pads area)/ total core area macros provide designers with pre-designed, pre-verified building blocks that streamline the development of complex SOC designs. Soft vs hard
- 12. Fullchip Design Overview 12 •Chip size • Number of Gates • Number of Metal layers • Interface to the outside • Hard IPs/Macros • Power Delivery • Multiple Voltages • Clocking Scheme • Flat or Hierarchical? The location of the core, I/O areas P/G pads and the P/G grid Core placement area Periphery (I/O) area Rings Straps P/G Grid IP ROM RAM Adam Teman, 2018
- 13. Floorplanning Inputs andOutputs 13 • Outputs • Die/block area • I/Os placed • Macros placed • Power grid designed • Power pre-routing • Standard cell placement areas • Design ready for standard cell placement • Inputs • Design netlist (required) • Area requirements (required) • Power requirements (required) • Timing constraints (required) • Physical partitioning information (required) • Die size vs. performance vs. schedule trade-off (required) • I/O placement (optional) • Macro placement information (optional) Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 14. IO Ring 14 • Thepinout is often decided by front-end designers, with input from physical design and packaging engineers. • I/Os do not tend to scale with Moore’s Law and therefore, they are very expensive (in terms of area). • I/Os are not only needed for connecting signals to the outside world, but also to provide power to the chip. • Therefore, I/O planning is a critical and very central stage in Floorplanning the chip. • Let’s leave it at that for a bit, and revisit the I/Os a little later… core IO Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 15. How do wechoose our chip size? 15 Design Import Floorplan Placement CTS Route Finish Design “Core Limited” Adam Teman, 2018 “Pad Limited”
- 16. 18 AdamTeman, 2018 Design Import rplan ement TS oute Floo Plac C R Fini sh Design Utilization • Utilization refers to the percentage of core area that is taken up by standard cells. • A typical starting utilization might be 70% • This can vary a lot depending on the design • High utilization can make it difficult to close a design • Routing congestion, • Negative impact during optimization legalization stages. • Local congestion • Can occur with pin-dense cells like multiplexers, so utilization is not completely sufficient for determining die size. • Run a quick trial route to check for routing congestion • Refine the synthesis or increase routing resources Low standard-cell utilization High standard-cell utilization
- 17. Uniquifying the Netlist 17 •When moving to the physical domain, the netlist must be unique • A unique netlist, means that each sub-module is only referenced once. • In the example, the non-unique netlist cannot optimize instance m1/u1 without changing instance m2/u1 • A synthesized netlist must be uniquified before placement can begin. This can be done either by the synthesizer or during design import. module amod (); BUFFD1 u1 (); endmodule module bmod (); amod m1 ; amod m2 ; endmodule bmod m2 m1 u1 u1 module amod1 (); BUFFD1 u1 (); endmodule module amod2 (); BUFFD1 u1 (); endmodule module bmod (); amod1 m1 ; amod2 m2 ; endmodule Non-unique Unique bmod m2 m1 u1 u1 Adam Teman, 2018
- 18. Hard Macro Placement 18 •When placing large macros we must consider impacts on routing, timing and power. Usually push them to the sides of the floorplan. • Placement algorithms generally perform better with a single large rectangular placement area. • For wire-bond place power hungry macros away from the chip center. • After placing hard macros, mark them as FIXED. Possible routing congestion hotspots Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 21. • What iselectromigration? We will discuss it later in depth. • Electro-migration is the movement or molecular transfer of electrons in the metal from one area to another area that is caused by a high density electric current inflows in the metal. High density current can create voids or hillocks, resulting in increased metal resistance or shorts between wires and it can degrade the ASIC performance • Where • Ngnd = Itotal/Imax • Ngnd = number of ground pads • Itotal = total current in design (sum of static and dynamic currents) • Imax= max EM current
- 22. • Manual macroplacement is done based on the connectivity information of macros to IO pin/pads and macro to macro. Automatic macro placement is more appropriate if the number of macros is large. • Types of macros: Hard macros: The circuit is fixed. We can’t see the functionality information about macros. Only we know the timing information. • Soft macros: The circuit is not fixed and we can see the functionality and which type of gates are using inside it. Also we know the timing information.
- 23. • Place themacros around to the boundary of the core, leaving some space between macro to core edge so that during optimization this space will be used for buffer/inverter insertion and keeping large areas for placement of standard cells during the placement stage. • Macros that are communicating with pins/ports of core place them near to core boundary. • Place the macros of same hierarchy together. • Keep the sufficient channel between macros • channel width = (number of pins * pitch )/ number of layers either horizontal or vertical
- 24. Example • Let’s assumeIf there are two macros having 50 pins and the pitch values are 0.6 and the total number of horizontal and vertical layers are 12. Means M0 M2 M4 M6 M8 M10 are horizontal layers and M1 M3 M5 M7 M9 M11are vertical layers. • Channel width = ((50+50)*0.6)/6= 10 • Notch formation avaoid: because it affects uniform placement density.
- 25. key terms relatedto floorplan • standard cell row: The area allotted for the standard cells on the core is divided into rows where standard cells are placed. fly lines: macros are placed manually using fly lines. fly lines are a virtual connection between macros and macros to IO pads.
- 26. • halo(keep outmargin): This is the region around the fixed macros so that no other macros and standard cell can be placed near to macros boundary • Blockages : Blockages are the specific location where the placing of cells is blocked. • Soft: only buffer can be placed. • prevents from the placement of std cell and hard macro within the specified area during coarse placement but allows placement of buffer/inv during optimization, legalization and clock tree synthesis.
- 27. • Use placementblockages to: • Define std-cells and macro area • Reserve channels for buffer insertion • Prevent cells from being placed at or near macros • Prevent congestion near macros • Soft (Non buffer blockage) • Only buffers can be placed and standard cells cannot be placed. • Hard (Std-cell blockage) • Blocks all std-cells and buffers to be placed. Std-cell blockages are mostly used to: Avoid routing congestion at macro corners • End Cap cells. TAP cells, DECAP cell-power house, spare cells
- 28. Power Planning 1 Moving toPhysical Design 2 MSV 3 Floorplanning 4 Hierarchical Design 5 Power Planning
- 29. Power Consumption andReliability 29 Dynamic Power IR-Drop / Voltage Droop Fail Electromigration (EM) Static Power (Leakage Power) Floorplan + Design of the grid Power density problem in the Long run Average or Instantaneous Power problem Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 30. IR Drop 30 • Thedrop in supply voltage over the length of the supply line • A resistance matrix of the power grid is constructed • The average current of each gate is considered • The matrix is solved for the current at each node, to determine the IR-drop. VDD Pad VDD Minimum Tolerance Level Ideal voltage level Actual voltage level Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 31. Electromigration (EM) 31 • Electromigrationrefers to the gradual displacement of the metal atoms of a conductor as a result of the current flowing through that conductor. • Transfer of electron momentum • Can result in catastrophic failure do to either • Open : void on a single wire • Short : bridging between to wires • Even without open or short, EM can cause performance degradation • Increase/decrease in wire RC Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 32. Design Import Floorplan Placement CTS Route Finish Design PowerDistribution 32 • Power Distribution Network functions • Carry current from pads to transistors on chip • Maintain stable voltage with low noise • Provide average and peak power demands • Provide current return paths for signals • Avoid electromigration & self-heating wearout • Consume little chip area and wire • Easy to lay out More (Wider) Power Lines: • Less Static (IR) drop • Less Dynamic (dI/dt) drop • Less Electromigration More (Wider) Power Lines: • Fewer (signal) routing resources (i.e., higher congestion) Adam Teman, 2018
- 33. Power Distribution Challenge 33 •Assume we have a 1mm long power rail in M1. • Square resistance is given to be 0.1 ohm/square • If we make a 100nm wide rail, what is the resistance of the wire? • Now, given a max current of 1mA/1um, due to Electromigration, what is the IR drop when conducting such a current through this wire? • So what do we do? • Make the power rails as wide and as thick as possible! 103 m R R L W 0.1 1000 100 109 m max max 1μ m drop wire I 1mA 100nm 0.1mA IR I R 104 103 100mV Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 34. 38 After adding asingle wire! Adam Teman, 2018 Hot Spots • We generally map the IR drop of a chip using a color map to highlight “hot spots”, where the IR drop is bad. Design Import Floorplan Placement CTS Route Finish Design Initial IR Drop Mapping Source: Cadence
- 35. 39 AdamTeman, 2018 Power and Ground Routing • Each standard cell or macro has power and ground signals, i.e., VDD (power) and GND (ground) • They need to be connected as well • Power/Ground mesh will allow multiple paths from P/G sources to destinations • Less series resistance • Hierarchical power and ground meshes from upper metal layers to lower metal layers • Multiple vias between layers • You can imagine that they are HUGE NETWORKS! • In general, P/G routings are pretty regular • P/G routing resources are usually reserved Design Import Floorplan Placement CTS Route Finish Design
- 36. 40 AdamTeman, 2018 Standard Approaches to Power Routing • Power Grid • Interconnected vertical and horizontal power bars. • Common on most high-performance designs. • Often well over half of total metal on upper thicker layers used for VDD/GND. • Dedicated VDD/GND planes. • Very expensive. • Only used on Alpha 21264, Dropped on subsequent Alphas. • Simplified circuit analysis. • Some thoughts/trends: • P/G I/O pad co-optimization with classic physical design • Decoupling capacitors to reduce P/G related voltage drop • Multiple voltage/frequency islands make the P/G problem and clock distributions more challenging. Design Import Floorplan Placement CTS Route Finish Design
- 37. 41 Power Grid Creation •Tradeoff IR drop and EM versus routing resources • Require power budget • Initial power estimation • Average current, max current density • Need to determine • General grid structure (gating or multi- voltage?) • Number and location of power pads (per voltage) • Metal layers to be used • Width and spacing of straps • Via stacks versus available routing tracks • Rings / no rings • Hierarchical block shielding • Run initial power network analysis to confirm design Mx Mx-1 Mx-2 Mx Mx-1 Mx-2 Power lines Signal routing area Adam Teman, 2018 Design Import Floorplan Placement CTS Route Finish Design
- 38. Power Grid Creation– Macro Placement 38 Blocks with the highest performance and highest power consumption Close to border power pads (IR drop) Away from each other (EM) Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 39. • For theproper power planning, the estimated power requirements for a VLSI chip is 100mV and the supply voltage is 1 volt. A power ring is of width 2.5 microns. Also, assume there are four sets of supply nets VDD and VSS pads available around the chip. given M8 – 1u width – 10mA current-carrying strength and A square floorplan of width and height equals 1mm. Metal spacing is 25 microns. • Since the power P and voltage V are given, we can calculate the current I using the formula P=VI. Modifying the formula for current i.e. I = P/V implies I = 100mW/1v = 100mA. Here comes the total current estimated I is 100 milliamperes.
- 40. • Since thereare four VDD pads, then each pad will consume 100mA/4 = 25mA of current. • A 1u width M8 metal element is carrying a current of 10mA and therefore for a 2.5u width of M8 element power ring will carry a current of 2.5mA. • Now we need to calculate the number of vertical stripes and the width of the stripes required. • The number of stripes would be the ratio of core width to the spacing between the metals. hence the number of stripes = 1mm/25u = 40 number of vertical stripes.
- 41. • The widthof these vertical stripes can be calculated by the formula is the ratio of the width of the power ring upon the total number of vertical stripes. which is 2.5u / 40 = 0.625 micron • The number of horizontal stripes and width of the stripes required is • The number of stripes would be the ratio of core height to the spacing between the metals. hence the number of stripes = 1mm/25u = 40 number of horizontal stripes. • The width of these horizontal stripes can be calculated by the formula is the ratio of the width of the power ring upon the total number of horizontal stripes. which is 2.5u / 40 = 0.625 micron.
- 42. Ex2 • The numberof the core power pad required for each side of the chip • = total core power / [number of side*core voltage*maximum allowable current for a I/O pad] • = 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM) • = 2.278 • ~ 2 • Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.
- 43. • Total dynamiccore current (mA) • = total dynamic core power / core voltage • = 236.2068mW / 1.08V • = 218.71 mA • Core PG ring width • = (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer • used (Jmax) for PG ring)=218.71 mA/(4*49.5 mA/µm)~1.1 µm~2 µm VLSI Physical Design: Power Planning Basics (vlsijunction.com)
- 44. • Pad tocore trunk width (µm) • = total dynamic core current / number of sides * Jmax where Jmax is the maximum current density of metal layer used • = 218.71 mA / [4 * 49.5 mA/µm] • = 1.104596 µm • Hence pad to trunk width is kept as 2µm.
- 45. Summary – Floorplanningin Innovus • • Define Global nets • • Tell the tool what the names of the global nets (VDD, GND) are and what their names are in the IPs. • • Create Power Rings • • Often rings for VDD, GND are placed around the chip periphery, as well as around each individual hard IP. • • Build Power Grid 45 • Connect standard cell ‘follow pins’ • Build power stripes on metal layers • Make sure power connects to hard IPs robustly • Assign Pins • If working on a block (not fullchip), assign pins to the periphery of the floorplan. Design Import Floorplan Placement CTS Route Finish Design Init Design Specify Floorplan Place Hard Macros Regions & Blockages Global Nets Power Rings Power Grid Pin Assignment Adam Teman, 2018
- 46. Summary – Floorplanningin Innovus 46 • Floorplanning is very specific to each design and can include many commands, but the general flow is: • Initialize Design: • Define Verilog netlist, MMMC (timing, SDC, extraction, etc.), LEF, IO placement • Specify floorplan • Define floorplan size, aspect ratio, target utilization • Place hard macros • Absolute or relative placement • Define halos and blockages around macros • Define regions and blockages • If necessary, define placement regions and placement blockage • If necessary, define routing blockage Design Import Floorplan Placement CTS Route Finish Design Init Design Specify Floorplan Place Hard Macros Regions & Blockages Adam Teman, 2018
- 47. How do wedefine this? 47 • • But, in general, there is a command format for this. • Well, actually two. • Cadence calls theirs CPF (Common Power Format), and it’s surprisingly (…confusingly) similar to MMMC. • Synopsys calls theirs UPF (Unified Power Format), and it’s surprisingly similar to SDC. • I guess neither is very common or unified… • Luckily for you, we will not talk any more about this right now . • Instead, we’ll start with the basics of Floorplanning. Design Import Floorplan Placement CTS Route Finish Design Adam Teman, 2018
- 48. I/O Planning • Planningof input and output pins or pads is very important. Earlier we have seen that Corner cells are placed at the four corners of an IC. The dimension of corner cells for our technology is (250times 250). The I/O pads have dimension of (250times 65). This means the I/O pads have width of 65 um. In the case of the simple 4-bit counter there are 4 I/Os at each side. Say, the total area for the IC is 1000 mu m^2. Then the gap between the I/O pads is X. The value of X can be found out as • 1000 = (4times 65)+ (2times 250) - 5X • Thus X = 240/5=48