The document discusses input/output (I/O) system design and the 8255 programmable peripheral interface chip. It provides three key points: 1. The 8255 PPI chip has three 8-bit I/O ports (ports A, B, and C) that can be configured for input or output. It supports three operating modes for controlling data transfer and handshaking. 2. The keyboard and printer are examples of I/O devices that can be interfaced using the 8255 ports. The keyboard scan code and status can be read from port A, while data can be sent to the printer through port B. 3. There are three main techniques for I/O data

1. 4446 Design of Microprocessor-Based Systems
I/O System Design
Dr. Esam Al_Qaralleh
CE Department
Princess Sumaya University for Technology
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2. Introduction (cont’d)
 65,536 possible I/O ports
 Data transfer between ports and the processor is over data bus
 8088 uses address bus A[15:0] to locate an I/O port
 AL (or AX) is the processor register that takes input data (or provide
output data)
Data bus
AL
AX
I/O I/O I/O
8088
Address bus A[15:0]
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3. Introduction
• I/O devices serve two main purposes
– To communicate with outside world
– To store data
• I/O controller acts as an interface between the systems bus
and I/O device
– Relieves the processor of low-level details
– Takes care of electrical interface
• I/O controllers have three types of registers
– Data
– Command
– Status
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4. Introduction (cont’d)
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5. Introduction (cont’d)
• To communicate with an I/O device, we need
– Access to various registers (data, status,…)
• This access depends on I/O mapping
– Two basic ways
» Memory-mapped I/O
» Isolated I/O
– A protocol to communicate (to send data, …)
• Three types
– Programmed I/O
– Direct memory access (DMA)
– Interrupt-driven I/O
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6. Accessing I/O Devices
• I/O address mapping
– Memory-mapped I/O
• Reading and writing are similar to memory read/write
• Uses same memory read and write signals
• Most processors use this I/O mapping
– Isolated I/O
• Separate I/O address space
• Separate I/O read and write signals are needed
• Pentium supports isolated I/O
– 64 KB address space
» Can be any combination of 8-, 16- and 32-bit I/O ports
– Also supports memory-mapped I/O
FFFFF FFFFF
Memory
addressing I/O
space FFFF I/O
addressing Memory addressing
00000 space
00000 0000 space 11-6
Direct I/O Memory-mapped I/O

7. Accessing I/O Devices (cont’d)
• Accessing I/O ports in 80x86
– Register I/O instructions
in accumulator, port8 ; direct format
– Useful to access first 256 ports
in accumulator,DX ; indirect format
– DX gives the port address
– Block I/O instructions
• ins and outs
– Both take no operands---as in string instructions
• ins: port address in DX, memory address in ES:(E)DI
• outs: port address in DX, memory address in ES:(E)SI
• We can use rep prefix for block transfer of data
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8. 8088 Port Addressing Space
 Addressing Space
 Accessing directly by instructions
IN AL, 80H
FFFF IN AX, 6H
OUT 3CH, AL
OUT 0A0H, AX
Accessed
 Accessing through DX
through
DX IN AL, DX
00FF IN AX, DX
Accessed OUT DX, AL
00F8
directly by OUT DX, AX
instructions
0000
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9. Input Port Implementation
Data Bus
Gating Input
8088 device
Address bus
Decoder
Other control
signals
— The outputs of the gating device are high impedance when the processor is not
accessing the input port
— When the processor is accessing the input port, the gating device transfers input
data to CPU data bus
— The decoding circuit controls when the gating device has high impedance output
and when it transfers input data to data bus
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10. Input Port Implementation
 Circuit Implementation
— Assume that the address of the input port is 9CH
A7 Tri-state
A6 Data bus Input data
A5 buffer
A4
A3 CE
A2
A1
A0
RD IO/M
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11. Input Port Implementation
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12. Output Port Implementation
 Circuit Implementation
— Assume that the address of the output port is 9CH
A7
A6 Data bus Latch Output data
A5
A4
A3 CLK
A2
A1
A0
WR IO/M
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13. Output Port Implementation
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14. A Reconfigurable Port Decoder
1 Vcc
A=B R
A7 A3 B3
A6 A2 B2
A5 A1 B1
A4 A0 B0
A=B
A=B
A3 A3 B3
A2 B2
A2
A1 A1 B1
A0 A0 B0
A=B
RD or WR
IO/M
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15. An Example I/O Device
• Keyboard
– Keyboard controller scans and reports
– Key depressions and releases
• Supplies key identity as a scan code
– Scan code is like a sequence number of the key
» Key’s scan code depends on its position on the keyboard
» No relation to the ASCII value of the key
– Interfaced through an 8-bit parallel I/O port
• Originally supported by 8255 programmable peripheral
interface chip (PPI)
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16. An Example I/O Device (cont’d)
• 8255 PPI has three 8-bit registers
• Port A (PA)
• Port B (PB)
• Port C (PC)
– These ports are mapped as follows
8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
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17. An Example I/O Device (cont’d)
Mapping of 8255 I/O ports
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18. An Example I/O Device (cont’d)
• Mapping I/O ports is similar to mapping memory
– Partial mapping
– Full mapping
• Keyboard scan code and status can be read from
port 60H
– 7-bit scan code is available from
• PA0 – PA6
– Key status is available from PA7
• PA7 = 0 – key depressed
• PA0 = 1 – key released
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19. I/O Data Transfer
• Data transfer involves two phases
– A data transfer phase
• It can be done either by
– Programmed I/O
– DMA
– An end-notification phase
• Programmed I/O
• Interrupt
• Three basic techniques
– Programmed I/O
– DMA
– Interrupt-driven I/O
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20. I/O Data Transfer (cont’d)
• Programmed I/O
– Done by busy-waiting
• This process is called polling
• Example
– Reading a key from the keyboard involves
• Waiting for PA7 bit to go low
– Indicates that a key is pressed
• Reading the key scan code
• Translating it to the ASCII value
• Waiting until the key is released
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21. 8255 Programmable Peripheral
Interface
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22. 8255 Programmable Peripheral Interface
Data bus
D[7:0]
PA[7:0]
A0
8088 A1 PB[7:0]
RD Control port
WR PC[7:0]
RESET
A7 CS
A6
A5
A4
A3
A2 A1 A0 Port
IO/M
0 0 PA
0 1 PB
3 0 PC
1 1 Control
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23. 8255 Programmable Peripheral Interface
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24. Programming 8255
 8255 has three operation modes: mode 0, mode 1, and mode 2
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25. Programming 8255
 Mode 0:
— Ports A, B, and C can be individually programmed as input or output ports
— Port C is divided into two 4-bit ports which are independent from each other
 Mode 1:
— Ports A and B are programmed as input or output ports
— Port C is used for handshaking
PA[7:0] PA[7:0]
PC4 STBA PC7 OBFA
PC5 IBFA PC6 ACKA
PC3 INTRA PC3 INTRA
8255 PB[7:0] 8255 PB[7:0]
PC2 STBB PC2 OBFB
PC1 IBFB PC1 ACKB
PC0 INTRB PC0 INTRB
PC6, 7 PC4, 5 11-25

28. Programming 8255
 Mode 2:
— Port A is programmed to be bi-directional
— Port C is for handshaking
— Port B can be either input or output in mode 0 or mode 1
PA[7:0]
PC7 OBFA
PC6 ACKA
PC4 STBA
8255 PC5 IBFA
PC3 INTRA
PC0 In Out STBB OBFB
PC0 In Out IBFB ACKB
PC0 In Out INTRB INTRB
PB[7:0]
Mode 0 Mode 1
1. Can you design a decoder for an 8255 chip such that its base address is 40H?
2. Write the instructions that set 8255 into mode 0, port A as input, port B as output,
PC0-PC3 as input, PC4-PC7 as output ?
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29. Timing diagram is a combination of the Mode 1 Strobed Input
and Mode 1 Strobed Output Timing diagrams.

30. Example: Mode 1 Input
8255 keyboard
PA0
• BIT5 EQU 20H
• PORTC EQU 22H PA7
• PORTA EQU 20H
• READ STB
PROC NEAR PC4 DAV
• Read:
– IN AL, PORTC ; read portc
– TEST AL, BIT5 ;test IBF
– JZ Read ;if IBF=0
– IN AL, PORTA ;Read Data
• READ ENDP
11-30

31. Example: Mode 1 output
8255 Printer
PB0
PB7
ACK Data Strobe : to tell
PC2 ACK the printer to latch the
incoming data.
PC4 DS
Generated Externally
11-31

32. Example: Mode 1 output
BIT1 EQU 2 ;send character to printer
PORTC EQU 62H MOV AL, AH ;get data
OUT PORTB, AL ;print data
PORTB EQU 61H
; send data strobe to printer
CMD EQU 63H MOV AL, 8 ;clear DS
PRINT PROC NEAR OUT CMD, AL
; check printer ready? MOV AL, 9 ;clear DS
IN AL, PORTC ;get OBF OUT CMD, AL
TEST AL, BIT1 ;test OBF ;rising the data at the positive
JZ PRINT ;if OBF=0 buffer is edge of DS
full RET
PRINT ENDP
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33. Keyboard example 1/2
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34. Keyboard example 2/2
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35. Bouncing Problem
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36. Bouncing
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37. Software Solution
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38. De-bouncing Circuitry
Two asynchronous flip-flop solutions are given below
• The basic idea is that these flip-flops store the values even if the D/D
nodes both float
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39. Another Solution
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40. External Interface
• Two ways of interfacing I/O devices
– Serial
• Cheaper
• Slower
– Parallel
• Faster
• Data skew
• Limited to small distances
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41. External Interface (cont’d)
Two basic modes of data transmission
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42. External Interface (cont’d)
• Serial transmission
– Asynchronous
• Each byte is encoded for transmission
– Start and stop bits
• No need for sender and receiver synchronization
– Synchronous
• Sender and receiver must synchronize
– Done in hardware using phase locked loops (PLLs)
• Block of data can be sent
• More efficient
– Less overhead than asynchronous transmission
• Expensive
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43. External Interface (cont’d)
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44. External Interface (cont’d)
Asynchronous transmission
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45. External Interface (cont’d)
• EIA-232 serial interface
– Low-speed serial transmission
– Adopted by Electronics Industry
Association (EIA)
• Popularly known by its predecessor
RS-232
– It uses a 9-pin connector DB-9
• Uses 8 signals
– Typically used to connect a modem
to a computer
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46. External Interface (cont’d)
• Transmission protocol uses three phases
– Connection setup
• Computer A asserts DTE (Data Terminal Equipment) Ready
– Transmits phone# via Transmit Data line (pin 2)
• Modem B alerts its computer via Ring Indicator (pin 9)
– Computer B asserts DTE Ready (pin 4)
– Modem B generates carrier and turns its DCE (Data Communication
Equipment) Ready
• Modem A detects the carrier signal from modem B
– Modem A alters its computer via Carrier Detect (pin 1)
– Turns its DCE Ready
– Data transmission
• Done by handshaking using
– request-to-send (RTS) and clear-to-send (CTS) signals
– Connection termination
• Done by deactivating RTS
11-46

47. External Interface (cont’d)
• Parallel printer interface
– A simple parallel interface
– Uses 25-pin DB-25
• 8 data signals
– Latched by strobe (pin 1)
• Data transfer uses simple handshaking
– Uses acknowledge (CK) signal
» After each byte, computer waits for ACK
• 5 lines for printer status
– Busy, out-of-paper, online/offline, autofeed, and fault
• Can be initialized with INIT
– Clears the printer buffer and resets the printer
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48. External Interface (cont’d)
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49. Serial Data Transfer
 Asynchronous v.s. Synchronous
— Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication
— Synchronous transfer does not transfer extra bits. However, it requires clock signal
Frame
Asynchronous data
Data transfer
Start
bit B0 B1 B2 B3 B4 B5 B6 Stop bits
Parity
clk
Synchronous
Data transfer
data
B0 B1 B2 B3 B4 B5
Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity). 11-49

50. 8251 USART Interface
8251 RS232
D[7:0] TxD
RD RD RxD
WR WR
A0 C/D
TxC
CLK CLK RxC
A7
A6
A5
A4
A3
A2
A1
IO/M
11-50

51. 11-51

52. Programming 8251
 8251 mode register
7 6 5 4 3 2 1 0 Mode register
Number of Baud Rate
Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
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53. Programming 8251
 8251 command register
EH IR RTS ER SBRK RxE DTR TxE command register
TxE: transmit enable
DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER: error reset
RTS: request to send, CTS pin will be low
IR: internal reset
EH: enter hunt mode
11-53

54. Programming 8251
 8251 status register
DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register
TxRDY: transmit ready
RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
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55. Simple Serial I/O Procedures
 Read  Write
start start
Check RxRDY Check TxRDY
No No
Is it logic 1? Is it logic 1?
Yes Yes
Read data register* Write data register*
end end
* This clears RxRDY * This clears TxRDY
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56. Errors
– Parity error: Received data has wrong error --
transmission bit flip due to noise.
– Framing error: Start and stop bits not in their proper
places.
• This usually results if the receiver is receiving data at the
incorrect baud rate.
– Overrun error: Data has overrun the internal receiver
FIFO buffer.
• Software is failing to read the data from the FIFO.
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57. Programmable Timer 8254
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58. 8254 Programming
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59. 8254 Programming
• Each counter may be programmed with a
count of 1 to FFFFH.
– Minimum count is 1 all modes except 2 and 3
with minimum count of 2.
• Each counter has a program control word
used to select the way the counter operates.
– If two bytes are programmed, then the first byte
(LSB) stops the count, and the second byte
(MSB) starts the counter with the new count.
11-59

60. 8254 Read Back Command
 8254 Read Back Command
1 1 COUNT STATUS CNT2 CNT1 CNT0 0
 8254 status word format
NULL
OUTPUT COUNT RW1 RW0 M2 M1 M0 BCD
NULL COUNT: goes low when the new count written to a counter is
actually loaded into the counter
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61. 8254 Modes
• Mode 0: An events counter enabled with G.
– The output becomes a logic 0 when the control word is written and
remains there until N plus the number of programmed counts.
Mode 1: One-shot mode.
– The G input triggers the counter to output a 0 pulse for `count' clocks.
– Counter reloaded if G is pulsed again.
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62. 8254 Modes
• Mode 2: Counter generates a series of pulses 1 clock pulse wide.
– The seperation between pulses is determined by the count.
– The cycle is repeated until reprogrammed or G pin set to 0.
– Mode 3: Generates a continuous square-wave with G set to 1.
• If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.
11-62

63. 8254 Modes
• Mode 4: Software triggered one-shot
– (G must be 1).
• Mode 5: Hardware triggered one-shot. G
controls similar to Mode 1.
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64. Motor Control
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65. Motor Control
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66. 11-66

67. DMA
• Direct memory access (DMA)
– Problems with programmed I/O
• Processor wastes time polling
– In our example
» Waiting for a key to be pressed,
» Waiting for it to be released
• May not satisfy timing constraints associated with some
devices
– Disk read or write
– DMA
• Frees the processor of the data transfer responsibility
11-67

68. DMA Example
• A hard disk data transfer rate of 5MB/s
– One byte every 200 ns !!
• A microprocessor hardly can execute even
one instruction in 200 ns.
– Multiple instructions would be required to
accomplish data transfer
• read the byte from the hard disk
• place it in memory
• increment a memory pointer
• test for another byte to read
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69. DMA
11-69

70. DMA
• DMA is implemented using a DMA controller
– DMA controller
• Acts as slave to processor
• Receives instructions from processor
• Example: Reading from an I/O device
– Processor gives details to the DMA controller
» I/O device number
» Main memory buffer address
» Number of bytes to transfer
» Direction of transfer (memory → I/O device, or vice versa)
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71. DMA
• Steps in a DMA operation
– Processor initiates the DMA controller
• Gives device number, memory buffer pointer, …
– Called channel initialization
• Once initialized, it is ready for data transfer
– When ready, I/O device informs the DMA controller
• DMA controller starts the data transfer process
– Obtains bus by going through bus arbitration
– Places memory address and appropriate control signals
– Completes transfer and releases the bus
– Updates memory address and count value
– If more to read, loops back to repeat the process
– Notify the processor when done
• Typically uses an interrupt
11-71

72. I/O Data Transfer (cont’d)
DMA controller details
11-72