SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT I Core of Embedded SystemsArti Parab Academics
Core of embedded systems: microprocessors and microcontrollers, RISC and CISC controllers, Big endian and Little endian processors, Application specific ICs, Programmable logic devices, COTS, sensors and actuators, communication interface, embedded firmware, other system components.
Challenges faced during embedded system design:
The challenges in design of embedded systems have always been in the same limiting requirements for decades: Small form factor; Low energy; Long-term stable performance without maintenance.
SYBSC IT SEM IV EMBEDDED SYSTEMS UNIT I Core of Embedded SystemsArti Parab Academics
Core of embedded systems: microprocessors and microcontrollers, RISC and CISC controllers, Big endian and Little endian processors, Application specific ICs, Programmable logic devices, COTS, sensors and actuators, communication interface, embedded firmware, other system components.
Challenges faced during embedded system design:
The challenges in design of embedded systems have always been in the same limiting requirements for decades: Small form factor; Low energy; Long-term stable performance without maintenance.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
Introduction to Cellular Mobile System,
Performance criteria,
uniqueness of mobile radio environment,
operation of cellular systems,
Hexagonal shaped cells,
Analog Cellular systems.
Digital Cellular systems
How to put these nodes together to form a meaningful network.
How a network should function at high-level application scenarios .
On the basis of these scenarios and optimization goals, the design of networking protocols in wireless sensor networks are derived
A proper service interface is required and integration of WSNs into larger network contexts.
Unit 1 Introduction to Embedded computing and ARM processorVenkat Ramanan C
INTRODUCTION TO EMBEDDED COMPUTING AND ARM PROCESSORS
Complex systems and microprocessors – Embedded system design process – Formalism for system design– Design example: Model train controller- ARM Processor Fundamentals- Instruction Set and Programming using ARM Processor.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
Introduction to Cellular Mobile System,
Performance criteria,
uniqueness of mobile radio environment,
operation of cellular systems,
Hexagonal shaped cells,
Analog Cellular systems.
Digital Cellular systems
How to put these nodes together to form a meaningful network.
How a network should function at high-level application scenarios .
On the basis of these scenarios and optimization goals, the design of networking protocols in wireless sensor networks are derived
A proper service interface is required and integration of WSNs into larger network contexts.
Unit 1 Introduction to Embedded computing and ARM processorVenkat Ramanan C
INTRODUCTION TO EMBEDDED COMPUTING AND ARM PROCESSORS
Complex systems and microprocessors – Embedded system design process – Formalism for system design– Design example: Model train controller- ARM Processor Fundamentals- Instruction Set and Programming using ARM Processor.
1.CPU INSTRUCTION AND EXECUTION CYCLEThe primary function of the .pdfaniyathikitchen
1.CPU INSTRUCTION AND EXECUTION CYCLE:
The primary function of the cpu of a computer is to execute the sequence of instructions stored
ina memory which is an external to the cpu.The cpu must first fetch an instruction from the
memory before it can be executed .The sequence of operations involved in processing an
instruction constitutes an instruction cycle.This can be sub divided into two major phases i.e.,
fetch phase and execution phase.These two phases are performed in two cosecutive time slots
under the control of a clock.Hence these two operations are called as cycles .The time needed to
complete the execution of an instruction is known as INSTRUCTION CYCLE time .
a.FETCH CYCLE:The instruction is obtained from main memory during the fetch cycle.The
fetch operation can be described as \"send the address of the next instruction to memory and
recieve the instruction from the memory\".
b.EXECUTION CYCLE:The execution cycle includes decoding the instruction fetching of the
required operand and performing the operations specified by aninstructions opcode.In other
words it can be stated as \"Decode the fetched instruction if the operand is specified in the
memory then fetch that operand and execute the instruction \".
**INSTRUCTION CYCLE:
Thus the fetch and execute operations are carried out in synchronism with a clock is known as
instruction cycle i.e.,IC=FC+EC.
3.a.INSTUCTION FORMAT:Instruction format has one or more number of fields.The first field
is called as operation code field or opcode fielde which indicates type of operations to be
performed by the cpu.It also contains other fields known as operand fields.The cpu executes the
instructions using the information which resides in these fields.
b.WORD SIZE:A memory unit stores binary information in group of bits called words.The
number of bits in each word is often refered to as the WORD SIZE of a computer.Each word is
stored in one memory register.The word size in micro and mini computers ranges from 8 to 32
bits, and large computers usually have 32 or more bits in a word.
c.CLOCK RATE:A clock is a square wave , which is used to synchronize various devices in the
microprocessor and the system.Every microprocessor system requires a clock for its
functioning.The time taken for the microprocessor and the system to execute an instruction is
called clockrate.
4.FUNCTION OF GENERAL PURPOSE AND SPECIAL PURPOSE REGISTERS:
General purpose registers are available to store any transient data required by the program.For
example, when a program is interrupted its state, ie: the value of the registers such as the
program counter, instruction register or memory address register - may be saved into the general
purpose registers, ready for recall when the program is ready to start again.In general the more
registers a CPU has available, the faster it can work.
A Special Function Register (or Special Purpose Register, or simply Special Register) is a
register within a microprocessor, which controls or mon.
TOP 10 B TECH COLLEGES IN JAIPUR 2024.pptxnikitacareer3
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NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
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Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
2. Contents
1. Structural Units in a Processor
2. Processor selection for an Embedded System
3. Memory Devices
4. Memory Selection for an Embedded System
5. Allocation of memory to Program segments &
Blocks and Memory map of a system
6. Direct Memory Access
7. Interfacing Processor
8. Memories and Input Output Devices
3. Structural Units in a Processor
Structural Unit Functions
MAR – Memory
Address Register
• holds address of byte/word to be fetched from external memory.
• processor issues the address of instruction or data to MAR
before it initiates fetch cycle.
MDR – Memory
Data Register
• holds a byte/word fetched (to be sent) from (to) an external
memory / IO address.
System Buses
1. Internal Bus
2. Address Bus
3. Data Bus
4. Control Bus
• internally connects all the structural units inside the processor
(width – 8,18, 32, 48 or 64 bits)
• external bus that carries address from MAR to memory as well
as to IO devices & other units of system.
• external bus that carries, during read/write operation, the bytes
for instruction/data from/to an address. (determined by MAR)
• external set of signals to carry control signal to
processor/memory/device
4. BIU – Bus Interface Unit • interface unit between processor’s internal units &
external buses
IR – Instruction Register • sequentially takes instruction codes (opcode) to
execution unit of processor.
ID – Instruction Decoder • decodes the instruction received at the IR & passes it to
processor CU.
CU – Control Unit • controls all the bus activities & unit functions needed for
processing.
ARS – Application Register
Set
• set of on-chip registers used during processing of
instruction of an application program or
• a register window
• a subset of registers with each subset storing static
variables of a software routine
• a register file associated to a unit (ALU/FPLU)
ALU – Arithmetic Logic Unit • unit to execute arithmetic/logical instruction according to
current instruction present at IR.
PC – Program Counter • generates an instruction cycle by sending the address
defined by it to memory through MAR
• auto increments as the instructions are fetched regularly
& sequentially
• called as instruction pointer in 80x86 processors
5. SP – Stack Pointer • pointer for an address which corresponds to a stack top in
memory.
IQ – Instruction
Queue
• queue of instructions so that IR does nit have to wait for next
instruction
PFCU – Pre-fetch
Control Unit
• unit that controls the fetching of data into I- & D- caches in
advance from memory units.
• improve performance by fetching instructions and data in
advance for processing.
I- Cache – Instruction
Cache
• sequentially stores (like instruction queue) instructions in FIFO
mode.
• lets the processor execute instructions at greater speed using
PFCU.
D- Cache –
Data Cache
• stores pre-fetch data from external memory.
• stores both key and value together at a location.
• also stores write-through data when configured.
BT- Cache – Branch
Target Cache
• facilitate ready availability of the next instruction-set when a
branch instruction like JUMP/LOOP/CALL is encountered.
MMU – Memory
Management Unit
• manages the memories such that the instructions and date are
readily available for processing.
SRS – System
Register Set
• set of registers used while processing the instructions of the
supervisory system program.
6. FLPU – Floating Point
Processing Set
• separate unit from ALU for floating point processing
which is essential in processing mathematical function
fast in a microprocessor/DSP
FRS – Floating point Register
Set
• register set dedicated for storing floating point
numbers in a standard format and used by FLPU for its
data & stack.
MAC – Multiply and
Accumulate unit
• units for multiplying coefficients of a series and
accumulating these during computations.
AOU – Atomic Operation
Unit
• it lets a user/compiler instructions when broken into
a number of processor instructions called atomic
operations, finish before an interrupt of a process
occurs.
• it prevents problems from arising out of shared data
between various routines and tasks.
7. Organisation of various structural units of processor
Units shown with dashed boundary are present in the high performance processors only
8. Features in most processors
1. Instruction CycleTime:
◦ It’s the time taken by a processor to execute a simple instruction ( ˜1µs
for 8051- ˜1.6ns for MPC604 )
◦ System designer uses as an indicator to match the processor speed with
application
2. Internal BusWidth:
◦ ALU gets inputs through internal buses
◦ 32 bit bus to facilitate the availability of arithmetic operations on 32-bit
operands in a single cycle
◦ 32-bit bus – a necessity for signal processing and control system instructions
3. Program-Counter (PC) bits & Reset value:
◦ Number of PC bits decides maximum possible size of physical memory that
can be accessed by the processor
◦ Reset value tells the designer the initial program address from where the
program runs on a system reset/power up
9. 4. Stack-Pointer bits & initial reset value
◦ SP values must point to addresses of the words stored at
stack
◦ Software designer defines an initial reset value & sets the
beginning SP accordingly
5. Interrupt Controller
◦ To program the service routine priorities and to allocate
vector addresses
6. Direct Memory Access (DMA) controller with
multiple channels
◦ More number of I/O devices needs to access a multi byte data
set faster, DMA is useful.
Features in most processors
10. PROCESSOR SELECTION
Processor specific feature:
1. Should operate at higher clock speed for processing more
instructions per second.
2. High computing performance when there exist
◦ (a) Pipeline(s) and superscalar architectures,
◦ (b) pre-fetch cache unit, caches, and register-files and MMU and
(c) RISC architecture.
3. Register-windows provides fast context switching in a
multitasking system.
4. Power-efficient embedded system requires a processor
that has auto-shut down feature for its units and
programmability for the disabling use of caches when the
processing need for a function or instruction set is not
constrained by limit or execution time. Uses Stop, Sleep
and Wait instructions, also require special cache design.
11. Processor specific feature:
5. Burst mode accesses external memories fast, reads
fast and writes fast.
6. Atomic operation unit provides hardware solution to
shared data problem when designing embedded
software, else special programming skill and efforts
are to be made when sharing the variables among the
multiple tasks.
7. Big-endian (MSB to lowest address) or Little-endian
(LSB to lowest address)
8. Energy efficient
12. Case Studies:
Case-1
◦ Systems in which processor instruction cycle time
is ˜1µs and on-chip devices & memory can suffice.
◦ Examples:Automatic chocolate vending machine,
robots, data acquisition systems
Case-2
◦ Systems in which processor instruction cycle
time is ˜10 to 40ns and on-chip devices &
memory do not suffice and medium processor
performance required.
◦ Examples: 2Mbps router, image processing, voice data
acquisition, voice compression
13. Case Studies:
Case-3
◦ Systems in which instruction cycle time is 5 to 10ns
required and high MIPS/MFLOPS performance needed.
◦ Examples: Multiport 100Mbps network transceiver, fast
100Mbps switches, router
Case-4
◦ Systems in which instruction cycle time of even1ns
does not suffice and multi-processor system is required
along with use of floating point & MAC unit.
◦ Examples:Voice processing,Video processing, Real-time
audio/video processing
14. MEMORY DEVICES
A simple credit-debit transaction card may
require just 2kB of memory.
◦ On other hand, smart card for secure transactions
(cryptographic functions) require 32kB of memory.
A memory- a data byte, or a word, or a double
word, or a quad word may be accessed from
all addressable locations with a similar process
and there is would be equal access time for
a read or for a write operation.
15. ROM : Uses, Forms &Variants
Non-Volatility is an important asset useful to
embed codes & data in a system.
ROM embeds software/application logic circuit in
either forms – Masked ROM, PROM &
EPROM.
During runtime programming EEPROM/Flash
memory is used.
16. Masked ROM
One time masking charge – very high
Therefore, system manufacturer will
place order & manufacturing foundry will
accept the order for a minimum of 1000
pieces.
ROM is a cost effective solution to a bulk
user.
17. EPROM, EEPROM and OTP ROM
EPROM:
◦ It is an ultraviolet ray erasable & device
programmable.
◦ Erasing means restoring 1 at each bit.
EEPROM:
◦ Electrically Erasable and Programmable Read Only
Memory
Flash Memory:
◦ Form of EEPROM, in which sector of bytes can be
erased in a flash.
PROM:
◦ Once written is not erasable.
◦ OTP (One Time device Programmer)
18. RAM – Random Access Memory
A system designer considers RAM devices of EIGHT
forms.
1. SRAM – Static RAM,
2. DRAM – Dynamic RAM,
3. NVRAM – NonVolatile RAM,
4. EDORAM – Extended Data Output RAM,
5. SDRAM – Synchronous DRAM,
6. RDRAM – Rambus DRAM,
7. Parameterized distributed RAM and
8. Parameterized Block RAM.
USES:
Stores variables during a program run & stores stack.
Stores input & output buffers.
◦ Eg: Speech & Image
19. 1. SRAM: commonly used for designing caches &
in embedded systems and microcontrollers.
2. DRAM: mostly used in high performance
computers / high memory density systems.
3. EDORAM: used for system having buses with
clock rates up to 100MHz.
4. SDRAM: synchronizes read operations &
keeps next word ready, used for processor
speed of 1GHz.
5. RDRAM: accesses in burst (four successive
words in a single fetch), thus performance
1GHz speed.
20. 6. Parameterized distributed RAM:
distributes in various system sub-units -
IO buffers & transceiver sub-units.
Distribution buffering of memory &
facilitates faster inputs from IO devices.
7. Parameterized Block RAM: used when
specific block of RAM is dedicated to sub-
unit (eg: MAC unit), used when access by
the system / IO / Internal bus is slow
compared to processing speed of sub-unit.
21. Summary of Memory
Masked ROM/EPROM/Flash stores embedded software
(ROM image). Masked ROM is for bulk manufacturing.
EPROM / EEPROM is used for testing & design stages.
EEPROM is used to store the results during program
runtime (erased byte-by-byte and written during
system run).
Flash is useful when a processed image /voice /data
/system configuration has to be stored.
RAM is mostly used in SRAM form
22. Memory Selection for an
Embedded System
Once Software designer’s coding is over and the
ROM image file is ready, a hardware designer is faced
with the questions, of what type of memory and what
size of each should be used.
CASE STUDIES:
1. Automatic chocolate vending machine or real time
robotic control system.
2. Data Acquisition Systems
3. Multi-pot network transceivers, Fast switches, Routers,
or Multi-channel Fast Encryption and decryption System
4. Voice processor or video processing or Mobile Phone
system
5. Digital Camera orVideo recorder system.
23. Allocation of MemoryTo
Program Segments and Blocks
Functions, Processes, Data and Stacks at theVarious
Segments of Memory:
◦ Program routines & processes can have different
segments.
◦ A pointer address, points to the start of memory block
storing a segment and an offset value is used to retrieve
for a memory address within that segment.
Segment wise memory allocation in four segments:
Code, Data, Stack and Extra
(for examples, image, String)
24. Segments and Paging at the Memory
A segment can have partitions of fixed
sizes called PAGES.
◦ Figure shows different segment types required
by software designer.
Each Segment has a starting and
ending memory address.
Each Segment has a pointer and
an offset address.
Using offset, code / data is
retrieved from a segment
25. Different Data Structures/Sets at
Various Memory Blocks
1) Stacks –
• allotted memory
block, from which
data is read (LIFO)
• Return addresses on
the nested calls,
• Sets of LIFO (Last In
First Out)
retrievable data,
• Saved Contexts of
the tasks as the
stacks
26. 2) Arrays – One dimensional or multidimensional
data can be retrieved from any element
address.
3) Queues – Sets of FIFO (First In First Out)
retrievable data;Two pointer (Front/Head & Back/Tail)
Circular Queue (Example- a Printer Buffer);
bounded memory block, on exceeding limit reset to start.
PIPE / Block Queue (Example- a network stack)
common memory block allotted for a queue with source &
destination.
For Circular Queue, when back attempts
To exceed end, back becomes equal to start.
27. 4) Table – two dimensional array (matrix)
three pointers – table base, column index, destination index pointer
5) HashTable – collection of pairs of key &
corresponding value.
data set allocated with a memory block - Look-up-table
6) List – a data structure with number of memory
blocks, one for each element.
each list-element stores pointer to next element
last element points to NULL
A list is for non-consecutively located objects
at the memory.
30. The Memory Maps
Memory areas needed in the case of Princeton
and Harvard architecture are different and as
shown
◦ Vectors and pointers, variables, program segments
and memory blocks for data and stacks have different
addresses in the program – PRINCETON memory
architecture.
◦ Program segments and memory blocks for data and
stacks have separate sets of addresses in Harvard
architecture. Control signals and read-write
instructions are also separate.
Designer must remember that if main memory is
of Harvard architecture, program memory map
will be separate.
31. Memory Map
Map to show the program and data
allocation of the addresses to ROM, RAM,
EEPROM or Flash in the system
Fig: Memory map for an
exemplary embedded
system,
smart card needing
2 kB memory
32. Direct Memory Access
A DMA is required when a multi-byte data set or a
burst of data or a block of data is to be transferred
between the external device and system or two
systems.
A device facilitates DMA transfer with a processing
element (single purpose processor) and that device is
called DMAC (DMA Controller).
Three modes of DMA operations:
◦ Single transfer at a time and then release of the hold on
the system bus.
◦ Burst transfer at a time and then release of the hold on
the system bus.A burst may be of a few kB.
◦ Bulk transfer and then release of the hold on the system
bus after the transfer is completed.
33. DMAC - DMA Controller
Data transfer occurs efficiently between I/O
devices and system memory with the least
processor intervention using DMAC.
DMAC provide memory access to Multiple
channels
◦ Separate set of registers for programming each
channel.
◦ Separate interrupt signals in the case of a multi-
channel DMAC
Provides DMA action from system memories
and two (or more IO) devices.
34. DMA Controller with the buses &
control signals in between
Figure shows the buses and control signals between processor, Memory,
DMAC and the data transferring I/O devices.
35. DMA Controller Execution
DMA proceeds without the CPU intervening
◦ Except
(i) at the start for DMAC programming and
initializing and
(ii) at the end.
◦ Whenever a DMA request by external device is
made to the DMAC, the CPU is requested (using
interrupt signal) the DMA transfer by DMAC at
the start to initiate the DMA and at the end to
notify (using interrupt signal) the end of the
DMA by DMAC.
36. Interfacing Processor, Memories
& Input Output Devices
Interconnections for a simple bus structure has three sets
of signals – data, address and control signals.
A system-bus interfacing-design is according to the timing
diagrams of processor signals, speed and word length for
instructions and data.
Interfacing of processor, memory and IO devices using
memory system bus
37. Time division multiplexed (TDM)
address and data bits for the memories
TDM ─ Different time slots, there is a different sets
(channel) of the signals.
Address signals during one time slot and
data bus signals in another time slot.
Interfacing circuit for the demultiplexing of the buses
uses a control signal.
Control signal - Address Latch Enable (ALE) in 8051,
Address Strobe (AS) in 68HC11 and address valid
(ADV) in 80196.
ALE or AS or ADV demultiplexes the address and data
buses to the devices
38. Interfacing circuit using Latch and
decoders
ALE for latching the address
PSEN (Program Store ENable) for program
memory read using address data buses
Each chip of the memory or port that
connects the processor has a separate chip
select input from a decoder.
Decoder is a circuit, which has appropriate
signals of the address bus at the input and
control circuit signals to generate
corresponding CS (chip select) control
signals for each device (memory and ports)
39. Summary: Interfacing- circuit
Consists of latches, decoders and demultiplexers
Designed as per available control signals and
timing diagrams of the bus signals.
Circuit connects all the units, processor, memory
and the IO device through the system buses.
Also called glue circuit used as it joins the
devices and memory with the system bus and
processor
Can be designed using a GAL (generic array
logic) or FPGA