The document discusses computer organization and architecture. It defines architecture as the instruction set, registers, and addressing modes visible to programmers, while organization refers to internal design details like caching and pipelining. It describes the basic functional units of a computer including I/O, memory, arithmetic logic, and control units. It explains the fetch-execute cycle and how instructions are stored and executed from memory. Pipelining and superscalar techniques are discussed to improve processor performance.

1. COMPUTER
ORGANIZATION AND ARCHITECTURE
By: MOHAMMAD ASIM

2. Architecture vs. Organization
• Architecture:
– Also known as Instruction Set Architecture (ISA)
– Programmer visible part of a processor:
instruction set, registers, addressing modes, etc.
• Organization:
– High-level design: how many caches? how many
arithmetic and logic units? What type of
pipelining, control design, etc.
– Sometimes known as micro-architecture

3. Functional Units
Basic functional units of a computer.
I/O Processor
Output
Memory
Input
Arithmetic
and
logic
Control

4. Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in
ALU of the processor.
 Load the operands into memory – bring them
to the processor – perform operation in ALU –
store the result back to memory or retain in
the processor.
 Registers

5. Control Unit
 All computer operations are controlled by the control unit.
 The timing signals that govern the I/O transfers are also
generated by the control unit.
 Operations of a computer:
 Accept information in the form of programs and data through an input
unit and store it in the memory
 Fetch the information stored in the memory, under program control, into
an ALU, where the information is processed
 Output the processed information through an output unit

6. INSTRUCTIONS
Instruction codes
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation (a sequence of
micro-operation)
• The instructions of a program, along with any needed data are
stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into
the sequence of micro-operations necessary to implement it
• Ability to store and execute  differs from one to other

7. INSTRUCTION FORMAT
Instruction codes
• A computer instruction is often divided into two parts
– An op-code (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation
15 14 0
I Op-code Address
Instruction Format
12 11
Addressing
mode

8. PC
Register
Bank
Data Memory
Address
Instructions Address
Data
Instruction
Memory
A
L
U
Data
Register #
Register #
Register #
The processor : Data Path and Control

9. PROCESSOR REGISTERS
Instruction codes
• A processor has many registers to hold instructions, addresses, data, etc….
• The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction to get
• Control unit stores instruction after reading it from memory is called as
Instruction Register (IR) .
• In a direct or indirect addressing, the processor needs to keep track of what
locations in memory it is addressing: The Address Register (AR) [Same as
MAR] is used for this
• When an operand is found, using either direct or indirect addressing, it is
placed in the Data Register (DR) [same as MDR]. The processor then uses this
value as data for its operation
• The Basic Computer has a Accumulator (AC) for manipulation of data .

10. PROCESSOR REGISTERS
Instruction codes
• The significance of a general purpose register (GPR) is that it can be referred
to, in instructions
– e.g. load AC with the contents of a specific memory location; store the contents of AC into a
specified memory location
• Often a processor will need a scratch register to store intermediate results or
other temporary data; in the Basic Computer this is the Temporary Register
(TR)
• The Basic Computer uses a very simple model of input/output (I/O)
operations
– Input devices are considered to send characters of data to the processor
– The processor can send characters of data to output devices
• The Input Register (INPR) holds character from an input device.
• The Output Register (OUTR) holds character to be send to an output device.

11. Stored Program Concept
• CPU consists of ALU & CU
• Main Memory
• INPUT & OUTPUT System
• Program + Data  on same memory
• But each memory location must be
addressed independently.
• Single path between main memory &
control unit, so control signal can’t
exchange simultaneously.
Von-neuman Architecture

12. Basic Operational Concepts
A Typical Instruction
 ADD LOCA, R0
 Add the operand at memory location LOCA to the operand
in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the processor –
the operand at LOCA is fetched and added to the contents
of R0 – the resulting sum is stored in register R0.

13. Memory Access & ALU
Operation
Example:-
 Load LOCA, R1
 Add R1, R0
 Whose contents will be overwritten?

14. Connection Between the Processor and the Memory
1. Instruction register (IR)
2. Program counter (PC)
3. General-purpose register (R0 – Rn-1)
4. Memory address register (MAR)
5. Memory data register (MDR)
• Programs reside in the memory through
input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded
into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
• Get operands for ALU
General-purpose register
Memory (address to MAR – Read –
MDR to ALU)
• Perform operation in ALU
• Store the result back
To general-purpose register
To memory (address to MAR, result to
MDR – Write)
• During the execution, PC is incremented
to the next instruction.
Typical Operating Steps

15. Interrupt
• Normal execution of programs may be preempted if
some device requires urgent servicing.
• The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
• Interrupt-service routine
• Current system information backup and restore (PC,
general-purpose registers, control information, specific
information)

16. Bus Structures
• There are many ways to connect different parts inside a
computer together.
• A group of lines that serves as a connecting path for several
devices is called a bus.
• Address/data/control

17. Performance
• The most important measure of a computer is how quickly it can execute
programs.
• Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
• Processor time to execute a program depends on the hardware involved
in the execution of individual machine instructions.
Main
memory Processor
Bus
Cache
memory

18. Processor Clock
• Clock :- Processor circuits are controlled by timing signal
• Clock cycle:- A regular time interval (Ex. Cycle length p)
• Clock rate (R):- Inverse of clock cycle { R = ⅟p } which is
measured in cycles per second.
• The execution of each instruction is divided into several
steps, each of which completes in one clock cycle.
• Hertz (Hz) – cycles per second

19. Basic Performance Equation
• T – processor time required to execute a program that has
been prepared in high-level language
• N – number of actual machine language instructions needed
to complete the execution (note: loop)
• S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
• R – clock rate
 Note:- These are not independent to each other
T 
NS
R
How to improve T ?
Reduce N & S
Increase R

20. Pipeline & Superscalar Operation
• If source program complied in fewer machine instruction
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)
• Goal – reduce N
• Instructions are not necessarily executed one after another.
• The value of S doesn’t have to be the number of clock cycles to execute one
instruction.
• Pipelining – overlapping the execution of successive instructions.
• Superscalar operation – multiple instruction pipelines are implemented in
the processor.
• Goal – reduce S
• Increase clock rate
 Improve the integrated-circuit (IC) technology to make the circuits faster
 Reduce the amount of processing done in one basic step
• Increases in R that are entirely caused by improvements in IC technology
affect all aspects of the processor’s operation equally except the time to
access the main memory.

21. CISC vs. RISC
Organizations
Main Memory Main Memory
Microprogrammed
Control Unit
Microprogrammed
Control Memory
Cache
Hardwared
Control Unit
Instruction
Cache
Data
Cache
(a) CISC Organization (b) RISC Organization

22. Compiler
• A compiler translates a high-level language program into a
sequence of machine instructions.
• To reduce N, we need a suitable machine instruction set
and a compiler that makes good use of it.
• Goal – reduce N×S
• A compiler may not be designed for a specific processor;
however, a high-quality compiler is usually designed for,
and with, a specific processor.

23. Multiprocessors & Multicomputer
• Multiprocessor
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-
memory multiprocessor
 Cost – processors, memory units, complex interconnection
networks
• Multicomputer
 Each computer only have access to its own memory
 Exchange message via a communication network – message-
passing multicomputer

24. UMA vs. NUMA Computers
Cache
P1
Cache
P2
Cache
Pn
Cache
P1
Cache
P2
Cache
Pn
Network
Main
Memory
Main
Memory
Main
Memory
Main
Memory
Bus
(a) UMA Model (b) NUMA Model

25. Memory Location, Addresses,&
Operation
• Memory consists of
many millions of
storage cells, each
of which can store 1
bit data as 0/1.
• Data is usually
accessed
groups
in n-bit
as Word
( Where n is called
word length ).
first word
second word
Memory words.
nbits
last word
i th word
•
•
•
•
•
•

26. Memory Location, Addresses &
Operation
• 32-bit word length example
(b) Four characters
ASCII
character
ASCII
character
ASCII
character
ASCII
character
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers
(a) A signed integer
32 bits
8 bits 8 bits 8 bits 8 bits
•
b31 b30
•
•
b1 b0

27. Memory Location, Addresses &
Operation
• To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location are
needed.
• A k-bit address memory has 2k memory locations,
namely 0 to 2k - 1,  called as memory space.
• Example:-
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240

28. Memory Location, Addresses &
Operation
• It is impractical to assign distinct addresses to individual bit
locations in the memory.
• The most practical assignment is to have successive
addresses refer to successive byte locations in the memory
called as  byte-addressable memory.
• Byte locations have addresses 0, 1, 2, …
• If word length is 32 bits, they successive words are located
at addresses 0, 4, 8,…, with each word consists of four
bytes.

29. Big-Endian & Little-Endian
Assignments

30. Big-Endian & Little-Endian
Assignments
0 1 2 3
4 5 6 7
•
•
•
2
k
- 4 2
k
- 3
k
2 - 2 2
k
- 1
k
2 - 4
k
2 - 4
0
0
4
3 2 1 0
7 6 5 4
•
•
•
k
2 - 1 2
k
- 2 2
k
- 3 2
k
- 4
Byte address
Byte address
(a) Big-endian assignment
Byte and word addressing.
(b) Little-endian assignment
4
Word
address
Big-Endian:- Lower byte addresses are used for the most significant bytes of the word
Little-Endian: - (opposite ordering ) Lower byte addresses are used for less significant bytes of word

31. Intel MultiCore Architecture
• Improving execution rate of a single-thread is still
considered important:
– Uses out-of-order execution and speculation.
• MultiCore architecture:
– Can reduce power consumption.
– (14 pipeline stages) is closer to the Pentium M (12 stages)
than the P4 (30 stages).
• Many transistors are invested in large branch
predictors:
– To reduce wasted work (power).

32. Intel’s Dual Core Architectures
• The Pentium D is simply two Pentium 4 cpus:
– Inefficiently paired together to run as dual core.
• Core Duo is Intel's first generation dual core processor based
upon the Pentium M (a Pentium III-4 hybrid):
– Made mostly for laptops and is much more efficient than Pentium
D.
• Core 2 Duo is Intel's second generation (hence, Core 2)
processor:
– Made for desktops and laptops designed to be fast while not
consuming nearly as much power as previous CPUs.
• Intel has now dropped the Pentium name in favor of the Core
architecture.

33. Intel Core Processor

34. Intel Core 2 Duo
• Code named
“conroe”
• Homogeneous cores
• Bus based chip
interconnect.
• Shared on-die Cache
ClM
assie
c O
m
OO
o:rR
y
e.
servation Stations,
Issue ports, Schedulers…etc
Large, shared set associative,
prefetch, etc.
Source: Intel Corp.

35. Core 2 Duo Microarchitecture

36. Why Sharing On-Die L2?
• What happens when L2 is too large?

37. I/O Hub
PCI-E
Bridge
PCI-E
Bridge
PCI-E
Bridge
PCI-E
Bridge
PCI-E
Bridge
I/O Hub
XMB
XMB XMB XMB
Memory
Controller
Hub
Dual-Core Dual-Core Dual-Core
Dual-Core
Dual-
Core
Dual-
Core
Dual-
Core
Dual-
Core
Xeon Vs. Opteron