It is introduction to computer organisation

1. COMPUTER ORGANIZATION AND
ARCHITECTURE
21CSE34
MODULE-1
Introduction

2. Introduction to the Course
• To become layman to computer professional
• Here while studying you should be knowing what going on
at back end like:
• Where information or data is stored
• Where these data going to be processed and how
• Where it should be held temporally
• How does it going to be displayed
• How the efficiency of computer can be improved
• CO is formal study of computers
• What is basic function of computer?
• Ans: Computation
• i,e: simple calculator, remote, mobile, laptops etc…….

3. • Computation means what?
Ans: to do some operation or to execute something
• Computer architecture:
Architecture is nothing but structuring of computer
• Computer organization :
Organizing a given architecture such that to get desired
output
E.g: building a house
• CA deals with functional behaviour of computer system
Design implementation for various part of computer
designing is attribute of architecture
• CO deals with structural relationship
utilization is attribute of organization

5. Parts of computer

7. History of COA
• Charles Babbage 
Analytical Engines( Father of computer)
• Ado Lavelace 
First Program Developer
• Alan Turing 
introduce Computability( what computer Can do and what Can’t)
• Johan Van Neumann
responsible for advancement in computer architecture

8. Computer architecture
Neumann Architecture Harvard Architecture

9. Instruction processing type
• 1. SISD: single instruction stream, single data stream
• 2. SIMD: single instruction stream multiple data stream

10. • 3. MISD: multiple instruction stream single data stream
• 4. MIMD: multiple instruction stream multiple data stream

11. Syllabus
• Module-1: Basic Structure of Computers: Basic Operational
Concepts, Bus Structures, Performance– Processor Clock,
Basic Performance Equation, Clock Rate, Performance
Measurement. Machine Instructions and Programs:
Memory Location and Addresses, Memory Operations,
Instructions and Instruction Sequencing, Addressing Modes,
• Module-2: Input/output Organization: Accessing I/O
Devices, Interrupts – Interrupt Hardware, Direct Memory
Access, Buses, Interface Circuits.
• Module–3: Memory System: Basic Concepts, Semiconductor
RAM Memories, Read Only Memories, Speed, Size, and
Cost, Cache Memories – Mapping Functions, Virtual
Memories

12. Syllabus Continued
• Module-4: Arithmetic:Numbers, Arithmetic Operations and Characters,
Addition and Subtraction of Signed Numbers, Design of Fast Adders,
Multiplication of Positive Numbers,
Basic processing Unit: Fundamental concepts, Execution of a complete
instruction, Hardwired control, Microprogrammed Control
• Module-5: Pipeline and Vector Processing: Parallel processing,
Pipelining, Arthmetic Pipeline, Instruction Pipeline, Vector Processing,
Array Processing
Text Book
• Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, 5th Edition,
Tata McGraw Hill, 2002. (Listed topics only from Chapters 1, 2, 4, 5, 6, )
• M. Morrio Mano, Computer Organization & Architecture, 9th edition, Pearson(
Chapter7 and 9)

13. Objectives
Explain the basic sub systems of a computer, their organization,
structure and operation.
• Illustrate the concept of programs as sequences of machine
instructions.
• Demonstrate different ways of communicating with I/O
devices and standard I/O interfaces.
• Describe different types of memory devices and their function
• Explain the arithmetic and logical operation with different data
types.
• Illustrate organization of a simple processor, pipelined
processor and other computing systems.

14. Outcome
• Explain the basic organization of a computer system.
• Understanding machine instruction and programs
• Demonstrate functioning of different sub systems, such as
processor, Input/output
• Demonstrate the function of different types of memory
devices
• Apply different data types simple arithmetic and logical
units.
• Analyse the function of basic processing unit, parallel
processing and pipelining.

15. Assessment details(CIE & SEE)
• Min passing should be 40% out of 100
• CIE 50%
• Min passing should be 40%(20 m)
• 20 Marks for internal 3 internal average
• 10 marks for 2 assignment
• 20 marks for GD/ Seminar/ Quiz etc
• SEE 50%
• Min passing should be 35%
• 10 question each of 20 marks 2 question from each modules
• Should ans one complete question

16. Basic Operational Concepts

17. Review
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of a list of
instructions is stored in the memory.
• Individual instructions are brought from the memory into the
processor, which executes the specified operations.
• Data to be used as operands are also stored in the
memory.
• An Instruction consists of 2 parts,
1) Operation code (Opcode)
2) 2)Operands

18. A Typical Instruction
• Add LOCA, R0
• Eg: Add a + 5
• Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
-Instruction is fetched from the memory into the processor
– the operand at LOCA is fetched and added to the
contents of R0
– the resulting sum is stored in register R0.

19. Separate Memory Access and ALU Operation
Load LOCA, R1
Add LOCA, R0
Add R1, R0
Which register content is preserved? Which is overwritten?

20. Connection Between the Processor and the Memory

21. Registers
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)

22. • IR it holds instructions that currently being executed
• PC Contain the memory address of the next instruction to be
fetched( PC updated during execution)
• MARit holds the address of memory location to which the data is to
be store or to be read
• MDR It holds the data to be written into memory or read from
memory
• Register R0…..R1 general purpose register, hold the data fetched
from memory

23. Typical Operating Steps
• Programs reside in the memory through input
devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded
into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction

24. Typical Operating Steps (Cont’)
• Get operands for ALU
General-purpose register
Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to
the next instruction

25. Problem :
List the steps needed to execute the machine instruction:
Add R0, LOCA
in terms of transfers between the components of processor and some simple control
commands. Assume that the address of the memory-location containing this
instruction is initially in register PC.
Solution:
• Transfer the contents of register PC to register MAR.
• Issue a Read command to memory.
• And, then wait until it has transferred the requested word into register MDR.
• Transfer the instruction from MDR into IR and decode it.
• Transfer the address LOCA from IR to MAR.
• Issue a Read command and wait until MDR is loaded.
• Transfer contents of MDR to the ALU.
• Transfer contents of R0 to the ALU.
• Perform addition of the two operands in the ALU and transfer result into R0.
• Transfer contents of PC to ALU.
• Add 1 to operand in ALU and transfer incremented address to PC.

26. Interrupt
• Normal execution of programs may be preempted if some
device requires urgent servicing.
• The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
• Interrupt may be fron I/O Device, or Processor Service
• Interrupt-service routine

27. Bus Structures
• There are many ways to connect different parts inside a
computer together.
• A group of lines that serves as a connecting path for several
devices is called a bus.
• Address/data/control line

28. Bus Structure
• Single-bus

29. Speed Issue
• Only 2 units can actively use Bus at single time, not all
• Single Bus is low cost & Flexible for attaching to Devices
• System may have multiple buses to achieve more speed
• Different devices have different transfer/operate speed.
• If the speed of bus is bounded by the slowest device connected to it,
the efficiency will be very low.
• How to solve this?
• A common approach – use buffers.
Eg: Printing Characters

30. Performance

31. Performance
• The most important measure of a computer is how
quickly it can execute programs.
• The speed at which computer execute depends on
Three factors affect performance:
 Hardware design
 Instruction set
 Compiler

32. • Time taken by the program to execute the program is called Processor
time
• Processor time Depends on H/W involved in execution of each
machine instruction
• Hard ware comprises the processor & memory that are connected
through Bus( takes more time to execute)
• The processor and a relatively small cache memory can be fabricated
on a single integrated circuit chip

33. Performance
• Processor clock
• Basic Performance Equation
• Clock rate
• Performance measurement
• Speed
• Cost
• Memory management

34. Performance
• Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.
Main
memory Processor
Bus
Cache
memory
Figure 1.5. The processor cache.

35. Processor Clock
• Clock, clock cycle, and clock rate
• Processor timing are controlled by signal called Clock
• Clock define regular time interval Called Clock Cycle
• The execution of each instruction is divided into several
steps, each of which completes in one clock cycle.
• Inverse of Clock Cycle is measured as clock Rate
• If P is length of one clock cycle then R=1/P is clock rate
Eg: P=5 R=1/5 0.2
• Hertz – cycles per second

36. Basic Performance Equation
• T – processor time required to execute a program that has been prepared
in high-level language
• N – number of actual machine language instructions needed to
complete the execution (note: loop)
• S – average number of basic steps needed to execute one machine
instruction. Each step completes in one clock cycle
• R – clock rate
• Note: these are not independent to each other
T 
NS
R
How to improve T?
By reducing N &S value, increasing R

37. Problem
A program contains 1000 instructions. Out of that 25% instructions
requires 4 clock cycles,40% instructions requires 5 clock cycles and
remaining require 3 clock cycles for execution. Find the total time
required to execute the program running in a 1 GHz machine.
Solution:
N = 1000
25% of N= 250 instructions require 4 clock cycles.
40% of N =400 instructions require 5 clock cycles.
35% of N=350 instructions require 3 clock cycles.
T = (N*S)/R
= (250*4+400*5+350*3)/1X109
=(1000+2000+1050)/1*109 = 4.05 μs.

38. Clock Rate
• Increase clock rate
 Improve the integrated-circuit (IC) technology to make the
circuits faster
 Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
• Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.

39. Performance Measurement
n 1
SPEC rating  ( SPECi ) n
i1
• T is difficult to compute.
• Measure computer performance using benchmark programs.
• System Performance Evaluation Corporation (SPEC) selects and publishes
representative application programs for different application domains,
together with test results for many commercially available computers.
• Compile and run (no simulation)
• Reference computer
SPEC rating 
Running time on the referencecomputer
Running time on the computer under test

40. Compiler
• A compiler translates a high-level language program into
a sequence of machine instructions.
• To reduce N, we need a suitable machine instruction set
and a compiler that makes good use of it.
• Goal – reduce N×S
• A compiler may not be designed for a specific processor;
however, a high-quality compiler is usually designed for,
and with, a specific processor.

41. CISC and RISC
• Tradeoff between N and S
• A key consideration is the use of pipelining
 S is close to 1 even though the number of basic steps per
instruction may be considerably larger
 It is much easier to implement efficient pipelining in processor
with simple instruction sets
• Reduced Instruction Set Computers (RISC)
• Complex Instruction Set Computers (CISC)

42. Multiprocessors and Multicomputers
• Multiprocessor computer
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-memory
multiprocessor
 Cost – processors, memory units, complex interconnection networks
• Multicomputers
 Each computer only have access to its own memory
 Exchange message via a communication network – message-passing
multicomputers

43. Pipeline and Superscalar Operation
• Instructions are not necessarily executed one after
another.
• The value of S doesn’t have to be the number of clock
cycles to execute one instruction.
• Pipelining – overlapping the execution of successive
instructions.
• Add R1, R2, R3
• Superscalar operation – multiple instruction pipelines are
implemented in the processor.
• Goal – reduce S (could become <1!)

44. Chapter 2. Machine
Instructions and
Programs

45. Memory Locations,
Addresses, and
Operations

46. Memory Location, Addresses, and Operation
• To retrieve information from memory, either for one
word or one byte, addresses for each location are
needed.
• A k-bit address memory has 2k memory locations, namely
0 – 2k-1, called memory space.
24-bit memory: 224 = 16,777,216 = 16M (1M=220)
32-bit memory: 232 = 4G (1G=230)
1K(kilo)=210
1T(tera)=240

47. Memory Location, Addresses, and Operation
• It is impractical to assign distinct addresses to
individual bit locations in the memory.
• The most practical assignment is to have
successive addresses refer to successive byte
locations in the memory – byte-addressable
memory.
• Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, the successive words
are located at addresses 0, 4, 8,…

48. Byte addressability
• Memory consists of many
millions of storage cells,
each of which can store 1
bit.
• Data is usually accessed
in n-bit groups. n is
called word length.
nbits
i th word
•
•
•
•
•
•
0 first word
1second word
2n -1 last word
Figure 2.5. Memory words.

49. Memory Location, Addresses, and Operation
• 32-bit word length example
(b) Four characters
(a) A signed integer
Sign bit:
ASCII
character
ASCII
character
ASCII
character
ASCII
character
32 bits
8 bits 8 bits 8 bits 8 bits
1 for positive numbers
2 for negative numbers
b31=
b31=
•
b31 b30
•
•
b1 b0
MSB

50. k
2 - 4
k
2 - 4
0
0
4
Byte address Byte address
4
address
3 2 1 0
7 6 5 4
•
•
•
k
2 - 1
k
2 - 2
k
2 - 3
k
2 - 4
0 1 2 3
4 5 6 7
•
•
•
k
2 - 4
k
2 - 3
k
2 - 2
k
2 - 1
(a) Big-endian assignment (b) Little-endian assignment
Figure 2.7. Byte and word addressing.
Big-Endian: lower byte addresses are used for the most significant
bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for
the less significant bytes of the word
Word

51. Memory Location, Addresses, and Operation
• Address ordering of bytes
• Word alignment
– Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….
• Access numbers, characters, and character
strings

52. 3 2 1 0
5 4 Unaligned Words

53. Address 1000 1001 1002 1003
Value 12 34 56 78
Consider a 32-bit integer (in hex): 0x12345678 which consists of 4
bytes: 12, 34, 56, and78.
34 56 78
Hexa -0x 12
Binary -
• Hence this integer will occupy 4 bytes in memory.
• Assume, we store it at memory address starting1000.
• On little-endian, memory will look like
• On big-endian, memory will look like
Address 1000 1001 1002 1003
Value 78 56 34 12
Little-Endian
Big-Endian

54. Memory Operation
• Load (Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
Processor Memory
D D
add add
read

55. • Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
write
processor
memory

56. Instruction and
Instruction Sequencing

57. “Must-Perform” Operations
• Data transfers between the memory and the
processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

58. Register Transfer Notation
• Data transfer can be represented by using some
notation
LOC,VAR2, PLACE, MEMmemory location
A,…R0,…….Rn,... processor registers
DATAIN,OUTSTATUS,DATAOUT  I/O registers
• Contents of a location are denoted by placing square
brackets around the name of the location
Eg: 1. R1←[LOC]
Eg: 2 . R3 ← [R1]+[ R2]
Register Transfer Notation (RTN)
• Data transfer from right to left

59. Assembly Language Notation
• Another type of notation used to represent
instruction
• Register name memory location are same as that of
RTN
• Represent machine instructions and programs.
Move LOC, R1 = R1←[LOC]
Add R1, R2, R3 = R3 ←[R1]+[R2]
Operation Source Destination
• Most of the computer follow this left to right
assignment
• Divided in to 3 fields

60. Basic Instruction Type
• Each instruction contain specific field of
information
• Operation code(opcode)
• Source/Destination operand
• Source operand address
• Destination operand address
• Next instruction address(eg: jump branch etc..)

61. CPU Organization
• Single Accumulator
– Result usually goes to the Accumulator
– Accumulator has to be saved to memory quite often
• General Register
– Registers hold operands thus reduce memory traffic
– Register bookkeeping
• Stack
– Operands and result are always in the stack

62. Instruction Formats
• Three-Address Instructions
• If n –bit is required to specify one memory address then 3n-
bit required to specify 3 address instruction
Operation Source1, Source2, Destination
ADD A, B, C
Cannot fit complete instruction in one word for 32bit
computer
• Two-Address Instructions
Operation Source, Destination
ADD A,B i.e., [B] [A]+[B] B is both Source and Destination
Opcode Operand(s) or Address(es)

63. Move B,C C [B]
Add A,C C [A]+[C]
Together can
perform
Add A,B,C
TwoAddress instruction containing two memory locations
also cannot fit into one word. Therefore a processor
register called accumulator can be used in One Address
instructions.
One-Address Instructions
Add A, B, C can be accomplished using below set
Load A
Add B
Store C
AC [A]
AC [AC] + [B]
C [AC]

64. • Zero Address instruction
• Here location of all operands are defined implicitly
• Such instruction are found in machine called a
pushdown stack
• Speed of instruction execution is mainly depend
on how much memory access it requires for the
execution
• So execution time for 3 address is more.

65. Generalization of Load, Store and Add instructions for a
single accumulator processor, where register Ri
performs the function of accumulator.
Load A,Ri
Store Ri, A
Add A, Ri
If a processor has several general processor registers ,
instructions can involve operands only in registers.
Add
Add
Ri, Rj
Ri, Rj, Rk

66. Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Three-Address
1. ADD A, B, R1
2. ADD C, D, R2
3. MUL R1, R2, X
; R1 ← M[A] + M[B]
; R2 ← M[C] + M[D]
; M[X] ← [R1]  [R2]

67. Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV A, R1
2. ADD B, R1
3. MOV C, R2
4. ADD D, R2
5. MUL R2, R1
6. MOV R1, X
; R1 ← M[A]
; R1 ← [R1] + M[B]
; R2 ← M[C]
; R2 ← [R2] + M[D]
; R1 ← [R1]  [R2]
; M[X] ← [R1]

68. Instruction Formats
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A
2. ADD B
3. STORE T
4. LOAD C
5. ADD D
6. MUL T
7. STORE X
; AC ← M[A]
; AC ← [AC] + M[B]
; M[T] ← [AC]
; AC ← M[C]
; AC ← [AC] + M[D]
; AC ← [AC]  M[T]
; M[X] ← [AC]

69. Instruction Formats
• PUSH A TOS  A
• PUSH B TOS B
• ADD TOS(A+B)
• PUSH C TOS C
• PUSH D TOSD
• ADD TOS(C+D)
• MUL TOS (C+D) * (A+B)
• POP X M[X] TOS
• Eg2: X=A*B+C*D
Zero address instruction

70. Using Registers
• Registers are faster.
• Potential speedup.
• Minimize the frequency with which data is moved
back and forth between the memory and processor
registers.

71. Instruction Execution and Straight-Line Sequencing
• Every processor has some basic type of instruction
• Data transfer instruction
• Arithmetic instruction
• Logical instruction
• Branch instruction
• To perform a task its programmer job to select n write
appropriate instruction one after the other(ISQ)
• Processor execute program with the help of PC
• During execution PC increment by on word length
• Instruction will be executed in 3 operations:
• Instruction fetching
• Opcode decoding
MOVE ,LOAD,STORE, PUSH, POP
ADD, MUL,SUB, DIV,NEG
OR,AND
JUMP, CALL, RETURN

72. • After each cycle CPU check for any valid interrupts
request
• Fetch the instruction from interrupt service rourine
• After execution continues

73. Instruction Execution and Straight-Line Sequencing
Begin execution here
Address Contents
C
B
A
the program
Data for
3-instruction
program
segment
Move A,R0
Add B,R0
Move R0,C
i
i + 4
i + 8
Figure 2.8. A program for C   + 
Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
Two-phase procedure
-Instruction fetch
-Instruction execute
 Program Counter
 Straight Line sequencing
PC
IR

74. NUMn
Figure 2.9. A straight-line program for adding n
numbers.
SUM
NUM1
NUM2
i + 4n- 4
i + 4n
i
i + 4
i + 8
Move NUM1,R0
Add NUM2,R0
Add NUM3,R0
•
•
•
Add NUMn,R0
Move R0,SUM
•
•
•
•
•
•
Branching
Add a list of n numbers
for( i=0; i<n; i++ )
sum= sum + a[i];
No of code is more
1
2
3

75. Branching
N,R1
Move
NUM1
NUM2
Figure 2.10. Using a loop to add n numbers. NUMn
Decrement R1
Program
loop
N
SUM
n
Clear R0
Determine address of
"Next" number and add
"Next" number to R0
Branch>0 LOOP
Move R0,SUM
•
•
•
•
•
•
 Branch instructions
 Will cause new value to be loaded into PC
 Branch target
 Conditional branch
N is the number
of elements in the
list
LOOP
R1 acts as a
counter of the
loop

76. Condition Codes
• The processor keeps track of information about the results of
various operations.
• These condition codes a stored in register called Status
Register( flag register).
• This is accomplished by recording the required information in
individual bits, called condition code flags.

77. Condition Codes
• Four commonly used flags are:
– 1) N (negative) set to 1 if the result is negative, otherwise cleared
to 0.
– 2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
– 3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise,
cleared to 0.
– 4) C (carry) set to 1 if a carry-out results from the operation;
otherwise cleared to 0

78. Addressing Modes

79. Addressing Modes
• The different ways in which the location of an
operand is specified in an instruction are referred to
as addressing modes.
• Immediate Mode
– The operand is given explicitly in the instruction.
MOV 200immediate, R1 i.e. R1 ← 200
i.e R0 = R0 + 200
ADD #200, R0
• Register Mode
- Operand is the content of processor register, name of register is
given in instruction
– Indicate which register holds the operand ADD R1, R2

80. Addressing Modes
• Absolute(Direct) Mode: The operand is in a memory
location; the address of this location is given explicitly in the
instruction.
this instruction uses two modes,
Absolute and Register mode.
Eg: MOV LOC, R2
Eg: A = B + 6
Mov B,R1
Add #6,R1
Mov R1, A

81. Addressing Modes
• Indirect Mode-
 The instruction does not give the operand or its address
explicitly.
 Instead it provides information from which the memory
address of the operand can be determined.
 We refer to this address as the effective address of the
operand
• The effective address of the operand is the content of a
register or memory location whose address appears in
the instruction.
– Register Indirect
– Memory Indirect
MOVE (R0) , A A memory address of R0

82. Addressing Modes
• Register Indirect
– Indicate the register that holds the number of the register
that holds the operand
MOV (R2), R1
5
R2
ADDRESS

84. Addressing Modes
• Indirect Address/ Memory Indirect
– Indicate the memory location that holds the address of the memory
location that holds the data

85. Addressing Modes

86. Addressing Modes
• The different
ways in which
the location of
an operand is
specified in an
instruction are
referred to as
addressing
modes.
Name Assem bler syn tax Addressing function
Immediate #Value Op erand = Value
Register R i EA = R i
Absolute (Direct) LOC EA = LOC
Indirect (R i ) EA = [R i ]
(LOC) EA = [LOC]
Index X(R i) EA = [R i ] + X
Base with index (R i ,R j ) EA = [R i ] + [R j ]
Base with index X(R i,R j ) EA = [R i ] + [R j ] + X
and offset
Relative X(PC) EA = [PC] + X
Autoincremen t (R i )+ EA = [R i ] ;
Incremen t R i
Autodecrement Decremen t R i ;
EA = [R i]
(R i )

87. Indexing
• Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
• Index register
• X(Ri)
– EA = X + [Ri]
• The constant X may be given either as an explicit number or
as a symbolic name representing a numerical value.

88. Indexing
• In general, the Index mode facilitates access to an
operand whose location is defined relative to a
reference point called offset
• Several variations:
• base indexing
(Ri,Rj): EA = [Ri] + [Rj]
• base and offset with
offset
X(Ri, Rj): EA = X + [Ri] + [Rj]

89. Indexing

90. Addressing Modes

91. Relative Addressing
• Relative mode – the effective address is determined by
the Index mode using the program counter in place of
the general-purpose register.
• X(PC) – note that X is a signed number
• Branch>0 LOOP
• This location is computed by specifying it as an offset
from the current value of PC.

92. Additional Modes
• Autoincrement mode – the effective address of the operand is the contents of
a register specified in the instruction. After accessing the operand, the contents
of this register are automatically incremented to point to the next item in a list.
• (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4
for 32-bit operands.
• Autodecrement mode: -(Ri) – decrement first
Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Initialization
LOOP
N,R1
#NUM1,R2
R0
(R2)+,R0
R1
LOOP
R0,SUM
Move
Move
Clear
Add
Decrement
Branch>0
Move

93. Question paper (seminar)
1. What is an addressing mode? Explain different types of addressing mode
with ex
2. Explain the basic instruction types with example
3. Show how bellow expression will be executed in one address, two address
three address in an accumulate. X=A*B+C*D
4. What is the effective address of source operand in each of the following
instruction
load 20(R1),R5 Move #3000, R1 Store R5, 30(R1,R2)
Add –(R2), R5 Subtract (R1+), R5

94. 1. With a neat diagram explain basic functional units of computer.
2. With a neat diagram explain basic operational concepts of computer.
(OR)
• Explain the concept of communication between memory and processor with the
respective registers. (*Also show how to add A + B to form C with the help of
same diagram
(OR)
• Define the functions of following processor registers: MAR, MDR, IP & IR.
1. What is performance measurement? Discuss the basic performance equation.
(Also explain the methods to improve the performance of the computer)
2. Write a note on: (a) Byte addressability (b) Big-Endian and Little-Endian
assignment.
3. With a memory layout starting at address ‘i’ represent how ‘ABCD’ data is stored
in big endian and little endian assignment scheme in a system of word length 16
bits.