John Aynsley provides an in-depth overview of advanced UVM concepts including sequences and sequencers, virtual sequences, layered sequencers for request-response transactions, and strategies for synchronizing multiple sequencer stacks. The document discusses techniques for modeling pipelined interfaces, out-of-order responses, and idle cycles in a driver. It also examines the arbitration queue, user-defined arbitration algorithms, locking versus grabbing sequences, and using events to synchronize different components.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
SystemVerilog based OVM and UVM Verification MethodologiesRamdas Mozhikunnath
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For more online courses and resources follow http://verificationexcellence.in/
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The System Verilog UVM promises to improve verification productivity while enabling teams to share tests and test benches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately the UVM promise can be hard to reach without training, practice and some significant expertise. Verification is one of the most important activities in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification.
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Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
AXI is an on-chip, point to point communication protocol. It is used as a high-performance bus in various IP or SoC Systems. It is used for connecting high-performance processors with memory.
SystemVerilog based OVM and UVM Verification MethodologiesRamdas Mozhikunnath
Introduction to System Verilog based verification methodologies - OVM and UVM concepts
For more online courses and resources follow http://verificationexcellence.in/
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
The System Verilog UVM promises to improve verification productivity while enabling teams to share tests and test benches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately the UVM promise can be hard to reach without training, practice and some significant expertise. Verification is one of the most important activities in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification.
How to create SystemVerilog verification environment?Sameh El-Ashry
Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
AXI is an on-chip, point to point communication protocol. It is used as a high-performance bus in various IP or SoC Systems. It is used for connecting high-performance processors with memory.
Locks? We Don't Need No Stinkin' Locks - Michael BarkerJAX London
Embrace the dark side. As a developer you'll often be advised that writing concurrent code should be the purview of the genius coders alone. In this talk Michael Barker will discard that notion into the cesspits of logic and reason and attempt to present on the less understood area of non-blocking concurrency, i.e. concurrency without locks. We'll look the modern Intel CPU architecture, why we need a memory model, the performance costs of various non-blocking constructs and delve into the implementation details of the latest version of the Disruptor to see how non-blocking concurrency can be applied to build high performance data structures.
Slides from tech talk about the art of non-blocking waiting in Java with LockSupport.park/unpark and AbstractQueuedSynchronizer. Presented on JPoint 2016 Conference.
Async and parallel patterns and application design - TechDays2013 NLArie Leeuwesteijn
TechDays2013 NL session on async and parallel programming. Gives an overview of todays relevant .net technologies, examples and tips and tricks. This session will help you to understand and select and use the right async/parallel technology to use in your .net application. (arie@macaw.nl)
Lie to Me: Bypassing Modern Web Application FirewallsIvan Novikov
The report considers analysis of modern Web Application Firewalls. The author provides comparison of attack detection algorithms and discusses their advantages and disadvantages. The talk includes examples of bypassing protection mechanisms. The author points out the necessity of discovering a universal method of masquerading for vectors of various attacks via WAFs for different algorithms.
Everything you wanted to know about Stack Traces and Heap DumpsAndrei Pangin
Stack traces and heap dumps are not just debugging tools; they open a doorway to the very heart of the Java Virtual Machine. This session is focused on peculiarities of JDK somehow related to heap walking and thread stacks.
• How to create dump in production without side effects?
• What is the performance impact of stack traces?
• How do jmap and jstack work under the hood, and what is special about 'forced' mode?
• Why do all profilers lie, and how to deal with it?
• How to scan heap using JVMTI?
The presentation supported by the live demos will address all these questions. It will also introduce new Java 9 Stack-Walking API (JEP 259) and reveal some useful but little known features of HotSpot JVM.
Sangam 18 - Database Development: Return of the SQL JediConnor McDonald
A look at the techniques that middle tier developers can employ to get greater value out of their applications, simply by having an understanding of how the database works and how to make it sing.
Random stability in systemVerilog and UVM based testbenchKashyap Adodariya
All about random stability in sv and UVM based testbench including examples. Represent through example and dig. Also explain how any process get seed for randomize.
El siguiente entrenamiento es sobre el programa para la creación de aplicaciones de prueba de Keysight Technologies TestExec y las ventajas que ofrece la versión 8.1 del mismo - threaded sequence
Down to Stack Traces, up from Heap DumpsAndrei Pangin
Глубже стек-трейсов, шире хип-дампов
Stack trace и heap dump - не просто инструменты отладки; это потайные дверцы к самым недрам виртуальной Java машины. Доклад будет посвящён малоизвестным особенностям JDK, так или иначе связанным с обоходом хипа и стеками потоков.
Мы разберём:
- как снимать дампы в продакшне без побочных эффектов;
- как работают утилиты jmap и jstack изнутри, и в чём хитрость forced режима;
- почему все профилировщики врут, и как с этим бороться;
- познакомимся с новым Stack-Walking API в Java 9;
- научимся сканировать Heap средствами JVMTI;
- узнаем о недокументированных функциях Хотспота и других интересных штуках.
4. Sequences and Sequencers
4
TLM exportTLM export
TLM portTLM port
start_item(req);
finish_item(req);
seq_item_port.get(req);
5. A Simple Sequence
5
class my_seq extends uvm_sequence #(my_tx);
`uvm_object_utils(my_seq)
function new(string name = "");
super.new(name);
endfunction: new
task body;
repeat(4)
begin
req = my_tx::type_id::create("req");
start_item(req);
if (!req.randomize())
`uvm_error("", "failed to randomize")
finish_item(req);
end
endtask
endclass
6. Nested Sequences
6
class top_seq extends uvm_sequence #(my_tx);
...
`uvm_declare_p_sequencer(my_seqr)
...
task body;
repeat(3)
begin
my_seq seq;
seq = my_seq::type_id::create("seq");
if (!seq.randomize())
`uvm_error("", "failed to randomize")
seq.start(p_sequencer, this);
end
endtask
... Parent sequenceParent sequenceSequencerSequencer
Variable that points to sequencerVariable that points to sequencer
7. Concurrent Sequences
7
task body;
fork
begin
seq1 = my_seq::type_id::create("seq1");
if (!seq1.randomize())
`uvm_error("", "failed to randomize")
seq1.start(p_sequencer, this);
end
begin
seq2 = my_seq::type_id::create("seq2");
if (!seq2.randomize())
...
seq2.start(p_sequencer, this);
end
begin
...
seq3.start(p_sequencer, this);
end
join
endtask
Transactions will be strictly interleavedTransactions will be strictly interleaved
8. The Finer Points of UVM
• Sequences and sequencers
• The arbitration queue
• Virtual sequences
• Request and response
• Multiple sequencer stacks
10. Setting the Arbritration Algorithm
10
task body;
p_sequencer.set_arbitration(
SEQ_ARB_STRICT_RANDOM);
fork
begin
seq1 = my_seq::type_id::create("seq1");
if (!seq1.randomize())
`uvm_error("", "failed to randomize")
seq1.start(p_sequencer, this, 1);
end
begin
...
seq2.start(p_sequencer, this, 2);
end
begin
...
seq3.start(p_sequencer, this, 3);
end
join
endtask Priority (default 100)Priority (default 100)
11. Arbitration Algorithms
11
Arbitration mode Order in which requests granted
SEQ_ARB_FIFO FIFO order (default)
SEQ_ARB_RANDOM Random order
SEQ_ARB_STRICT_FIFO Highest priority first, then FIFO order
SEQ_ARB_STRICT_RANDOM Highest priority first, then random order
SEQ_ARB_WEIGHTED Weighted by priority
SEQ_ARB_USER User-defined
12. User-Defined Arbitration Algorithm
12
class my_sequencer extends uvm_sequencer #(my_tx);
...
function integer user_priority_arbitration(
integer avail_sequences[$]);
foreach (avail_sequences[i])
begin
integer index = avail_sequences[i];
uvm_sequence_request req = arb_sequence_q[index];
int pri = req.item_priority;
uvm_sequence_base seq = req.sequence_ptr;
if (pri > max_pri)
...
end
return max_index;
endfunction
endclass
Could access properties of the sequence objectCould access properties of the sequence object
13. The Finer Points of UVM
• Sequences and sequencers
• The arbitration queue
• Virtual sequences
• Request and response
• Multiple sequencer stacks
14. Virtual Sequences
14
priority
seq1
priority
seq1
vseq.start(seqr0, null, priority)
body
fork
seq1.start(seqr1, this)
body
start_item
...
seq2.start(seqr2, this, 50)
body
start_item
...
seqr1
seqr2
seqr3
Blocks
Inherits priority
Blocks
Inherits priority
seqr0 Can be nullCan be null
No transactions
15. Sequencer Lock
15
seqr1
seqr0
No transactions
vseq.start(seqr0, null)
body
begin
this.lock(seqr1);
seq1.start(seqr1, this);
body
start_item
finish_item
this.unlock(seqr1);
...
priority
seqx
priority
seqx
priority
seqy
priority
seqy
priority
seq1
priority
seq1
Important!Important!
17. The Finer Points of UVM
• Sequences and sequencers
• The arbitration queue
• Virtual sequences
• Request and response
• Multiple sequencer stacks
18. Request and Response
18
TLM exportTLM export
TLM portTLM port
start_item(req);
finish_item(req);
get_response(rsp);
seq_item_port.get(req);
seq_item_port.put(rsp);
req rsp
The paper describes in detail
how to code pipelined req/rsp
and out-of-order responses
The paper describes in detail
how to code pipelined req/rsp
and out-of-order responses
20. The Finer Points of UVM
• Sequences and sequencers
• The arbitration queue
• Virtual sequences
• Request and response
• Multiple sequencer stacks
21. Multiple Agents / Sequencer Stacks
21
Communicate or
synchronize?
Communicate or
synchronize?
get(req)
Must not
block!
Must not
block!Driven by the DUT interface timingDriven by the DUT interface timing
Analysis ports
Callbacks
Events
Barriers
Analysis ports
Callbacks
Events
Barriers
22. Driver calls try_next_item
22
seq_item_port.try_next_item(req);
if (req == null)
begin
dut_vi.idle <= 1;
...
@(posedge dut_vi.clock);
end
else
begin
seq_item_port.item_done();
dut_vi.idle <= 0;
...
@(posedge dut_vi.clock);
...
seq_item_port.put(rsp);
Wiggle pins for idle cycleWiggle pins for idle cycle
Must be called in same time stepMust be called in same time step
Response can be pipelinedResponse can be pipelined
23. The Finer Points of UVM
• The UVM sequence library
• Pipelined requests and responses
• The response handler
• UVM events and event pools
• The configuration database
Also in the paperAlso in the paper