0015.register allocation-graph-coloring
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The document discusses register allocation techniques used by compilers to optimize code generation. It describes how register allocation works by constructing a register interference graph and using graph coloring algorithms to assign temporaries to a limited number of machine registers. When graph coloring fails to find a solution, spilling of temporaries is used to reduce interferences and allow coloring. Cache optimization is also briefly covered.
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Control-flow analysis discovers the flow of control within code by building basic blocks and a control-flow graph (CFG). It identifies loops by computing dominators. Basic blocks are sequences of straight-line code with a single entry and exit. A CFG represents control flow with nodes for basic blocks and edges for control transfers. Loops are detected by finding natural loops defined by back edges where the target dominates the source.
Dominator tree
1) The document discusses dominator trees and feedback cuts for a graph.
2) It provides the pre-order and post-order traversals for the dominator tree and post dominator tree of the graph.
3) The document also presents the total time complexity of O(N+E*D) for an algorithm to compute dominator sets, where N is the graph size, E is the number of edges, and D is the size of the largest dominator set.
Work items
This document contains summaries of various work items including:
1. ATPG work including converting test patterns between different formats and enhancing path delay testing.
2. CPU testing including developing test suites for different CPU performance bins and optimizing the test flow.
3. JTAG work including developing a software solution and using JTAG for debugging.
4. External work for ARM including developing system models and an emulator for the ARM bus architecture and cross compilers.
Work items
This document contains summaries of various work items including:
1. ATPG work including converting test patterns between different formats and enhancing path delay testing.
2. CPU testing including developing test suites for different CPU performance bins and optimizing the test flow.
3. JTAG work including developing a software solution and using JTAG for debugging.
4. External work for ARM including developing system models and an emulator for the ARM bus architecture and cross compilers.
ocelot
The document describes several passes that are performed by PTXOptimizer to optimize PTX code for GPU execution. The passes include subkernel formation, barrier removal, register allocation, and MIMD thread scheduling. The goals of the passes are to reduce kernel loading time, reduce thread waiting at barriers, increase data sharing between threads, and enable more parallel thread execution.
Lect.10.arm soc.4 neon
ARM was founded in 1990 and developed the first ARM processor in 1985. Key developments include the ARM2 commercial processor in the 1980s, the ARM7 used in early Nokia phones in the 1990s, and the modern Cortex-A9 which provides improved performance and power efficiency through features like out-of-order execution and cache hierarchies. NEON is ARM's SIMD architecture extension for improved media and signal processing, and it is now widely used in mobile software from Android to ffmpeg to accelerate tasks like video encoding and FFTs.
Image scalar hw_algorithm
The document discusses an image scalar hardware algorithm and proposes improvements. It analyzes issues with the current approach of no burst support and non-continuous addressing. It suggests adding burst mode support to increase efficiency, allow easier idle states, and reduce bus access time. This would help pipeline the computation and decrease hardware resource needs with buffering.
Virtual platform
This document discusses building a virtual platform for the OpenRISC architecture using SystemC and transaction-level modeling. It covers setting up the toolchain, writing test programs, and simulating the platform using event-driven or cycle-accurate simulation with Icarus Verilog or the Vorpsoc simulator. The virtual platform allows fast development and debugging of OpenRISC code without requiring physical hardware.
Spi
The document provides an overview of the Serial Peripheral Interface (SPI) bus including its definition, protocol, and use in iBoot.
The SPI bus is a synchronous serial data standard that uses four signals - Serial Clock, Master Output/Slave Input, Master Input/Slave Output, and Slave Select. It allows for a single master with one or more slave devices.
iBoot uses SPI for communication and defines registers, buffers, and methods for controlling the SPI clock, installing interrupts, and transferring data. References are provided for more information on SPI and iBoot.
Serializer
This document outlines the design of a serializer circuit. It discusses the fundamentals of serial links and phase locked loops (PLLs), including phase frequency detectors (PFDs), charge pumps, voltage controlled oscillators (VCOs), and dividers. It also covers serializer cells, circuits, and output drivers. Simulation results are presented on PLL parameters like bandwidth and jitter. The design is aimed at serial data transmission rates of 1.6Gbps and above.
Defense
The document proposes a design automation tool that represents a system from the behavioral level down to the transaction level for virtual bus-based platforms. It aims to allow for rapid system exploration and speed up simulation cycles by translating from behavioral descriptions to transaction-level models. Previous works are discussed that did not consider communication aspects. The proposed tool features a representation, design flow, block-level methodology for reducing computation and communication, and a translation process from control/data flow graphs to a transaction-level SystemC implementation.
Defense
The document proposes a design automation tool that represents a system from the behavioral level down to the transaction level for virtual bus-based platforms. It aims to allow for rapid system exploration and speed up the design process. Previous works are discussed that did not consider communication issues or allow automatic generation. The proposed tool includes representations of control and data flow, a design flow from block to system level, and methodologies for reducing computation and communication with translations to transaction level models.
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