The project focused on designing and fabricating a 5-bit dynamic pseudorandom sequence generator integrated circuit (dprsg) at Carleton University, utilizing various digital logic components and custom layouts. It details the design process, specifications, individual block designs, and a final layout while ensuring simulation tests like DRC and LVS were performed to verify functionality. Challenges included dimension reductions for the d-flip-flop and managing oscillator clock signals to minimize overlap in the clock phases.

1. ELEC 4609 A1O - Integrated Circuit Design & Fabrication
IC Design Project
5-BIT DYNAMIC PSEUDORANDOM
SEQUENCE GENERATOR
April 11, 2019
Rashad Alsaffar - 101006781
Mohammad Danyal - 101003904
Carleton University
Department of Electronics

2. IC Project Report Rashad Alsaffar - 101006781
Contents
1 Introduction 3
1.1 Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Project Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 System Level Block Diagram 3
3 Design of Individual Blocks 4
3.1 INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 Oscillator/Master Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6 2-Phase Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Top Level Block Discussion 12
4.1 Top Level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Schematic of Complete Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Spectre Simulation of PRSG Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Spectre Simulation of PRSG Output w/ RESET . . . . . . . . . . . . . . . . . . . . . 13
4.5 DPRSG Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Input Protection Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 DRC of Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 LVS of Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9 SPICE Simulation of Extracted Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10 Differences between Schematic and Extracted DPRSG . . . . . . . . . . . . . . . . . 15
4.11 Minimizing Layout Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.11.1 INV, NAND, NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11.2 XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11.3 Master Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11.4 2-Phase Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11.5 D-Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Appendices 18
5.1 Appendix A: DRC Final Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Appendix B: LVS Final Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Appendix C: Alternative Component Designs . . . . . . . . . . . . . . . . . . . . . . 21
5.3.1 D-Flip-Flop Alternative Design . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3. IC Project Report Rashad Alsaffar - 101006781
1 Introduction
Integrated circuit design is integral to the establishment of many modern circuits and the future of
electronics. Design of IC chips has evolved from hand-held techniques to complex software and fabri-
cation tools that express the sophistication and finesse of a skilled designer towards the final product.
The purpose of this project was to design and fabricate an IC tailored to act as a 5-bit pseudo-
random sequence generator (DPSRG), similar to that of a bicycle taillight circuit; a random flash
pattern is generated that repeats after 31 bits. The building blocks of the circuit were first de-
signed in schematic form within Cadence Virtuoso. Symbols were created to expand and simplify
the schematic design of larger components. Simulations were performed for each component to test
their individual performance.
Layout blocks for each component were created through Virtuoso XL. DRC and LVS tests were ex-
ecuted to confirm appropriate design restrictions and performance in layout form. The final project
layout contained all layout cells and was verified through DRC and LVS before submission.
1.1 Design Specifications
The following points characterize the assigned design specification of our IC:
− Chip Dimension: 230λ x 240λ ⇒ Bond Pad Size: 40λ x 40λ
− FET Dimensions: w, l intervals of 2.4µm
− Carleton University CMOS SOI Technology
− Operating Voltage: 3V Supply (two series AA batteries)
1.2 Project Management
The IC design work was distributed amongst our group as follows:
Rashad Alsaffar: Mohamamd Danyal:
− Oscillator − D-Flip Flop
− 2-Phase Clock Generator − Output Driver
− XNOR Gate
2 System Level Block Diagram
Figure 1: System Level Block Diagram of DPRSG

4. IC Project Report Rashad Alsaffar - 101006781
The figure above details the system level block diagram characterizing all high-level components
applied towards the final design.
An oscillator/master clock generates a clock signal PHI (φ). PHI is fed into the 2-Phase Clock
Generator, producing two non-overlapping clock signals PHI 1 (φ1) and PHI 2 (φ2).
Clock signals φ1 and φ2 are fed into a series of five D Flip-Flops creating a shift register; when
φ1 is high the D Flip-Flop will accept input data and when φ2 the device will output data.
3 Design of Individual Blocks
3.1 INV
The schematic for the inverter was designed using a single PMOS and single NMOS. The lengths
of both devices were kept constant. PMOS width is double NMOS width due to the mobility of
electrons is twice that of the mobility of holes.
The schematic and layout of the inverter device is displayed below:
Figure 2: INV Schematic
Figure 3: INV Layout
The truth table below details the expected behavior of the inverter device. Note that A resembles
input of PMOS and B resembles input of NMOS:
A B Output
0 0 1
0 1 0
1 1 0
1 0 0
Table 1: INV Truth Table

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3.2 NAND
The schematic for the NAND was designed using two parallel PMOS and two series NMOS. Length
(L) and width (W) dimensions for each FET were attuned to the same design rules as the INV.
The schematic and layout of the NAND device is displayed below:
Figure 4: NAND Schematic
The truth table below details the expected behavior of the NAND device:
A B Output
0 0 0
0 1 0
1 1 1
1 0 0
Table 2: NAND Truth Table
Figure 5: NAND Layout

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3.3 NOR
The schematic for the NOR was designed using two series PMOS and two parallel NMOS. L, W for
each FET were attuned to the same design rules as the INV.
The schematic and layout of the NOR device is displayed below:
Figure 6: NOR Schematic
The truth table below details the expected behavior of the NOR device:
A B Output
0 0 0
0 1 1
1 1 1
1 0 1
Table 3: NOR Truth Table
Figure 7: NOR Layout

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3.4 XNOR
The schematic for the XNOR was designed using a collection of four NAND gates and a single NOR
gate. L, W for each FET were attuned to the same design rules as the INV.
The schematic and layout of the NOR device is displayed below:
Figure 8: XNOR Schematic
The truth table below details the expected behavior of the XNOR device:
A B Output
0 0 0
0 1 1
1 1 0
1 0 1
Table 4: XNOR Truth Table
Figure 9: XNOR Layout

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3.5 Oscillator/Master Clock Generator
The schematic for the Master Clock Generator was designed using a collection of four series INV
gates in addition to an external capacitance noted by pins C1 and C2. An NMOS with a L/W ratio
of 20 was included as well. L, W for each FET were attuned to the same design rules as the INV.
The schematic, layout and simulation of the Master Clock Generator device are displayed below:
Figure 10: Master Clock Generator Schematic
Figure 11: Master Clock Generator LTSpice Waveform Simulation
Figure 12: Master Clock Generator Layout

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3.6 2-Phase Clock Generator
The schematic for the 2-Phase Clock Generator was designed using a collection of two separated
groups of six INV and two NAND gates in addition to an additional INV gate to generate a sec-
ondary clock. L, W for each FET were attuned to the same design rules as the INV.
The schematic, layout and simulation of the Master Clock Generator device are displayed below:
Figure 13: 2-Phase Clock Generator Schematic
The plots below display the two generated phase outputs φ1 (top) and φ2 (bottom):
Figure 14: 2-Phase Clock Generator LTSpice Full Waveform Simulation
The plot below displays the overlapping behavior between φ1 and φ2:
Figure 15: 2-Phase Clock Generator LTSpice Overlap Waveform Simulation

10. IC Project Report Rashad Alsaffar - 101006781
It is important that overlap remains minimum as possible. As previously mentioned, the D Flip-Flop
will sample data φ1 is high, and will output data when φ2 is high. A large overlap occurrence would
potentially result in the D Flip-Flop not being able to differentiate between which clock signal is
high and low. This could result in false performance operation.
Figure 16: 2-Phase Clock Generator Layout
3.7 D Flip-Flop
The schematic for the inverter was designed using two INV gates. L, W dimensions were doubled
from the INV gate due to a lack of current flow resembled in the TOP output module. Note: due to
lack of space on final chip D Flip-Flop device dimensions were reduced.
The schematic and layout of the D Flip-Flop device is displayed below:
Figure 17: D Flip-Flop Schematic Figure 18: D Flip-Flop Layout
Two NMOS transmission gates were also included. The selected FET dimensions were L = 38.4µm
and W = 4.8µm. NMOS transistors are more likely to have lower off-stage channel leakage, and
therefore was used instead of PMOS.

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The used transmission gate device should resemble the dimensions of a pull-up device; lack of resem-
blance between models may result in corrupted stored data as a result of charge injection.
3.8 Output Buffer
The schematic for the Output Buffer was designed using a W
L
ratio of 50. The wide MOSFET device
would be used to drive the external load. The figures below display the schematic and layout of the
structured output buffer:
Figure 19: Output Buffer Schematic
Figure 20: Output Buffer Layout

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4 Top Level Block Discussion
4.1 Top Level Schematic
The top level schematic displayed below includes the full DPRSG, external capacitor and specified
LED model, as well as RESET, VDD and VSS signals:
Figure 21: Top Level Schematic of DPRSG
4.2 Schematic of Complete Circuit
The schematic of the complete circuit is detailed below, with the identifiable shift register chain,
XNOR gate, output buffer, master clock/oscillator and 2-phase clock generator:
Figure 22: Complete Schematic of DPRSG

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4.3 Spectre Simulation of PRSG Output
The simulation of the DPRSG output represents the initially configured setup for the transistor
values within the D-Flip-Flop configuration. Reduced dimensions were established due to sizing
irregularities within the final layout. Reduction of transistor sizing within the flip flop components
decreases their current draw, corresponding to a smaller output voltage swing, i.e. from 0-1.5V.
Instead, the captured Cadence Spectre simulations below detail the response of the original circuit
response with transistor dimensions corresponding to an appropriate 0-3V output voltage swing:
Figure 23: DPRSG Spectre Simulation
4.4 Spectre Simulation of PRSG Output w/ RESET
The captured Cadence Spectre simulations below detail the response of the original circuit response
with a RESET pulse:
Figure 24: DPRSG Spectre Simulation w/ RESET Pulse

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4.5 DPRSG Final Layout
The final layout of the DPRSG integrated circuit was implemented onto a 230λ x 240λ chip. All
modules including the oscillator/2-phase clock generator configuration, XNOR gate, and D Flip-Flop
shift register sequence.
All required input protection circuits and I/O pads for the external capacitor and LED are in-
cluded. Power rails were created connecting VDD and VSS to their corresponding pads.
Figure 25: Final Layout of DPRSG

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4.6 Input Protection Layout
An example of input protection layout circuitry is displayed in the figure below:
Figure 26: Input Protection Layout
Large well and poly lines ensured that the input signal would be received, dissipating unwanted
sources and protecting the circuit.
4.7 DRC of Final Layout
See full results in Appendix A.
4.8 LVS of Final Layout
See full results in Appendix B.
4.9 SPICE Simulation of Extracted Circuit
Unfortunately we did not know how to generate a proper netlist from within Cadence to import as
an HSPICE file. The design did in fact miss the manufacturing deadline and therefore a real-life
simulation was not possible to provide.
4.10 Differences between Schematic and Extracted DPRSG
The integration of multiple materials, particularly metal and poly crossing and in close proximity
creates unwanted parasitic capacitance. This in turn will affect the simulation of the extracted layout
circuit.
4.11 Minimizing Layout Area
The process of minimizing layout area heavily involved several design iterations to produce a feasible
design.

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It was just as important to constantly check DRC for complicated design iterations at each turn to
ensure the layout process was structured well.
LVS testing occurred within the final stages of the layout, and from that point decisions were made
to ensure minimum layout area whilst DRC/LVS testing had passed for each component.
Each component minimization process is discussed in detail in the following sections, iterating design
decisions selected to further minimize layout area and provide explanation for faults made throughout
the process.
4.11.1 INV, NAND, NOR
The NAND and NOR gate development cycle had initially been formatted as their schematic coun-
terparts in terms of FET orientation, i.e. Figures 4 and 6. This proved to increase the area of the
layout, and therefore decisions were made to integrate PMOS and NMOS transistors by having them
share terminals, i.e. drain/source with respect to the intended gate creation, as can be seen in the
final layout iteration described in Figures 5 and 7.
It is important to note that the transistor sizing decisions for all INV, NAND and NOR gates
involved using a 2:1 W
L
ratio for PMOS devices compared to NMOS devices, due to generally weaker
current draw through PMOS transistors.
4.11.2 XNOR
The XNOR design required particular thought in the final layout design. An early design decision
was to provide shared VDD connections between NAND gates to save space. Once again, the original
design involved orienting the gates in the same form of its schematic counterpart, and while this made
the device narrow, it was much longer than intended. Instead, the provided gates were oriented in
a square-like shape with particular thought given to the distribution of metal and poly connections
avoiding overlap by providing contacts when necessary, shortening layout area seen in Figure 9.
4.11.3 Master Clock Generator
Following the practices of the XNOR design, all included INV gates were oriented in a square-like
fashion with effective VDD connections among all components. The the addition of a long FET
with a L/W ratio of 20 initially proved as a struggle, mainly due to providing enough room for all
connections to be applied within the final layout, i.e. connections to C1, C2, VDD and VSS pads.
The main priority was to ensure that all DRC/LVS tests were successful before proceeding with the
remainder of the components. Note that the schematic replaced the capacitor with two InputOutput
signal pins C1 and C2 due to the lack of recognition of a capacitor component within the layout
editor.
4.11.4 2-Phase Clock Generator
The 2-Phase Clock Generator contained the largest amount of logic gates, and therefore was expected
to have the largest layout area. This design in particular was challenging when handling connections
involving power sources (VDD and VSS). INV gates were simple to share VDD power sources, however
NAND gates could not be handled the same way due to cross-input connections from the second to
last INV gates on the top and bottom level as seen in the schematic within Figure 13. Poly connec-
tions were required to connect metal power lines to avoid metal connections from other components
overlapping. Once again, DRC/LVS tests were iterated multiple times due to the importance and
size of the layout.

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4.11.5 D-Flip-Flop
The D-Flip-Flop creation was the most controversial within the design process; five iterations of the
device were to be spread throughout the final chip layout. Initially the D-Flip-Flops encountered a
transistor size increase due to the lack of current draw, resulting in the output voltage captured by
the simulation swinging from 0-1.5V. As a result of doubling the ratio (see Appendix C for previous
layout/schematic), the output voltage was corrected, handling a proper swing from 0-3V.
Unfortunately, this resulted in problems with layout generation, particularly with the size of the
transistors. The plan was to segregate half of the final chip to the master clock generator, 2-phase
clock generator and XNOR gate and reside the other half to the five D-Flip-Flop gates. The original-
sized D-Flip-Flops (see Appendix C) were unfortunately too large, and instead were cut down and
restructured to reduce layout area, resulting in the finalized schematic/layout characterized in Fig-
ures 17 and 18.
DRC/LVS testing ensured proper device functionality. Admittedly further enhancements could be
made in future design alterations to tweak the size of the D-Flip-Flop composed transistors to increase
current flow delivering a larger output voltage swing.

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5 Appendices
5.1 Appendix A: DRC Final Results
Figure 27: DRC Final Results

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5.2 Appendix B: LVS Final Results

20. IC Project Report Rashad Alsaffar - 101006781
Figure 28: LVS Final Results

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5.3 Appendix C: Alternative Component Designs
5.3.1 D-Flip-Flop Alternative Design
Figure 29: Previous Model Schematic of D-Flip-Flop w/ 0-3V Output Voltage Swing
Figure 30: Previous Model Layout of D-Flip-Flop w/ 0-3V Output Voltage Swing