International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed...VLSICS Design
Abstract This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed...VLSICS Design
Abstract This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Ieee Xpert
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Ieee Xpert
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOL...VLSICS Design
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
An Innovative Design solution for minimizing Power Dissipation in SRAM CellIJERA Editor
Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based o...IOSR Journals
Abstract: Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold
voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We
analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for
ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design
requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better readstability
as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to
propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and
less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were done using DSCH and Microwind.
Index Terms: read stability, write ability, Schmitt trigger.
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Spee...VLSICS Design
This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Elevating Tactical DDD Patterns Through Object Calisthenics
Af34193199
1. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
193 | P a g e
Implementation Of Low Power SRAM By Using 8T Decoupled
Logic
K.R.Surendra, K.Venkatramana Reddy
(Department of ECE, M.Tech Student, SVCET, Chittoor, India)
(Department of ECE, Asst. Professor, SVCET, Chittoor, India)
ABSTRACT
We present a novel half-select disturb
free transistor SRAM cell. The cell is 6T based
and utilizes decoupling logic. It employs gated
inverter SRAM cells to decouple the column
select read disturb scenario in half-selected
columns which is one of the impediments to
lowering cell voltage. Furthermore, “false read”
before write operation, common to conventional
6T designs due to bit-select and word line timing
mismatch, is eliminated using this design. Two
design styles are studied to account for the
emerging needs of technology scaling as designs
migrate from 90 to 65 nm PD/SOI technology
nodes. Namely we focus on a 90 nm PD/SOI sense
Amp based and 65 nm PD/SOI domino read
based designs. For the sense Amp based design,
read disturbs to the fully-selected cell can be
further minimized by relying on a read-assist
array architecture which enables discharging the
bit-line (BL) capacitance to GND during a read
operation. This together with the elimination of
half-select disturbs enhance the overall array low
voltage operability and hence reduce power
consumption by 20%–30%.
The domino read based SRAM design
also exploits the proposed cell to enhance cell
stability while reducing the overall power
consumption more than 30% by relying on a
dynamic dual supply technique in combination of
cell design and peripheral circuitry. The
feasibility of the cell and sensitivity to sense Amp
timing has been proved by fabricating a 32 kb
array in a 90-nm PD/SOI technology.
Keywords-Column-decoupled, differential/domino
read, half-select, low power 8T, SRAM, stability.
I. INTRODUCTION
DEVICE miniaturization and the rapidly
growing demand for mobile or power-aware systems
have resulted in an urgent need to reduce power
supply voltage (Vdd). However, voltage reduction
along with device scaling is associated with
decreasing signal charge. Furthermore, increasing
intra-die process parameter variations, particularly
random dopant threshold voltage variations can lead
to large number of fails in extremely small channel
area memory designs. Due to their small size and
large numbers on chip, SRAM cells are adversely
affected. This trend is expected to grow significantly
as designs are scaled further with each technology
generation [1]. Particularly, it conflicts with the need
to maintain a high signal to noise ratio, or high noise
margins, in SRAMs and is one of the major
impediments to producing a stable cell at low
voltage. When combined with other effects such as
narrow width effects, soft error rate (SER),
temperature, and process variations and parasitic
transistor resistance, the scaling of SRAMs becomes
increasingly difficult due to reduced margins [2].
The plot indicates that the SRAM area
scaling drops below 50% for 32-nm technology and
beyond. Furthermore, voltage scaling is virtually
nullified. Higher fail probabilities occur due to
voltage scaling, and low voltage operation is
becoming problematic as higher supply voltages are
required to conquer these process variations. To
overcome these challenges, recent industry trends
have leaned towards exploring larger cells and more
exotic SRAM circuit styles in scaled technologies.
Fig. 1 illustrates the saturation in the scaling trend
(dashed line) of SRAM cells across technology
generations.
Examples are the use of write-assist design
[3], read-modify-write [4], read-assist designs [5],
and the 8T register file cell [6], [7]. Conventional 6T
used in conjunction with these techniques does not
lead to power saving due to exposure to half select
condition [3], [4].
Column select/half-select is very commonly
used in SRAMs to provide SER protection and to
enable area efficient utilization and wiring of the
macro. Nevertheless, the use of column select
introduces a read disturb condition for the unselected
cells along a row (half-selected cells), potentially
destabilizing them. In this paper we present a new
column-decoupled 6T-based SRAM cell where read
2. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
194 | P a g e
disturb is eliminated for column selected/ half
selected cells [5], [8]. The decoupling logic uses two
additional devices and henceforth we will refer to
the cell as the 8T-column-decoupled-cell (8T-CDC).
We study the cell in the presence of two design
styles: namely, sense Amp-based read peripheral
circuitry that was typical for the 90-nm node, and
domino read peripheral circuitry [9] for 65 nm and
beyond. In a sense Amp-based read design, the read
disturb condition is further minimized for the
selected cells by the use of a sense-amp architecture
which actively discharges the selected cell(s) BL to
GND, thereby eliminating the source of disturb.
Through a combination of accurate simulations and
hardware (HW) data acquired from a 32 kb SRAM
macro, a path towards low voltage SRAM operation
of the cells is shown, and the design is shown to
enhance read stability and half-select stability
problems thereby enabling improved .
However, process variations are
increasingly affecting sense Amp designs in PD/SOI
designs and it is natural to converge to domino-read
designs [9]. In domino read-based designs, the
column-decoupled cell still maintains guard against
half-select cell disturbs. However, with the absence
of read-assist feature in domino designs, we need to
account for the read disturb on fully-selected cells.
For this, we propose a dynamic dual supply header
design that leverages the benefits of the column
decoupled cell design and helps save power. As is
the case with traditional dual supply techniques, the
proposed header design maintains separate cell
supply (Vcs) and logic supply (Vdd). However,
unlike traditional techniques, the dynamic cell
supply changes based on the column selection status.
The new header design sets: 1) the selected cell
columns at a voltage supply higher than the logic
one for improved read stability and 2) maintains a
low supply for half-select cells since half-select
disturbs are not an issue for this design. Hence, we
rely on the column-decoupled cell to enable a
simplified low-power high performance column-
decoupled domino read based design. We implement
the design using simplified bit-select logic and
dynamic supply headers with shorter bitlines. In
what follows, we provide a thorough analysis into
the design modifications compared to the traditional
6T dynamic supply designs. We also highlight the
advantages this methodology brings in terms of
lower power and yield improvements.
A localized gated inverter consisting of two
additional transistors, T1 and T2, effectively perform
a logical “AND” operation between the column
select signal (BDT0) and the decoded row, or global
wordline, GWLE. The output of the inverter is the
local wordline signal (LWLE0). The local wordline
is ON only when both the column and row are
selected (i.e., for fully selected cells only); hence, as
illustrated in the waveforms of Fig. 3, LWLE0 of the
selected columned turns ON while LWLE1 of the
half-selected column remains low.
II. 8T COLUMN DECOUPLED CELL
2.1 Proposed 8T-CDC
Fig. 2 illustrates a new 8T-CDC SRAM cell (inside
dashed rectangle) with a gated wordline which
enables the decoupling of the column/half-select
condition [5] hence eliminating half select stability
fails.
This ensures that the local wordline for
only the selected cells is activated, thereby
effectively protecting the half-selected SRAM cells
from the read disturb scenario that exists in 6T cell
due to wordline sharing. Alternatively, it is possible
to swap the input and supply pairs of the gated
inverter; however this comes at the cost of extra
delay stage and power. The advantages of the 8T-
CDC cell are as follows: 1) conforming with
traditional 6T requirements in terms of (a) allowing
the designer to integrate it in a column select fashion
and (b) offering/maintaining SER protection while
2) maximizing array efficiency, 3) eliminating the
read disturb to the unselected cells, and 4) reducing
power with simplification in peripheral logic.
Fig. 3(a) shows a layout view of the 8T-
column-decoupled cell in a 90-nm PD/SOI
technology. The two extra devices are integrated on
top of an existing 6T cell to allow for easy cell
mirroring and integration into an array topology. The
addition of the two new transistors results in a cell
area increase of 40% (all in -direction). Through the
use of higher level metallurgy to wire in the column
decode (BDC) signal, the growth to the -direction of
cell was not impacted. The increase to the –
dimension of the cell causes a proportionate increase
to the BL metal capacitance while maintaining the
original diffusion capacitance contributed by the 6T
cell. Column decode signal integrated with higher
level metal. Area penalty can be further reduced to
30% via use of 6T thin cell integration in Fig. 3(b);
further reduction can be achieved by use of non-
DRC clean devices.
3. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
195 | P a g e
Fig. 3. Layout view of the new 8T-CDC SRAM cell
for a (a) typical cell and a (b) 2 �2 thin cell front
end of the line layout view and (c) back end of the
line layout view to show ROX and GND sharing.
Fig. 3(b) and (c) presents the front end of
the line (FEOL) and back end of the line (BEOL)
layout view of 2 8T-CDC thin cell. The views
illustrate how the recessed oxide (ROX) and power
buses are shared. The area can be reduced further to
30% by utilizing thin cells as presented in this paper
without degrading the bitline capacitance.
2.2 Timing Advantages: Elimination of “False
Read” Before Write
During the write operation in conventional
6T SRAM, when the wordline precedes ahead the
column-select in timing, then the cell starts reading
the data [8]. When the bitline droops, “false read”
before write happens [see Fig. 4(a)]. This is a
disadvantage for conventional 6T SRAM. This
particular drawback is overcome by the technique
that is proposed here as illustrated in the Fig. 4(b); if
the wordline arrives earlier than the column select it
will be gated by the column select and thus “false
read” before write does not ripple through the
bitlines to the evaluation logic.
III. SENSE AMPLIFIER BASED DESIGN
The 8T-CDC cell together with read-assist
sense amp designs [5] can mitigate the read disturb
problem both for selected and half-selected designs.
Fig. 4. (a) For conventional 6T SRAM, during write,
when the wordline precedes ahead the column-
select, the cell starts reading the data [8]. When the
bitline droops, “false read” before write happens. (b)
This particular drawback is overcome by the 8T-
CDC cell; the early wordline (GWLE in dashes) will
be gated by the column select and thus “false read”
before write does not happen.
3.1 Read Assist Sense Amp Based Design
Fig. 5 illustrates the 8T-CDC cell design
combined with read assist sense Amp. The sense
amplifier is shared among multiple columns. In a
typical sense Amp scenario, the bit switch (BDC),
and the WL on the selected cells columns are turned
off once enough margin is developed for the sense-
amplifier to accurately resolve the BL differential.
This is done to save ac power (prevents discharge of
BL to GND) and to speed up sense-time (smaller
capacitance for sense-amplifier to discharge). For
this scenario, only the PFET transistor exists (solid
bit switch PFET Fig. 7) and it closes during “Sense”
to save power and perform faster sense. In a read-
assist scenario the bit-switch PFET is converted to a
complementary (dashed line) NFET and PFET bit-
switch pair. The pair is kept open during the entire
WL active phase. Consequently, the sense-amp and
the cell discharge the BL completely during a sense-
read operation [5]. Hence the sense amplifier “sees”
the full BL capacitance during a read operation; it
discharges the capacitance to GND, and the cell data
is “written back”. This helps minimize the amount of
read disturb charge induced onto the cell from the
bitlines. Temperature/K”.
IV. SENSE AMPLIFIER APPROACH
ANALYSIS & RESULTS
To effectively evaluate the 8T-CDC cell, it
was compared to two versions of a 6T cell within the
same read disturb mitigating system. The first was a
default 6T (106 cell) and the second a 40% larger 6T
cell (149 cell); the latter is intended to compare
functionality gains under similar design area
constraints for 6T and 8T-CDC. It should be noted
4. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
196 | P a g e
that the cell devices within the 8T-CDC cell (PG,
PD, PU) are identical to the 106 cell, while the 149
cell has devices that are 40% larger than the 106
cell. For each cell type, simulations were run using
90-nm PD SOI technology to determine the cell’s
sigma to fail as a function of voltage. Simulations
were also performed to investigate the effect of SET
timings and BL height on each cell type. Finally area
and power tradeoffs were studied to determine
optimum design points. Also a chip was fabricated
and hardware results corroborate well with the
simulations.
In a typical scenario, PFET bit-switch
closes during sense to save power and perform faster
sense. In a read-assist scenario true/comp (dashed
line) NFET and PFET bit-switch pair is kept open
during sense. Hence the sense Amp “sees” the BL
capacitance; it discharges the capacitance to GND,
and the cell data is “written back”. This helps
minimize the amount of read disturb charge.
4.2. Simulation Results
In the following analysis, cell and logic
supplies are assumed the same. is minimum supply
needed to maintain the desired cell yield. Fig. 6
shows the cell yield in sigma values for the three
different cell options. For a BL height of 128 cells,
clamped half-select condition, and a 10% of Vdd BL
differential SET timing, the half-select stability fails
dominate in 6T.
Fig. 5. Gated 8T-CDC cell design combined with
read-assist sense Amp [5].
The 8T-CDC cell shows a marked improvement of
200 mV when compared to 6T (106 cell) and 80 mV
compared to 6T (149 cell). The comparison was
performed at the 5 sigma cell yield point. For
unclamped (floating BL) half-select, the 8T-CDC
curve remains unchanged; half-select is not an issue
for the 8T-CDC cell, and read stability graph
remains the same. A small improvement in (30 mV)
for the two 6T cells is noticed due to relaxation in
the half-select conditions for the 6T. This
improvement increases for shorter BL heights (50
mV for 32 cells/BL) [5]. The effect of SET timing
(for 8T-CDC) on yield sigma was investigated by
advancing the SET signal earlier during the read
cycle. Fig. 7 depicts this data for three different SET
timings (10%, 7%, and 5% of supply BL
differential). 8T-CDC cell improvement between 70
and 130 mV was observed compared to 10% margin
(for the 7% and 5%, respectively); again we
assumed 5 sigma yield point as the target for Vddmin.
Advancing SET timing will have no effect on for 6T
versions as half-selected cells will not derive any
benefit from the read disturb mitigating topology.
Finally, the dependence of BL height for the
unclamped case on cell was investigated and the
results plotted in Fig. 8. It can be seen that to
achieve a cell of 0.6 V (with 5 sigma yield), the 6T-
106 cell cannot be used, the 6T-149 cell offers only
one design option (32 cells/BL), while the 8T-CDC
cell offers several options to the designer (32 to 128
cells/BL with 10% to 7% BL margin SET timings).
Fig. 6. Cell yield in sigma values versus Vdd.
Clamped bitlines; load 128 cells/ bitline. Half-select
stability fails dominate in 6T. Even sized-up 6T (6T-
149) requires Vddmin increase of 80 mV and the
regular 6T requires an increase of 200 mV.
Fig. 7. It is possible to further improve �__ of 8T-
CDC with earlier set arrival (due to lowering margin
criteria of bitline drop voltage).
5. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
197 | P a g e
V. DOMINO READ BASED DESIGN
In the following sections, we discuss the
advantages of the proposed 8T-CDC design in the
presence of domino read based architectures as well
as the rationale behind these architectures.
As technology scales, sense-Amp devices
suffer from Vt-mismatch and scaling becomes
difficult particularly for PD/SOI technology designs
due to hysteretic Vt variation. Thus, it is preferred to
use large signal domino read circuitry [9]. During a
domino read, the dual rail signals from the cell are
amplified by skewed inverters to full rails. This
eliminates the dependency on bitline differential
which can be highly sensitive to Vt-mismatch and
we refer the reader to [9] and the references within
for a detailed overview of domino based read
designs. However, the SRAM cell read disturbs and
half-select problems are still critical in a domino
read design. In what follows, we study the
advantages of combining a decoupled half-select
column design cell design with dynamic supply
techniques for a 65-nm PD/SOI domino read-based
design.
Fig. 8. Unclamped bitlines: the half-select problem
still dominates in sized-up 6T-149 cell. For a target
of 0.6 V the 6T (149) must operate with 32
cells/bitline, whereas the 8T-CDC offers multiple
bitline height options.
Our goal is to exploit the elimination of
half-select disturbs together with dynamic supply
techniques for optimal yield and power. For this
purpose, we propose new header designs for the
dynamic supply suitable for the 8T-CDC cell. An
overview of the targeted domino-read memory
cross-section is illustrated in Fig. 9. Next, we revisit
traditional circuit and peripheral logic for 6T domino
designs and propose simplifications or modifications
as well as novel dynamic header designs suitable for
low-power 8T-CDC cell design.
Fig.9. 8T-CDC-decoupled cell memory cross-section
for domino read designs.
VI. SIMULATION RESULTS
In this project we used DSCH [Digital
Schematic] software for simulating the circuit and to
generate the code, MICROWIND is used to extract
the layout of the schematic diagram.
The following figure shows the schematic diagram,
Layouts and Simulation results of 6T and 8T SRAM
Cell using DSCH & MICROWIND.
6.1 SRAM 6T:
Fig: 6.1 Schematic diagram of one stage 6T SRAM
6.2 SRAM 6T LAYOUT:
Fig: 6.2 Layout of 6T SRAM cell
6. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
198 | P a g e
6.3 SRAM 6T PROPOSED:
Fig 6.3 Schematic diagram of 2 stages 6T SRAM cell
6.4 SRAM 6T PROPOSED LAYOUT:
Fig: 6.4 Proposed Layout of 6T SRAM cell
6.5 SIMULATION RESULT OF SRAM 6T:
Fig: 6.5 Simulation results of SRAM 6T
6.6 SRAM 8T:
Fig: 6.6 Schematic diagram of SRAM 8T cell
6.7 SRAM 8T LAYOUT:
Fig: 6.7 Layout of proposed 8T SRAM Cell
6.8 SIMULATION RESULT OF SRAM 8T:
Fig: 6.8 Simulation results of SRAM 8T
VII. CONCLUSION
We studied a novel 8T-CDC column-
decoupled SRAM design. The half-select free design
enables enhanced voltage scaling capabilities, and
30%–40% power reduction in comparison to
standard 6T techniques. This study involved a 90-nm
read assist-based sense Amp design, and a 65-nm
domino read-based design with dynamic supply
capabilities. The 8T-CDC cell enables significant
power savings in terms of reduction for read-assist
design, and half-select column power reduction in
dynamic dual supply domino read designs with the
aid of new header designs. New simplified local
evaluation logic and shorter bitlines are employed
for the domino read-based design. Simulations
showed high performance for the proposed design
using shorter bitlines, and dynamic header circuit.
Measured hardware data from fabricated chips in 90-
and 65-nm PD/SOI technology shows improved
stability and yield, and voltage scalability due to the
elimination of half-select disturb with comparable
access times as that of 6T-based designs.
VIII. Acknowledgment
We sincerely thank Mr. C. Chandrasekhar,
HOD ECE, SVCET, Mr. Lokesh Krishna, Associate
Professor, SVCET, Mr. L.Rama Murthy HOD ECE,
Vemu IT, Chittoor, and the Staff members of ECE
Dept, SVCET, family members, and friends, one and
all who helped us to make this paper successful.
References
[1] R. Joshi, S. Mukhopadhyay, D. W. Plass,
Y. H. Chan, C.-T. Chan, and A. Devgan,
“Variability analysis for sub-100 nm
PD/SOI CMOS SRAM cell,” in Proc. 30th
Eur. Solid-State Circuits Conf., Sep. 2004,
pp. 211–214.
[2] L. Itoh, K. Osada, and T. Kawahara,
“Reviews and future prospects of low
voltage embedded RAMs,” in Proc. IEEE
7. K.R.Surendra, K.Venkatramana Reddy / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.193-199
199 | P a g e
Custom Integr. Circuits Conf., 2004, pp.
339–344.
[3] K. Zhang, U. Bhattacharya, Z. Chen, F.
Hamzaoglu, D. Murray, N. Vallepalli, Y.
Wang, B. Zheng, and M. Bohr, “3-GHz 70
MB SRAM in 65 nm CMOS technology
with integrated column-based dynamic
power supply,” in ISSCC Dig. Tech.
Papers, Feb. 2005, pp. 474–475.
[4] M. Kellah, Y. Yibin, S. K. Nam, D.
Somasekhar, G. Pandya, A. Farhang, K.
Zhang, C. Webb, and V. De, “Wordline &
bitline pulsing schemes for improving
SRAM cell stability in low-Vcc 65 nm
CMOS designs,” in Proc. VLSI Circuits
Symp., 2006, pp. 9–10.
[5] V. Ramadurai, R. Joshi, and R. Kanj, “A
disturb decoupled column select 8T SRAM
cell,” in Proc. CICC, 2007, pp. 25–28.
[6] W. Henkels, W. Hwang, R. Joshi, and A.
Williams, “Provably correct storage
arrays,” U.S. Patent 6 279 144, Aug. 21,
2001.
[7] L. Chang, D. M. Fried, J. Hergenrother, J.
W. Sleight, R. H. Dennard, R. K. Montoye,
L. Sekaric, S. J. McNab, A. W. Topol, C.
D. Adams, K. W. Guarini, and W. Haensch,
“Stable SRAM cell design for the 32 nm
node and beyond,” in Proc. IEEE Symp.
VLSI Technol., 2005, pp. 128–129.
[8] R. Joshi, “Random access memory with
stability enhancement and early ready
elimination,” U.S. Patent Appl.
A1/20060250860, Nov. 9, 2006.
[9] R. Joshi, Y. Chan, D. Plass, T. Charest, R.
Freese, R. Sautter,W. Huott, U. Srinivasan,
D. Rodko, P. Patel, P. Shephard, and
T.Werner, “A low power and high
performance SOI SRAM circuit design
with improved cell stability,” in Proc. SOI
Conf., Oct. 2006, pp. 4–7.
[10] H. Pilo, J. Barwin, G. Braceras, C.
Browning, S. Burns, J. Gabric, S.
Lamphier, M. Miller, A. Roberts, and F.
Towler, “An SRAM design in 65 nm and
45 nm technology nodes featuring read and
write-assist circuits to expand operating
voltage,” in Proc. Symp. VLSI Circuits, Jun.
2006, pp. 15–16.
[11] C. Wann, R. Wong, D. J. Frank, R. Mann,
S.-B. Ko, P. Croce, D. Lea, D. Hoyniak, Y.-
M. Lee, J. Toomey, M. Weybright, and J.
Sudijono, “SRAM cell design for stability
methodology,” in Proc. IEEE VLSI-TSA
Int. Symp. VLSI Technol., 2005, pp. 21–22.
[12] R. Kanj, R. Joshi, and S. Nassif, “Mixture
importance sampling and its application to
the analysis of SRAM designs in the
presence of rare failure events,” in Proc.
Des. Autom. Conf., Jul. 2006, pp. 69–72.
ABOUT AUTHORS
1. Mr.K.R.Surendra received Diploma
degree from Dr. Y.C.James Yen Rural Polytechnic
College, Kuppam, Chittoor Dist, A.P, India and the
B.Tech degree from SVPCET, Puttur, Chittoor Dist,
A.P, and India. He worked as Asst. Professor in Vemu
Institute of Technology during 2010-11. His
interested areas are Communications, VLSI and
Electronics.
2. Mr.K.Venkataramana Reddy received
B.Tech Degree from MITS, Madanapalli, Chittoor,
A.P, India and M.Tech from R.V.C.E, Bangalore, and
Karnataka, India. His interested areas are digital
electronics and VLSI. He has co-authored for several
Conference Papers. He thought several subjects for
under graduate and post graduate students.