A Translation Lookaside Buffer (TLB) is a memory cache that improves access speed by storing recent translations of virtual memory to physical addresses, which helps avoid multiple memory accesses. It operates by checking for virtual page numbers, resulting in either a TLB hit (found in cache) or a TLB miss (not found, requiring additional lookups). Handling TLB misses can involve either hardware or software methods to retrieve the necessary data and manage page faults effectively.

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TLB
(Translation Lookaside Buffer)
Group Member:
 Zara
 Zainab Khalid

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Contents
● What is Translation Look aside Buffer?
● What is the purpose of TLB?
● Structure of TLB
● Working of TLB
● TLB miss handling
● Handling page faults

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What is Translation Look aside
Buffer?
● A translation lookaside buffer (TLB) is a memory cache that
stores recent translations of virtual memory to physical
addresses for faster retrieval.
● The translation look aside buffer (TLB) is a cache for page table
entries.
● The TLB stores the recent translations of virtual memory to
physical memory and can be called an address-translation
cache.

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What is the purpose of TLB?
● A translation lookaside buffer is a special high-speed cache for
page table entries to overcame that every virtual memory
reference can cause two physical memory access: one to fetch
the appropriate page table entry and one to fetch the desired
data.
● is used to reduce the time taken to access a user memory
location. It is a part of the chip's memory-management unit
(MMU).

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Working of TLB
● The TLB works as follows. On a virtual memory access, the
CPU searches the TLB for the virtual page number of the page
that is being accessed, an operation known as TLB lookup.
● If a TLB entry is found with a matching virtual page number,
a TLB hit occurred and the CPU can go ahead and use the
PTE(page table entry) stored in the TLB entry to calculate the
target physical address.
● If a TLB entry is not found with a matching virtual page
number, a TLB miss occurred and the CPU can go ahead and
search it from the page table to calculate the target physical
address.

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Structure of TLB

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TLB miss handling:
● TLB miss and, depending on the CPU architecture, is handled in
one of two ways:
● Hardware TLB miss handling:
● Software TLB miss handling:

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Hardware TLB miss handling:
● With hardware TLB management, the CPU automatically
walks the page tables to see if there is a valid page table entry
for the specified virtual address.
● If an entry exists, it is brought into the TLB and the TLB
access is retried: this time the access will hit, and the program
can proceed normally. If the CPU finds no valid entry for the
virtual address in the page tables, it raises a page
fault exception, which the operating system must handle.

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Handling page faults
● Handling page faults usually involves bringing
the requested data into physical memory,
setting up a page table entry to map the
faulting virtual address to the correct physical
address, and resuming the program. With a
hardware-managed TLB, the format of the
TLB entries is not visible to software, and can
change from CPU to CPU without causing loss
of compatibility for the programs.

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Software TLB miss handling:
● In this case, the CPU simply raises a TLB miss fault. The fault
is intercepted by the operating system, which invokes the TLB
miss handler in response.
● With software-managed TLBs, a TLB miss generates a "TLB
miss" exception, and operating system code is responsible for
walking the page tables and performing the translation in
software. The operating system then loads the translation into
the TLB and restarts the program from the instruction that
caused the TLB miss.
● If the PTE is not found, control is handed over to the page
fault handler.

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