The document discusses two primary methods of control unit design: hardwired and microprogrammed implementations. Hardwired control units use state machine circuits with combinational logic for generating control signals, offering speed but lacking flexibility and ease of modification. Microprogrammed control units utilize sequences of micro-instructions stored in control memory, enabling easier updates and additions to control logic, structured around microinstructions and control signals generation.

1. CONTROL UNIT
DESIGN
CONTROL UNIT
DESIGN
By Prof. Vinit Raut

2. Introduction
• To execute instructions, the processor must have some
means of generating the control signals needed in the
proper sequence.
• A wide variety of techniques have been used for control
unit implementation. Most of these fall into one of two
categories:
1. Hardwired implementation
 control unit is essentially a state machine circuit
2. Microprogrammed implementation
 micro-instructions are stored in control memory
• To execute instructions, the processor must have some
means of generating the control signals needed in the
proper sequence.
• A wide variety of techniques have been used for control
unit implementation. Most of these fall into one of two
categories:
1. Hardwired implementation
 control unit is essentially a state machine circuit
2. Microprogrammed implementation
 micro-instructions are stored in control memory

3. Hardwired Control Unit
CLK
Clock
Control step
counter
inputs
External
Figure 7.10 Control unit organization.
IR
encoder
Decoder/
Control signals
codes
inputs
Condition

4. • The decoder/encoder is a combinational circuit that generates a
set of required control signals.
• A control step counter is used to keep track of the control steps.
• Each count of this counter corresponds to one control step.
• The required control signals are determined by the following
information:
1. contents of the control step counter
2. contents of IR register
3. contents of the condition code flags
4. External input signals, like MFC and interrupt request.
Hardwired Control Unit
• The decoder/encoder is a combinational circuit that generates a
set of required control signals.
• A control step counter is used to keep track of the control steps.
• Each count of this counter corresponds to one control step.
• The required control signals are determined by the following
information:
1. contents of the control step counter
2. contents of IR register
3. contents of the condition code flags
4. External input signals, like MFC and interrupt request.

5. Detailed Block DescriptionExternal
inputs
Figure 7.11. Separation of the decoding and encoding functions.
Encoder
Reset
CLK
Clock
Control signals
counter
Run End
Condition
codes
decoder
Instruction
Step decoder
Control step
IR
T1 T2 Tn
INS1
INS2
INSm
External
inputs
Figure 7.11. Separation of the decoding and encoding functions.
Encoder
Reset
CLK
Clock
Control signals
counter
Run End
Condition
codes
decoder
Instruction
Step decoder
Control step
IR
T1 T2 Tn
INS1
INS2
INSm

6. • The step decoder generate a separate clock signal for each step, or
time slot, in the control sequence.
• The instruction decoder decodes the instruction loaded in IR.
• The output of the instruction decoder consists of a separate line for
each of the ‘m’ machine instruction.
• According to the code in the IR, only one line amongst all output
lines of decoder is set to 1 and all other lines are set to 0.
• The input signals to encoder are combined to generate the
individual control signals like add, read, etc.
• The End signal starts the a new instruction fetch cycle by resetting
the control step counter to its starting value.
• When run=1, the counter to be incremented by one at the end of
every clock cycle.
• When run=0, the counter stops counting and this is needed
whenever the WMFC signal is activated.
Detailed Block Description
• The step decoder generate a separate clock signal for each step, or
time slot, in the control sequence.
• The instruction decoder decodes the instruction loaded in IR.
• The output of the instruction decoder consists of a separate line for
each of the ‘m’ machine instruction.
• According to the code in the IR, only one line amongst all output
lines of decoder is set to 1 and all other lines are set to 0.
• The input signals to encoder are combined to generate the
individual control signals like add, read, etc.
• The End signal starts the a new instruction fetch cycle by resetting
the control step counter to its starting value.
• When run=1, the counter to be incremented by one at the end of
every clock cycle.
• When run=0, the counter stops counting and this is needed
whenever the WMFC signal is activated.

7. • Advantages of Hardwired Control Unit:
1. Fast because control signals are generated by combinational
circuits.
2. The delay in generation of control signals depends upon the
number of gates.
• Disadvantages of Hardwired Control Unit:
1. More the control signals required by CPU, more complex will
be the design of control unit.
2. No Flexibility. Modification in control signal is very difficult i.e. it
requires rearranging of wires in the hardware circuit.
3. Difficult to add new feature in existing design of control unit.
Hardwired Control Unit
• Advantages of Hardwired Control Unit:
1. Fast because control signals are generated by combinational
circuits.
2. The delay in generation of control signals depends upon the
number of gates.
• Disadvantages of Hardwired Control Unit:
1. More the control signals required by CPU, more complex will
be the design of control unit.
2. No Flexibility. Modification in control signal is very difficult i.e. it
requires rearranging of wires in the hardware circuit.
3. Difficult to add new feature in existing design of control unit.

8. Hardwired Control Unit Design
Methods
1. State-table Method
2. Delay-element Method
 Uses clocked delay element (D-Flip Flop)
3. Sequence-counter Method
 Uses counter for timing purposes
4. PLA Method
 Uses programmable logic array
1. State-table Method
2. Delay-element Method
 Uses clocked delay element (D-Flip Flop)
3. Sequence-counter Method
 Uses counter for timing purposes
4. PLA Method
 Uses programmable logic array

9. • Let us consider 2’s complement multiplier control circuit
for illustration.
Hardwired Control Unit Design
Methods (cont.)

10. Hardwired Control Unit Design
Methods (cont.)
Multiplier control circuit with control signals

11. Hardwired Control Unit Design
Methods (cont.)
Control signals for 2’s complement multiplier

12. State-table Method
• Classical method of sequential circuit design.
• Attempts to minimize the amount of hardware.
• It starts with the construction of state transition table. In
every state the control unit generates a set of control
signals.
• Control unit transmits from one state to another state
depending on its:
1. Current state Ij
2. Input to the controller
• The state Si (i=1,2…)
has been marked above
each block of the flowchart.
• Classical method of sequential circuit design.
• Attempts to minimize the amount of hardware.
• It starts with the construction of state transition table. In
every state the control unit generates a set of control
signals.
• Control unit transmits from one state to another state
depending on its:
1. Current state Ij
2. Input to the controller
• The state Si (i=1,2…)
has been marked above
each block of the flowchart.

13. State-table Method (cont.)
• State Assignment: States are assigned as
S1,S2,S3…;each such assignment specifies a particular
state of the controller at the specific time step. State
table derived from state assignment
• State Minimization: A set of states {Sa,Sb,…Sc} can be
merged to a single state S’ if Si & Sj is pair wise
compatible
• State Encoding: State variables are defined and states
are encoded in terms of state variables
• State Assignment: States are assigned as
S1,S2,S3…;each such assignment specifies a particular
state of the controller at the specific time step. State
table derived from state assignment
• State Minimization: A set of states {Sa,Sb,…Sc} can be
merged to a single state S’ if Si & Sj is pair wise
compatible
• State Encoding: State variables are defined and states
are encoded in terms of state variables

14. State-table Method (cont.)
• 2’s complement multiplier
• State table construction is necessary.
• Associate a state with every micro-operation block giving nine
states from S0 through S8.
• There are four primary input signals BEGIN, COUNT, Q0 and Q-1,
so sixteen possible input combinations.
• Each entry in the table indicates next state followed by list of
control signals that are activated.
• Note:
• 2’s complement multiplier
• State table construction is necessary.
• Associate a state with every micro-operation block giving nine
states from S0 through S8.
• There are four primary input signals BEGIN, COUNT, Q0 and Q-1,
so sixteen possible input combinations.
• Each entry in the table indicates next state followed by list of
control signals that are activated.
• Note:

15. State-table Method (cont.)
Flowchart for 2’s complement multiplication

16. State-table Method (cont.)

17. State-table Method (cont.)

18. State-table Method (cont.)
State table for multiplier control unit

19. State-table Method (cont.)
State table for multiplier control unit (cont.)

20. Delay-element Method
• Control signals or groups of control signals are activated
in proper sequence.
• There is a specific time delay between activation of two
consecutive control signals or groups of control signal.
• For synchronous operation, delay elements are
implemented using D flip-flops and controlled by
common clock signal.
• Control signals or groups of control signals are activated
in proper sequence.
• There is a specific time delay between activation of two
consecutive control signals or groups of control signal.
• For synchronous operation, delay elements are
implemented using D flip-flops and controlled by
common clock signal.

21. Rules for Delay-element Method
1. Each sequence of two successive micro-operations
requires a delay element.

22. Rules for Delay-element Method
(cont.)
2. The signals that are intended to activate same control
lines are logically ORed to get one common output
signals.

23. Rules for Delay-element Method
(cont.)
3. n lines in the flowchart
merge to a common line
are transformed into n
input OR gate.
4. A decision box can be
implemented by two
AND gates as shown in
figure b
Figure a
3. n lines in the flowchart
merge to a common line
are transformed into n
input OR gate.
4. A decision box can be
implemented by two
AND gates as shown in
figure b
Figure a
Figure b

24. Controller specification for the
Fetch Sequence
• Address of next instruction is in PC (S01)
• Content of PC loaded into MAR (C01), S02
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MDR (C02), S03
• PC incremented by 1 (in parallel with data fetch from
memory) (C03), S03
• Data (instruction) moved from MDR to IR (C04), S04
• MDR is now free for further data fetches (F 0 ; E 1)
(C05), S05
• Address of next instruction is in PC (S01)
• Content of PC loaded into MAR (C01), S02
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MDR (C02), S03
• PC incremented by 1 (in parallel with data fetch from
memory) (C03), S03
• Data (instruction) moved from MDR to IR (C04), S04
• MDR is now free for further data fetches (F 0 ; E 1)
(C05), S05

25. Delay-element Method (cont.)
• Control unit based on delay element method for the
fetch cycle

26. Delay-element Method (cont.)
• Implementation of multiplier control unit from flowchart
by using transformation rules

27. Delay-element Method (cont.)
Multiplier control unit using delay elements

28. Delay-element Method (cont.)
Multiplier control unit using delay elements (cont.)

29. Sequence-counter Method
• Step 1: Identify the distinct phases in the flowchart. Employ log p
number of flip flops to handle p number distinct phases
R
S
1
0 Reset
Begin
End
Modulo–k
counter
Count
enable
……
…..
S 0 ResetEnd
Clock
Reset
Modulo–k
counter
I/k Decoder
c1c2 ck
Step 2: Identify the maximum number of distinct
steps, k, in each of the phases. Employ a mod k
counter to generate control signals for each of the
k steps
Step 3 : design a combinational logic circuit to
generate the sequence of control signals to
control the micro operations of each phase
Reset
Enable

30. Sequence-counter Method

31. Sequence-counter Method
Flowchart for 2’s complement multiplication

32. Sequence-counter Method
Flowchart for 2’s complement multiplication (cont.)

33. Sequence-counter Method
Flowchart for 2’s complement multiplication (cont.)

34. Sequence-counter Method

35. Sequence-counter Method
Multiplier control unit using Sequence counter method

36. Sequence-counter Method

37. Sequence-counter Method

38. Microprogrammed Control Unit
• Control signals are generated by a program similar to
machine language programs.
• Sequence of control steps required to perform
ADD (R3),R1 operations are

39. Microprogrammed Control Unit
• Control Word(CW):
A word where individual bits represents the various control signals.
• Microroutine:
A sequence of CWs corresponding to the control sequence of a
machine instruction.
• Microinstruction:
The individual control word in microroutine.
• Control Store:
The microroutine for all instructions in instruction set of a computer
are stored in a special memory called control store.
• Control Word(CW):
A word where individual bits represents the various control signals.
• Microroutine:
A sequence of CWs corresponding to the control sequence of a
machine instruction.
• Microinstruction:
The individual control word in microroutine.
• Control Store:
The microroutine for all instructions in instruction set of a computer
are stored in a special memory called control store.

40. Microinstructions
• Each line in microroutine/microprogram describes a set
of micro-operations occurring at one time and is known
as a microinstruction.
• Different formats of microinstruction depending on the
encoding of control signals.
1. Horizontal microinstructions
2. Vertical microinstructions
• Each line in microroutine/microprogram describes a set
of micro-operations occurring at one time and is known
as a microinstruction.
• Different formats of microinstruction depending on the
encoding of control signals.
1. Horizontal microinstructions
2. Vertical microinstructions

41. Horizontal Microinstructions
• Each bit directly controls each micro-operation
or each control signal.
• A Horizontal microinstruction has the following
general attributes:
 long microinstruction word
 high degree of parallelism
 little encoding of control information
• Each bit directly controls each micro-operation
or each control signal.
• A Horizontal microinstruction has the following
general attributes:
 long microinstruction word
 high degree of parallelism
 little encoding of control information

42. Horizontal Microinstructions

43. Horizontal Microinstructions
Execution of horizontal microinstruction
Turn on all control lines with bit value equal to 1
If the condition bit is If the condition bit is
False True
Execute the next Next microinstruction to be
microinstruction in executed is indicated in the
the sequence. address field.
Execution of horizontal microinstruction
Turn on all control lines with bit value equal to 1
If the condition bit is If the condition bit is
False True
Execute the next Next microinstruction to be
microinstruction in executed is indicated in the
the sequence. address field.

44. Vertical Microinstructions
• A Vertical microinstruction has the following
general attributes:
 short microinstruction word
 limited ability to express parallel micro-
operations
 considerable encoding of the control
information
• A Vertical microinstruction has the following
general attributes:
 short microinstruction word
 limited ability to express parallel micro-
operations
 considerable encoding of the control
information

45. Vertical Microinstructions

46. Vertical Microinstructions
• Many similar control signals can be encoded into
few microinstruction bits.
• For example, for 32 ALU operations, only 5
encoded bits will be required in vertical
microinstruction.
• However, these encoded bits need to be passed
from respective decoders to get the individual
control signals.
• Many similar control signals can be encoded into
few microinstruction bits.
• For example, for 32 ALU operations, only 5
encoded bits will be required in vertical
microinstruction.
• However, these encoded bits need to be passed
from respective decoders to get the individual
control signals.

47. Figure 7.16. Basic organization of a microprogrammed control unit.
store
Control
generator
Starting
address
CW
Clock µPC
IR
Basic Organization of Micro
programmed Control Unit
Figure 7.16. Basic organization of a microprogrammed control unit.
store
Control
generator
Starting
address
CW
Clock µPC
IR

48. Basic Organization of Micro
programmed Control Unit
Figure 7.16. Basic organization of a microprogrammed control unit.
store
Control
generator
Starting
address
CW
Clock µPC
IR
Key elements of control unit microarchitecture are
• Control memory- stores set of microinstructions.
• Control address register- contains the address of the
next microinstruction to be read.
• Control buffer register- contains microinstruction after
reading it from control memory.
• reading a microinstruction from the control memory is
the same as executing that microinstruction.
• Sequencing unit- loads the control address register and
issues a read command.
Figure 7.16. Basic organization of a microprogrammed control unit.
store
Control
generator
Starting
address
CW
Clock µPC
IR
Key elements of control unit microarchitecture are
• Control memory- stores set of microinstructions.
• Control address register- contains the address of the
next microinstruction to be read.
• Control buffer register- contains microinstruction after
reading it from control memory.
• reading a microinstruction from the control memory is
the same as executing that microinstruction.
• Sequencing unit- loads the control address register and
issues a read command.

49. Functioning of Microprogrammed
Control Unit

50. The control unit functions as follows:
1. To execute an instruction, the sequencing logic unit issues a
READ command to the control memory.
2. The word whose address is specified in the control address
register is read into the control buffer register.
3. The content of the control buffer register generates control
signals and next address information for the sequencing logic
unit.
4. The sequencing logic unit loads a new address into the
control address register based on the next-address
information from the control buffer register and the ALU flags.
All this happens during one clock pulse.
Functioning of Microprogrammed
Control Unit
The control unit functions as follows:
1. To execute an instruction, the sequencing logic unit issues a
READ command to the control memory.
2. The word whose address is specified in the control address
register is read into the control buffer register.
3. The content of the control buffer register generates control
signals and next address information for the sequencing logic
unit.
4. The sequencing logic unit loads a new address into the
control address register based on the next-address
information from the control buffer register and the ALU flags.
All this happens during one clock pulse.

51. The 4th step elaboration. Depending on the value of the
ALU flags and the control buffer register, one of three
decisions is made:
• Get the next instruction: Add 1 to the control address
register.
• Jump to a new routine based on a jump microinstruction:
Load the address field of the control buffer register into
the control address register.
• Jump to a machine instruction routine: Load the control
address register based on the opcode in the IR.
Functioning of Microprogrammed
Control Unit
The 4th step elaboration. Depending on the value of the
ALU flags and the control buffer register, one of three
decisions is made:
• Get the next instruction: Add 1 to the control address
register.
• Jump to a new routine based on a jump microinstruction:
Load the address field of the control buffer register into
the control address register.
• Jump to a machine instruction routine: Load the control
address register based on the opcode in the IR.

52. • Microprogram was coined by Wilkes in the early
1950s
• 1951 – Wilkes first proposed microprogrammed
control
• Matrix partially filled with diodes
• During cycle, one row activated
 Generates signals where diode present
 First part of row generates control
 Second generates address for next cycle
Wilkes Control
• Microprogram was coined by Wilkes in the early
1950s
• 1951 – Wilkes first proposed microprogrammed
control
• Matrix partially filled with diodes
• During cycle, one row activated
 Generates signals where diode present
 First part of row generates control
 Second generates address for next cycle

53. Wilkes's Microprogrammed
Control Unit

54. Microprogrammed control unit
• Advantages:
1. It simplifies the design of control unit. Thus it is both, cheaper and less
error prone to implement.
2. Control functions are implemented in software rather than hardware.
3. More flexible, can be changed to accommodate new system
specification or to correct design error.
4. Debugging and maintenance of a microprogrammed CPU is easy.
• Disadvantages:
1. Slower than the hardwired control unit, because time is required to
access the microinstruction from control store.
2. The flexibility is achieved at some extra hardware cost due to the
control memory and its access circuitry.
3. The design duration of microprogrammed control unit is more than
hardwired control unit for smaller CPU.
• Advantages:
1. It simplifies the design of control unit. Thus it is both, cheaper and less
error prone to implement.
2. Control functions are implemented in software rather than hardware.
3. More flexible, can be changed to accommodate new system
specification or to correct design error.
4. Debugging and maintenance of a microprogrammed CPU is easy.
• Disadvantages:
1. Slower than the hardwired control unit, because time is required to
access the microinstruction from control store.
2. The flexibility is achieved at some extra hardware cost due to the
control memory and its access circuitry.
3. The design duration of microprogrammed control unit is more than
hardwired control unit for smaller CPU.

55. Comparison between Hardwired and
Microprogrammed Control Unit
Sr. No Attribute Hardwired Microprogrammed
1 Speed Fast Slow
2 Cost of
implementation
More Cheaper
3 Implementation
approach
Sequential circuit Programming
4 Flexibility Not flexible Flexible
5 Ability to handle
complex instruction
Difficult Easier
6 Design process Complicated Systematic
7 Decoding and
sequencing logic
Complex Easy
8 Application RISC µp CISC µp
9 Control memory Absent Present
10 Chip area Less more

56. Microinstruction Sequencing
• Two basic tasks performed by a
microprogrammed control unit are:
• Microinstruction sequencing: Get the next
microinstruction from the control memory.
• Microinstruction execution: Generate the control
signals needed to execute the microinstruction.
• Two basic tasks performed by a
microprogrammed control unit are:
• Microinstruction sequencing: Get the next
microinstruction from the control memory.
• Microinstruction execution: Generate the control
signals needed to execute the microinstruction.

57. Microinstruction Sequencing:
Design Considerations
• Size of the microinstruction
• The address-generation time
• The address of the next microinstruction to be
executed is in one of these categories:
• Determined by instruction register
• Next sequential address
• Branch
• Size of the microinstruction
• The address-generation time
• The address of the next microinstruction to be
executed is in one of these categories:
• Determined by instruction register
• Next sequential address
• Branch

58. Microinstruction Sequencing:
Sequencing Techniques
• Based on the current microinstruction, condition
flags, and the contents of the instruction register,
a control memory address must be generated
for the next microinstruction.
• Three general categories (based on the format
of the address information) are:
• Two address fields
• Single address field
• Variable format
• Based on the current microinstruction, condition
flags, and the contents of the instruction register,
a control memory address must be generated
for the next microinstruction.
• Three general categories (based on the format
of the address information) are:
• Two address fields
• Single address field
• Variable format

59. Microinstruction
Sequencing:
Sequencing
Techniques
• Two address fields• Two address fields

60. Microinstruction
Sequencing:
Sequencing
Techniques
• Single address field• Single address field

61. Microinstruction
Sequencing:
Sequencing
Techniques
• Variable format• Variable format

62. Microinstruction Execution
• The cycle is the basic event
• Each cycle is made up of two events
 Fetch
 Determined by generation of microinstruction
address
 Execute
• Effect is to generate control signals
• Some control points internal to processor
• Rest go to external control bus or other
interface
• The cycle is the basic event
• Each cycle is made up of two events
 Fetch
 Determined by generation of microinstruction
address
 Execute
• Effect is to generate control signals
• Some control points internal to processor
• Rest go to external control bus or other
interface

63. Control Unit
Organization
• Revised version of
Figure 16.4

64. A Taxonomy of Microinstructions
• Vertical/horizontal
• Packed/unpacked
• Hard/soft microprogramming
• Direct/indirect encoding
• Vertical/horizontal
• Packed/unpacked
• Hard/soft microprogramming
• Direct/indirect encoding

65. A Taxonomy of Microinstructions
• The control signal portion of the microinstruction format
falls on a spectrum.

66. Improvements over Wilkes
• Wilkes had each bit directly produced a control
signal or directly produced one bit of next
address
• More complex address sequencing schemes,
using fewer microinstruction bits, are possible
• Require more complex sequencing logic module
• Control word bits can be saved by encoding and
subsequently decoding control information
• Wilkes had each bit directly produced a control
signal or directly produced one bit of next
address
• More complex address sequencing schemes,
using fewer microinstruction bits, are possible
• Require more complex sequencing logic module
• Control word bits can be saved by encoding and
subsequently decoding control information

67. How to Encode
• K different internal and external control signals
• Wilkes’s:
 K bits dedicated
 2K control signals during any instruction cycle
• Not all used
 Two sources cannot be gated to same destination
 Register cannot be source and destination
 Only one pattern presented to ALU at a time
 Only one pattern presented to external control bus at a time
• Require Q < 2K which can be encoded with log2Q < K bits
• Not done
 As difficult to program as pure decoded (Wilkes) scheme
 Requires complex slow control logic module
• Compromises
 More bits than necessary used
 Some combinations that are physically allowable are not
possible to encode
• K different internal and external control signals
• Wilkes’s:
 K bits dedicated
 2K control signals during any instruction cycle
• Not all used
 Two sources cannot be gated to same destination
 Register cannot be source and destination
 Only one pattern presented to ALU at a time
 Only one pattern presented to external control bus at a time
• Require Q < 2K which can be encoded with log2Q < K bits
• Not done
 As difficult to program as pure decoded (Wilkes) scheme
 Requires complex slow control logic module
• Compromises
 More bits than necessary used
 Some combinations that are physically allowable are not
possible to encode

68. Specific Encoding Techniques
• Microinstruction organized as set of fields
• Each field contains code
• Activates one or more control signals
• Organize format into independent fields
 Field depicts set of actions (pattern of control signals)
 Actions from different fields can occur simultaneously
• Alternative actions that can be specified by a
field are mutually exclusive
 Only one action specified for field could occur at a
time
• Microinstruction organized as set of fields
• Each field contains code
• Activates one or more control signals
• Organize format into independent fields
 Field depicts set of actions (pattern of control signals)
 Actions from different fields can occur simultaneously
• Alternative actions that can be specified by a
field are mutually exclusive
 Only one action specified for field could occur at a
time

69. Microinstruction Encoding
Direct Encoding

70. Microinstruction Encoding
Indirect Encoding

71. Applications of
Microprogramming
• Realization of computers
• Emulation
• Operating system support
• Realization of special purpose devices
• High-level language support
• Microdiagnostics
• User tailoring
• Realization of computers
• Emulation
• Operating system support
• Realization of special purpose devices
• High-level language support
• Microdiagnostics
• User tailoring

72. Introduction to RISC and CISC
Architectures [Not mentioned in Syllabus]
• CISC Architecture
• RISC Architecture
 Pipelining
• RISC vs CISC
• CISC Architecture
• RISC Architecture
 Pipelining
• RISC vs CISC

73. What is CISC?
• Complex Instruction Set Computer
• “High level” Instruction Set
 Executes several “low level operations”
 Ex: load, arithmetic operation, memory store
• Complex Instruction Set Computer
• “High level” Instruction Set
 Executes several “low level operations”
 Ex: load, arithmetic operation, memory store

74. Features of CISC
• Instruction set with multiple instructions
• Instructions can operate directly on memory
• Variable instruction/data formats
• Small number of general purpose registers
• Instructions take multiple clocks to execute
• Few lines of code per operation
• A large number of addressing modes
• High dependency of microprogram
• Instruction set with multiple instructions
• Instructions can operate directly on memory
• Variable instruction/data formats
• Small number of general purpose registers
• Instructions take multiple clocks to execute
• Few lines of code per operation
• A large number of addressing modes
• High dependency of microprogram

75. What is RISC?
• Reduced Instruction Set Computer
• RISC is a CPU design that recognizes
only a limited number of instructions
 Simple instructions
 Instructions are executed quickly
• Reduced Instruction Set Computer
• RISC is a CPU design that recognizes
only a limited number of instructions
 Simple instructions
 Instructions are executed quickly

76. Features of RISC
• “Reduced” instruction set
• Only the load and store instructions operate directly onto
memory
• Simple instruction formats
• Incorporates a large number of general registers for arithmetic
operations to avoid storing variables on a stack in memory
• Instructions are executed within one clock cycle
• Executes a series of simple instruction instead of a complex
instruction
• Very few addressing modes
• Hardwired control unit for sequencing of microinstructions
• Pipelining = speed
• “Reduced” instruction set
• Only the load and store instructions operate directly onto
memory
• Simple instruction formats
• Incorporates a large number of general registers for arithmetic
operations to avoid storing variables on a stack in memory
• Instructions are executed within one clock cycle
• Executes a series of simple instruction instead of a complex
instruction
• Very few addressing modes
• Hardwired control unit for sequencing of microinstructions
• Pipelining = speed

77. Role of Compiler: RISC vs.
CISC
• CISC instruction:
MUL <addr1>, <addr2>
• RISC instructions:
LOAD A, <addr1>
LOAD B, <addr2>
MUL A, B
STORE <addr1>
• RISC is dependent on optimizing compilers
• CISC instruction:
MUL <addr1>, <addr2>
• RISC instructions:
LOAD A, <addr1>
LOAD B, <addr2>
MUL A, B
STORE <addr1>
• RISC is dependent on optimizing compilers

78. RISC Pipelining
• Most instructions are register to register
• Two phases of execution
 I: Instruction fetch
 E: Execute
 ALU operation with register input and output
• For load and store
 I: Instruction fetch
 E: Execute
 Calculate memory address
 D: Memory
 Register to memory or memory to register operation
• Most instructions are register to register
• Two phases of execution
 I: Instruction fetch
 E: Execute
 ALU operation with register input and output
• For load and store
 I: Instruction fetch
 E: Execute
 Calculate memory address
 D: Memory
 Register to memory or memory to register operation

79. Effects of Pipelining

80. Thank youThank you