The document provides an overview of the Translation Lookaside Buffer (TLB), which acts as a cache for page table entries to simplify the process of translating linear addresses to physical addresses. It explains the function of the TLB, including its structure, how it works with content addressable memory, and the costly page walk process involved when a TLB miss occurs. The TLB optimizes memory access by storing recently accessed entries, enhancing performance through locality of reference.

1. A
Presentation
On
“Translation lookaside buffer”

2. Content
a. What is Translational look aside buffer.
b. Use of Translational look aside buffer.
c. How it works.
d. Content addressable memory (CAM)
e. Page walk.
f. Structure of TLB.

3. What is Translational look aside
buffer (t. l. b)
The translation look aside buffer (TLB) is a cache for
page table entries. It works in much the same way as
the data cache: it stores recently accessed page table
entries. It also relies on locality of reference

4. use of t. l. b
It is cumbersome and time consuming to calculate the
physical address from linear address for every memory
location. A Translation Look-aside Buffer (TLB)
simplifies the process. TLB is a page table cache, which
stores the 32 recently accessed page table entries.

5. how it work’s
The paging unit receives a 32-bit linear address from
the segmentation unit. The upper 20 bits of the linear
address is compared with all 32-entries in the
translation look-aside buffer (TLB) to check if it
matches with any of the entries. If it matches, the 32-
bit physical address is calculated from matching TLB
entry and placed on the address bus.

6. Content addressable memory and
page walk
The TLB is sometimes implemented as content-addressable
memory (CAM). The CAM search key is
the virtual address and the search result is a physical
address. If the requested address is present in the TLB,
the CAM search yields a match quickly and the
retrieved physical address can be used to access
memory. This is called a TLB hit. If the requested
address is not in the TLB, it is a miss, and the
translation proceeds by looking up the page table in a
process called a page walk.

7. Page walk
The page walk is an expensive process, as it involves
reading the contents of multiple memory locations
and using them to compute the physical address. After
the physical address is determined by the page walk,
the virtual address to physical address mapping is
entered into the TLB.

9. Structure of TLB
TLB has 4 sets of eight entries each. Each entry
consists of a TAG and a DATA. Tags are 24 bit wide.
They contain 20 upper bits of linear address, a valid bit
and three attribute bits. The Data portion of each
entry contains higher 20 bits of the Physical address.