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Assembly Language x86 Family Architecture Motaz K. Saad Spring 2007 Motaz K. Saad, Dept. of CS
Overview ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
General Concepts ,[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Basic Microcomputer Design ,[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Motaz K. Saad, Dept. of CS Processor Control  Unit Arithmetic  Logic Unit (ALU) Arithmetic  Logic Unit (ALU) Input Devices Storage Devices Output Devices Memory Data Information Instructions Data Information Instructions Data Information Control  Unit
Motaz K. Saad, Dept. of CS
Clock ,[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
What's Next ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Instruction Execution Cycle ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Cache Memory ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
How a Program Runs Motaz K. Saad, Dept. of CS
Multitasking ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
IA-32 Processor Architecture ,[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Modes of Operation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Basic Execution Environment ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Addressable Memory ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
X86 General-Purpose Registers Named storage locations inside the CPU, optimized for speed. Motaz K. Saad, Dept. of CS
Accessing Parts of Registers ,[object Object],[object Object],Motaz K. Saad, Dept. of CS
Index and Base Registers ,[object Object],Motaz K. Saad, Dept. of CS
Some Specialized Register Uses ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Status Flags ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Intel Microprocessor History ,[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Early Intel Microprocessors ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The IBM-AT ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Intel IA-32 Family ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Intel P6 Family ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
CISC and RISC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
What's Next ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
IA-32 Memory Management ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Real-Address mode ,[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Segmented Memory ,[object Object],linear addresses one segment Motaz K. Saad, Dept. of CS
Calculating Linear Addresses ,[object Object],[object Object],Adjusted Segment value: 0 8 F 1 0 Add the offset:  0 1 0 0 Linear address:  0 9 0 1 0 Motaz K. Saad, Dept. of CS
Your turn . . . What linear address corresponds to the segment/offset address 028F:0030? 028F0 + 0030 =  02920 Always use hexadecimal notation for addresses. Motaz K. Saad, Dept. of CS
Your turn . . . What segment addresses correspond to the linear address 28F30h? Many different segment-offset addresses can produce the linear address 28F30h. For example: 28F0:0030, 28F3:0000, 28B0:0430, . . . Motaz K. Saad, Dept. of CS
Protected Mode  (1 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Protected mode  (2 of 2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
What's Next ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Components of an IA-32 Microcomputer ,[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Motherboard ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Intel D850MD Motherboard dynamic RAM  Pentium 4 socket Speaker IDE drive connectors mouse, keyboard, parallel, serial, and USB connectors AGP slot Battery Video Power connector memory controller hub Diskette connector PCI slots I/O Controller Firmware hub Audio chip Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification Motaz K. Saad, Dept. of CS
Video Output ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Sample Video Controller (ATI Corp.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Memory ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Input-Output Ports ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Input-Output Ports  (cont) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
What's Next ,[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Levels of Input-Output ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Displaying a String of Characters ,[object Object],Motaz K. Saad, Dept. of CS
ASM Programming levels ASM programs can perform input-output at each of the following levels: Motaz K. Saad, Dept. of CS
Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
More Details about X86 Family Architecture  X86 family Generations Motaz K. Saad, Dept. of CS
X86 Family ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Intel 8085 architecture : 8-bit data, 16-bit address Motaz K. Saad, Dept. of CS
Internal architecture of 8086 Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The 8086 and 80286 microprocessors. Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Internal architecture of 80386 Motaz K. Saad, Dept. of CS
Internal registers (partly) of 80386 Motaz K. Saad, Dept. of CS
[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Key features of the Pentium microprocessor. The execution unit has two pipelines allowing two instructions to be executed simultaneously. Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Pentium processor with heat sink and fan mated to a Socket 7 connector. Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The Pentium Pro is two chips in one. The larger die is the processor, the smaller a 256K L2 cache. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Superscalar Processor of Degree Three  : Pentium has three instruction decoders, and can execute 3 simul- taneous instructions. Internal Cache  : L2 cache in the same package. Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Exploded view of single-edge contact (SEC) cartridge. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
Installing the SEC cartridge into the retention mechanism. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The Celeron processor is a Pentium II without the L2 cache. Later versions, called the Celeron A, include this cache on the same silicon die with the processor. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The Pentium III microprocessor with integrated L2 cache. This chip has more than 22 million transistors. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
The AMD K7 or Athlon processor. It mates to a new proprietary socket called Slot A. (Courtesy of Advanced Micro Devices.) Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
CPUmark is a benchmark that measures the speed of the processor and its internal cache. Motaz K. Saad, Dept. of CS
[object Object],[object Object],[object Object],[object Object],[object Object],Motaz K. Saad, Dept. of CS
Winstone 98 measures the performance of a PC system running typical Windows applications. Motaz K. Saad, Dept. of CS

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The x86 Family

  • 1. Assembly Language x86 Family Architecture Motaz K. Saad Spring 2007 Motaz K. Saad, Dept. of CS
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  • 5. Motaz K. Saad, Dept. of CS Processor Control Unit Arithmetic Logic Unit (ALU) Arithmetic Logic Unit (ALU) Input Devices Storage Devices Output Devices Memory Data Information Instructions Data Information Instructions Data Information Control Unit
  • 6. Motaz K. Saad, Dept. of CS
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  • 11. How a Program Runs Motaz K. Saad, Dept. of CS
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  • 17. X86 General-Purpose Registers Named storage locations inside the CPU, optimized for speed. Motaz K. Saad, Dept. of CS
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  • 33. Your turn . . . What linear address corresponds to the segment/offset address 028F:0030? 028F0 + 0030 = 02920 Always use hexadecimal notation for addresses. Motaz K. Saad, Dept. of CS
  • 34. Your turn . . . What segment addresses correspond to the linear address 28F30h? Many different segment-offset addresses can produce the linear address 28F30h. For example: 28F0:0030, 28F3:0000, 28B0:0430, . . . Motaz K. Saad, Dept. of CS
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  • 40. Intel D850MD Motherboard dynamic RAM Pentium 4 socket Speaker IDE drive connectors mouse, keyboard, parallel, serial, and USB connectors AGP slot Battery Video Power connector memory controller hub Diskette connector PCI slots I/O Controller Firmware hub Audio chip Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification Motaz K. Saad, Dept. of CS
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  • 49. ASM Programming levels ASM programs can perform input-output at each of the following levels: Motaz K. Saad, Dept. of CS
  • 50.
  • 51. More Details about X86 Family Architecture X86 family Generations Motaz K. Saad, Dept. of CS
  • 52.
  • 53. Intel 8085 architecture : 8-bit data, 16-bit address Motaz K. Saad, Dept. of CS
  • 54. Internal architecture of 8086 Motaz K. Saad, Dept. of CS
  • 55.
  • 56.
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  • 58. The 8086 and 80286 microprocessors. Motaz K. Saad, Dept. of CS
  • 59.
  • 60. Internal architecture of 80386 Motaz K. Saad, Dept. of CS
  • 61. Internal registers (partly) of 80386 Motaz K. Saad, Dept. of CS
  • 62.
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  • 66.
  • 67. Key features of the Pentium microprocessor. The execution unit has two pipelines allowing two instructions to be executed simultaneously. Motaz K. Saad, Dept. of CS
  • 68.
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  • 70. Pentium processor with heat sink and fan mated to a Socket 7 connector. Motaz K. Saad, Dept. of CS
  • 71.
  • 72. The Pentium Pro is two chips in one. The larger die is the processor, the smaller a 256K L2 cache. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
  • 73.
  • 74. Superscalar Processor of Degree Three : Pentium has three instruction decoders, and can execute 3 simul- taneous instructions. Internal Cache : L2 cache in the same package. Motaz K. Saad, Dept. of CS
  • 75.
  • 76. Exploded view of single-edge contact (SEC) cartridge. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
  • 77. Installing the SEC cartridge into the retention mechanism. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
  • 78.
  • 79. The Celeron processor is a Pentium II without the L2 cache. Later versions, called the Celeron A, include this cache on the same silicon die with the processor. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
  • 80.
  • 81. The Pentium III microprocessor with integrated L2 cache. This chip has more than 22 million transistors. (Courtesy of Intel Corporation.) Motaz K. Saad, Dept. of CS
  • 82.
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  • 86. The AMD K7 or Athlon processor. It mates to a new proprietary socket called Slot A. (Courtesy of Advanced Micro Devices.) Motaz K. Saad, Dept. of CS
  • 87.
  • 88.
  • 89. CPUmark is a benchmark that measures the speed of the processor and its internal cache. Motaz K. Saad, Dept. of CS
  • 90.
  • 91. Winstone 98 measures the performance of a PC system running typical Windows applications. Motaz K. Saad, Dept. of CS