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Overview of ST7 8-bit Microcontrollers
The document provides an overview of ST7 8-bit microcontrollers from STMicroelectronics. It describes the ST7 portfolio, features, and peripherals. The ST7 is an 8-bit CISC core with up to 60KB program memory and 5KB RAM. It has flash memory options, a rich peripheral set including timers, serial interfaces, and USB/CAN connectivity. The document outlines the ST7 architecture and interrupt system, memory types, programming tools, and applications.
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Overview of ST7 8-bit Microcontrollers
- 1. Overview of ST7 8-bit Microcontrollers Source: STMicroelectronics
- 2. Introduction Purpose This training module provides an overview of ST7 8-bit Microcontrollers and its key features. Outline ST7 Portfolio Key Applications 8-Bit μC – General Purpose line ST7 CORE Block Diagram Introduction to different features Content 29 pages
- 3. Introduction to ST7Mainstream 8 bit microcontroller product line for STMicroelectronics. (MCU division, Automotive, Smart Card...) Industry standard 8 bit Core based on CISC architecture, easy hands on. Ideal for platform integration , core and peripheral compatibility from 1K to 60K program memory as well as compatible package configuration. RAM Memory: 128 to 5K bytes. Recognized for best in class EMC behaviour. Flash, ROM and FAST ROM to accommodate production ramp-up and economy of scale. From 2.4V to 5V Range in order to support different voltage environments. Cost Effective with models in Flash High reliability supported by the most demanding quality standards, The best Flash Data-retention specification. Complete tools offer From low cost development tools up to very high end emulators Various demonstration boards, and software library for an quick and easy hands on. In Circuit debugging module for fast verification. Production tools for Flash including Gang Programmer, or software DLL for ICP. Aggressive technology road map down to 0.18um
- 4. Features Advancedarchitecture offering Fast Programming and cost effective High Density Flash memory Rich Interrupt management In-circuit programming Data retention robustness Rich Peripheral set : SCI, LINSCITM, CAN 2.0B, SPI, I²C, USB, 16b timer, 8b timer Fast Conversion 10 bit A/D (3us to 7us) Wide choice of combination Scalable solution from Low to high pin count (8 to 80 pins) small to large memory (4K to 60K) 2.7V and 5V Applications, various Power saving modes The ST7 core (von neuman architecture) is built around An 8-bit Arithmetic and Logic Unit (ALU) 6 internal registers: Accumulator (A), X and Y index registers, Program Counter (PC), the Stack Pointer (SP) and the Code Condition register (CC) A controller block
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- 7. 8-Bit μC –General Purpose Line Complexity
- 8. ST7 CORE BlockDiagram ST7 Core
- 9. Internal Registers SixInternal Register
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- 11. ST7 INTERRUPTS OverviewExcept for the software interrupt (TRAP Instruction), all interrupts can be masked by setting the I BIT in CC When an interrupt occurs: The context is saved on the stack (CC, A, X, PC) All other interrupts are masked (the I bit is set By H/W) The interrupt vector is loaded in the Program Counter When return from interrupt is executed: The original context is automatically restored (CC, A, X, PC) Interrupts are enabled (I bit reset) Priority between interrupts is given by the interrupt address vector (Higher address = higher priority) Different Interrupts CPU INTERRUPT Reset Trap (Instruction) External Interrupt 0 External Interrupt 1 CSS SPI Timer A Timer B I2C Interrupt vectors: up to 16 vectors Number: 16 levels hardwired Software priority (Nested mode only): 4 levels user configurable Interrupt Reaction Time: 1.250µs to 2.750 µs (end of the current instruction +10 cpu cycles) Automatic register pushed: Program counter, accumulator, CC, X
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- 13. ST7 CORE Resetsources External reset using reset pin Purpose: allow to generate an external reset Condition: reset pin pull low Power supply dependent reset using LVD Purpose: ensure the MCU is in a known state whatever Vcc Condition: internal reset when Vcc reaches Vcc min Watchdog reset using the watchdog timer Purpose: guarantee the safety in case of software trouble Condition: internal reset when the WD register is not refreshed Illegal opcode Purpose: guarantee the safety in case of software trouble Condition: internal reset when executing an undefined prebyte or opcode
- 14. Low Voltage Detection3 Selectable levels Activation Flag RESET pin tied to GND
- 15. Flash Memory Module XFlash Single voltage Cycling:10K in program memory, 300K in data e²prom Programming method: Byte per byte or parallel (x32) programming with hardware control Prog/Erase time: 5ms for 1 to 32Bytes(including erasing) Supply conditions: 2.4V ≤ VDD ≤ 5.5V HDFlash Dual voltage Cycling:100 in program memory Emulated Data E²prom Programming method: Byte per byte or parallel (x256) programming and sectorized erasing with Embedded Commands Byte Prog: 49us, Block programming: 12.5ms-3s Sector erasing: 1.5-8.5s. Supply conditions: 3.8V ≤ VDD ≤ 5.5V (dedicated low voltage version) 11.4V ≤ VPP ≤ 12.6V XFlash HDFlash
- 16. ST7 EEPROM BLOCKDIAGRAM
- 17. FLASH PROGRAMMING Howto program: ICP: allows to PROGRAM or REPROGRAM (Xflash and HDFlash devices) the Program Memory when the micro is soldered on the application board or on an EPB socket. IAP: allows to program the whole FLASH memory except sector 0, when the application is running
- 18. ICC MODE Communicatingwith ICC Protocol Dedicated RESET sequence to enter ICC mode Real 4 pin ICC protocol ICCCLK, ICCDATA, RESET, VSS (and VPP when needed) No speed constraint for ST7 or Controller (PC/Tester) Minimum hardware needs to connect to a PC parallel port Allow ICD emulation and ICT without any other added external HW resources Bidirectional communication protocol Optimum command base protocol to manage ICP, ICT, ICD Commands: Read, Write, Go, Get SP
- 19. ST7 I/O PORTsAll the I/Os are individually software configurable using 3 different registers: DDR: Data Direction Register DR: Data Register Option Register
- 20. ST7 A/D CONVERTERBlock diagram 8-Bit on ST72254, ST72334, ST7Lite0 3µS 10-Bit on ST7Lite2, ST72264, ST7232x, ST72521,ST7262 7.25µS Conversion based on successive approximations with sample and hold circuitry Up to 16 analog channels Conversion time at fADC = 4MHz
- 21. ST7 16-BIT TimerBlock Diagram
- 22. ST7 SPI BlockDiagram
- 23. ST7 SCI BlockDiagram
- 24. ST7 I 2C Block Diagram I 2 C CLOCK CONTROL REGISTER
- 25. ST7 USB InterfaceTopology: Master-Slave architecture Tiered Star Physically - Up to 6 tiers - Up to 127 devices - 1 Master = Host Bus transaction Speed 12Mbps (full speed) - 1.5Mbps (low speed) - 480Mbps (High speed) - Embedded clock and data Isochronous and Asynchronous transfer PERFORMANCE APPLICATION ATTRIBUTES LOW SPEED Interactive Devices 10 - 100kb/s Keyboard, Mouse Game peripherals Monitor Configuration Lower cost Hot plugging Ease of use Multiple peripherals Full SPEED Phone, Audio Compressed Video 500Kb/s - 10Mb/s Printers Scanners Telephony Audio Low cost Hot plugging Ease of use Guaranteed latency Guaranteed Bandwidth Multiple devices HIGH SPEED (USB 2.0) Video, Disk 25 - 500 Mb/s Video Mass Storage High Bandwidth Guaranteed latency Ease of use
- 26. USB Host /Device LOW SPEED USB: The ST7263B series USB devices used in applications such as game pads, joysticks and UPS devices that need to exchange only short messages with the host computer. Benefit of low-speed USB: 3 endpoints including 2 with interrupt IN/OUT capability. HIGH SPEED USB: The ST7SCR provides low pin-count and single-chip solutions for EMV smartcard readers, with an exceptionally high level of integration. It includes an integrated smartcard analog interface and UART. Benefit of full-speed USB: 5 endpoints including 3 with interrupt IN/OUT and bulk capability
- 27. Basic vs. FullCAN Full CAN controller Many Buffer Sophisticated message filtering Dedicated HW Larger silicon (buffer size, filtering) Buffer allocation is static based on message ID Messages may not be copied to RAM (automatic reply capability) Typical: Car body Basic CAN Few Tx/Rx buffers Simple identifier filtering More SW overhead Less silicon Buffer allocation is dynamic based on avalaibility Messages must be copied to RAM (more CPU load) Typical: Engine management
- 28. ST7 CAN CELL- Block Diagram
- 29. Additional Resource Forordering the ST7 Microcontrollers, please click the part list or Call our sales hotline For additional inquires contact our technical service hotline For more product information go to http://www.st.com/mcu/inchtml-pages-st7.html Newark Farnell
Editor's Notes
- #3 Welcome to the training module on STMicroelectronics Overview of ST7 8-bit Microcontrollers. This training module provides an overview of ST7 8-bit Microcontrollers and its key features.
- #4 The ST7 has a CISC architecture which has up to 60K program memory and voltage range of 2.4V to 5V. The ST7 is based on a Von Neumann architecture, that is, there is only one addressing space in which program, data and input-output peripherals are mapped.
- #5 Here summarized some features of the ST7 Microcontroller family like Architecture, Peripherals, and Scalability. The ST7 has one address bus of 16 bits and one data bus of 8 bits. The core provides 6 internal registers used to store and calculate all CPU operations and a controller block that is able to decode/execute all the program instructions
- #6 The picture shows the different families available on ST7 microcontroller: ST7Lite, ST723XX, ST7WIND, ST726XX, ST7MC and their targeted application areas like Low End, Mid-range, RF, USB, Motor driven Application.
- #7 Here gives you brief idea about the key application where ST7 family devises can go.
- #8 The ST7 family consists of more than 50 microcontroller devices, available in 16 different types of package, ranging from 16 to 128 pins, with Flash from 1KB to 60KB. Most products also have compatible ROM versions. It supports for every type of Application like: smart sensors, large/small home appliances, as well as utility metering, car body, telephones, computers, process control and alarm systems.
- #9 The above block diagram shows the Core of ST7 Microcontroller. It interfaces with the peripherals and memory through the Address/ Data Bus. The ST7 has one address bus of 16-bit and one data bus of 8-bit. It has enhanced instruction set featured Core which offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The core is built with six internal registers and a control block which decodes and executes the instructions and the arithmetic and logic unit
- #10 The core has six internal registers, they do not have memory addresses. They can be reached only with specific instructions. The reset value of the program counter is the 2 bytes located at the address FFFE & FFFF (Reset Vector). The reset value of the I bit of the condition code register is 1.
- #11 The memory stores both the program and the data. The ST7 memory is linear. There is no pagination. So up to 64K can be addressed. RAM0 & Hardware Registers are addressed using short addressing modes, the address is coded in only one byte instead of two for the other parts of the memory. All the data located in the zero page (RAM0) have a faster access and generate less code when accessed than that located in the other locations.
- #12 The ST7 enhanced interrupt management provides Hardware interrupts, Software interrupt (TRAP) and Nested or concurrent interrupt management with flexible interrupt priority and level management. The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
- #13 The clock is generated from the multi-oscillator (up to 16 MHz). Then if the Clock Security System is activated (by option byte) the clock is filtered or replaced by the backup (safe) oscillator frequency (around 300 kHz). The frequency, called fosc, is then sent to a clock divider (at least by 2 in run mode) to become fcpu. fcpu is the clock sent to the core and to all the peripherals. The Clock divider is used to enter in Slow mode (Miscellaneous register 1). fcpu can be output on one pin called MCO (Main Clock Out) to drive other chips.
- #14 There are three reset sources in ST7 devices, External reset source pulse , Internal LVD reset (Low Voltage Detection), and Internal watchdog reset. The reset state is very important and has to be taken into account during the application development (hardware side). The I/Os on ST7 are in floating input state during the reset phase (default state) in almost all the devices
- #15 The purpose of the Low Voltage Detector (LVD) is to ensure that the ST7 always functions in its safe area. When VDD is below the “Min Working VDD”, the behaviour of the ST7 is no longer guaranteed. There is not enough power to decode/execute the instructions and/or read the memory. When VDD is below the LVD level the ST7 enters into reset state (internal reset High) in order to prevent unpredictable malfunctions.
- #16 The extended flash memory technology is based on EEPROM technology. It provides extended features such as byte per byte re-programming and data EEPROM capability. These devices are available between 1k and 16kbytes of memory size. The high density flash memory is based on flash technology. The high density of the HDFlash cell is used for devices with 4k up to 60kbytes flash memory. This memory is programmed byte per byte but erased by sector
- #17 The EEPROM memory matrix is made of 8 rows. Each row is made of 32 bytes. The cell is built around a 32 byte latch, where the bytes are copied using the 5 LSb of their address. Then the row is selected using the 11 MSb of the last write access to the latch and the previous written byte are loaded from the latch to the EEPROM memory matrix. An Interrupt can be generated at the end of the programming cycle depending on the value of the E2ITE bit of the control register. The two bits E2LAT and E2PGM set the operation of the EEPROM cell
- #18 There are 2 ways of programming the device, ICP (In-Circuit Programming) and IAP (In-Application Programming). T he implementation of IAP depends on the user application software. The data to be programmed into the XFlash memory is read from an external controller using a communication method called “user protocol”. This user protocol can be an SPI, SCI, CAN or USB interface.
- #19 Here explains about In-Circuit Communication (ICC) protocol. Testing or debugging tools can be written using the ICC protocol. The In-Circuit Communication (ICC) protocol is used by the ST7 microcontroller to communicate with an external controller. It is a half-duplex synchronous serial communication protocol using the two lines ICCCLK and ICCDATA. ICC enables an ST7 microcontroller to communicate with an External Controller (e.g. PC with ICC interface board) with only 4 wires including VSS. This protocol is used to download a program into the RAM for execution.
- #20 The diagram illustrates all I/O ports of the ST7 processors. The core, the memory, the power supply, reset and watchdog blocks are all present in ST7 devices as well. There is at least one timer and are I/O ports for input or output electrical signals on all ST7 devices. The ST7 family offers a very flexible feature on its parallel I/O where each bit can be independently configured as either an input with two options (with or without pull-up resistor), or an output with also two options (open-drain or push-pull).
- #21 There are 8-bit and 10-bit resolution Analog-to-digital converters in the ST7 family. The input range is positive; negative voltages are not converted. The ADC is fed with the core clock frequency. the analog multiplexer is driven by the bits [CH3:CH0] of the A/D control and status registers. This selects which analog input has to be converted. The analog signal is sent to the sample and hold and A/D converter where the value is converted. At the end of the conversion the EOC bit is set and the result is placed in the data registers as it is a 10-bit A/D converter here. No interrupt can be generated due to the speed of the conversion. The conversion time for a typical ST7 8-bit A/D, running at frequency of 4MHz is 3us and for 10-bit it is: 7.25us.
- #22 This slide shows 16 bit timer which has below features: There is a prescalar block and the bits CCO and CC1 configure the frequency of the timer. There is a free running counter register for the 16-bit counter. There are timer overflow status flags and maskable interrupts asscociated with the input capture and output compare modes. There are two Output Compare functions each with two 16-bit registers, two status flags and one maskable interrupt. There are two input capture functions with two 16-bit registers, active edge selection signals, status flags and one dedicated maskable interrupt. There is one status register and two control registers.
- #23 The SPI is built around a 8-bit shift register with both ends of the shift register brought out to MCU pins. One end of the shift register is connected to the master-in slave-out pin, MISO. This pin acts as an input for the master SPI Module and as an output for the slave SPI Module. The other end of the shift register is connected to MOSI pin. The CPU begins a serial SPI transfer by writing a byte of data to the master’s SPI transmit data register. All 8-bits of data will be automatically transferred serially out the master’s MOSI pin synchronized to the master’s SCK clock output. For each bit shifted out of the master’s MOSI pin, a bit is shifted in through the master’s MISO pin allowing full duplex communication. The control on SPI is done using SPIDR, SPISR, SPICR, SPIE, SPE, SSM SSI bits.
- #24 The SCI is connected through 2 I/O pins: TDO (Transmit Data Output) and RDI (Receive Data Input). The data register is made of 2 transmit registers (one buffer and one shift register). To start a transmission the user writes in the data register. The first time the shift register is empty and so, the byte goes directly into it and the transmission starts. A flag indicates that the buffer is free and so the 2nd byte of the frame will be placed in the buffer. When the transmission of the 1ST byte is ended, the 2nd one goes directly in the transmit register and the transmission of the 2nd byte starts .
- #25 The SDA line is connected to the data control (checking the arbitration) and the 8 bit shift register of the data register. There are 2 own address registers: after a start condition the first received data is compared to the value of the OAR registers.
- #26 Here gives you an overview of Basic USB interfaces. Bus transition can be done using Full speed, Low Speed, High Speed and Synchronous and Asynchronous mode. USB can have up to 127 Devices connected to network.
- #27 It shows basically how USB Host and USB Device is going to communicate each other. This page gives you the ST7 devices that supports for USB devices. The ST7263B series is a low speed USB mode, and the ST7SCR has high speed USB features.
- #28 Here explains about the Basic operation of CAN controller. ST7 microcontroller uses exclusively Basic CAN. Full CAN is dedicated to more sophisticated microcontrollers like ST9 or ST10.
- #29 This slide shows the block diagram of the ST7 CAN controller which has Tx/Rx Buffers of 10 Bytes each. It supports the CAN 2.0B specification up to 1MBits/s. ST7 controllers that embed CAN are - ST72T511, ST72T589, ST72T55 - ST72F521.
- #30 Thank you for taking the time to view this presentation on Overview of ST7 8-bit Microcontrollers. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simple call our sales hotline. For more technical information you may either visit the STMicroelectronics site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.