The document discusses the IA-64 architecture, which was jointly developed by Intel and HP as a 64-bit architecture intended for implementation on EPIC processors like Itanium. Some key points: - IA-64 uses explicit instruction-level parallelism specified by the compiler rather than relying on superscalar execution. It supports long instruction bundles containing multiple operations. - The architecture has large register sets, multiple execution units, predicated execution, and support for software pipelining to further exploit instruction level parallelism. - The Itanium processor implemented IA-64 using a superscalar design with hardware support for the EPIC features like predication and speculation.

1. Assembly Language AI-64 Motaz K. Saad Spring 2007 Motaz K. Saad, Dept. of CS

4. Superscalar v IA-64 Motaz K. Saad, Dept. of CS

7. General Organization Motaz K. Saad, Dept. of CS

10. Instruction Format Diagram Motaz K. Saad, Dept. of CS

14. Predication Motaz K. Saad, Dept. of CS

15. Speculative Loading Motaz K. Saad, Dept. of CS

20. Software Pipeline Example Diagram Motaz K. Saad, Dept. of CS

22. IA-64 Register Set Motaz K. Saad, Dept. of CS

26. Register Stack Behaviour Motaz K. Saad, Dept. of CS

27. Register Formats Motaz K. Saad, Dept. of CS

29. Itanium Processor Diagram Motaz K. Saad, Dept. of CS