UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Functional verification is one of the key bottlenecks in the rapid design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary tools used in logic and functional verification of commercial integrated circuits are simulation (at various levels), emulation at the chip level, and formal verification.
Basics of Functional Verification - Arrow DevicesArrow Devices
Are you new to functional verification? Or do you need a refresher? This presentation takes you through the basics of functional verification - overall scope and process with examples. Also included are some tips on do's and don'ts!
Functional verification is one of the key bottlenecks in the rapid design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary tools used in logic and functional verification of commercial integrated circuits are simulation (at various levels), emulation at the chip level, and formal verification.
Basics of Functional Verification - Arrow DevicesArrow Devices
Are you new to functional verification? Or do you need a refresher? This presentation takes you through the basics of functional verification - overall scope and process with examples. Also included are some tips on do's and don'ts!
This tutorial is intended for verification engineers that must validate algorithmic designs. It presents the detailed steps for implementing a SystemVerilog verification environment that interfaces with a GNU Octave mathematical model. It describes the SystemVerilog – C++ communication layer with its challenges, like proper creation and activation or piped algorithm synchronization handling. The implementation is illustrated for Ncsim, VCS and Questa.
SystemVerilog Assertions verification with SVAUnit - DVCon US 2016 TutorialAmiq Consulting
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- decouple assertion validation code from assertion definition code
- simplify the generation of a wide range of stimuli, from 1 bit signal toggling to transactions
- provide the ability to reuse scenarios
- provide self-checking mechanisms
- report test status automatically
- integrate with major simulators
This tutorial discusses SVA planning, coding guidelines, SVAUnit (SVAUnit framework, self-checking tests, debug), and test patterns. Planning includes parametrization, temporal sequence composition, sequence reuse and also consider how the SVA package will be integrated with other verification methods. Coding guidelines ensure efficiency as well as avoid common implementation pitfalls.
This Presentation will Clear the idea of non linear Data Structure and implementation of Tree by using array and pointer and also Explain the concept of Binary Search Tree (BST) with example
Those slides describe digital design using Verilog HDL,
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Wi-Fi: diagnosi lato client/edge
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Checking the Cross-Platform Framework Cocos2d-xAndrey Karpov
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In this article, we are going to discuss results of the check of Cocos2d-x, the framework for C++, done by PVS-Studio 5.18. The project is pretty high-quality, but there are still some issues to consider. The source code was downloaded from GitHub.
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The most powerful way of writing REST services is to define them via interfaces, then let the SOA/REST framework do all the routing, data marshalling and communication behind the scenes. One distinctive feature of mORMot is to define a method parameter as a notification interface, and let the server call back the client when needed, as with regular Delphi code. This session will present the benefit of defining REST services using interfaces, and how WebSockets can offer real-time notifications into your rich Delphi client applications.
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
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A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
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In his public lecture, Christian Timmerer provides insights into the fascinating history of video streaming, starting from its humble beginnings before YouTube to the groundbreaking technologies that now dominate platforms like Netflix and ORF ON. Timmerer also presents provocative contributions of his own that have significantly influenced the industry. He concludes by looking at future challenges and invites the audience to join in a discussion.
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GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
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1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
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The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
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Bob Boule
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Gopinath Rebala
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- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
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Maruthi Prithivirajan, Head of ASEAN & IN Solution Architecture, Neo4j
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Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
2. Ports
• SystemC lets modules use channels inserted
between the communicating modules.
• Such communication method uses a concept
related to a mechanism called port.
• Actually, a port is a pointer to a channel
outside the module.
3. Communication via Ports
• modA communicates a value contained in local variable v by calling
the write method of the parent module’s channel c. modB may
retrieve a value via the read method of channel c.
• Notice that access is accomplished via pointers pA and pB.
• modA only needs access to write, and modB only needs access to
read.
• This separation of access is managed using a concept known as an
interface.
4. Interfaces
• An interface class is a class that contains no data members
and only contains pure virtual methods. The derived classes
implements the access methods, respectively.
• If an object is declared as a pointer to an interface class, it
may be used with multiple derived classes.
5. Relation between interface and
channel
• A SystemC interface is an abstract class that inherits
from sc_interface and provides only pure virtual
declarations of methods referenced by SystemC
channels and ports. No implementations or data are
provided in SystemC interface.
• A SystemC channel is a class that implements one or
more SystemC interface classes and inherits from
either sc_channel or sc_prim_channel. A channel
implements all the methods of the inherited
interface classes.
6. Two Examples of Using Ports
• Ways of connecting ports, channels, modules
and processes cannot be arbitrary.
7. Convenience of sc_interfaces using
Ports
• Top: modA and modB are connected via a FIFO.
• Bottom: modA and modB are connected via a
shared bus.
• But, NO change to the definition of modA or
modB is necessary.
• A SystemC port is a class templated with and
inheriting from a SystemC interface. Ports
allow access of channels across module
boundaries.
12. Rules
• Port connected to channel through interface
• Between processes, events are used for
signaling, possibly for synchronization.
• Processes can communicate with processes via
interfaces to channels connected to the submodule ports or by way of interfaces through a
modules itself using sc_export.
• Modules communicate with processes via
channels. Ports and corresponding interfaces are
needed, mostly.
13. Mechanism
1.
2.
3.
4.
5.
Instantiate modules and channels
Make required interfaces
Connecting ports
Modules connected to channels
Syntaxes of connecting ports:
1. mod_inst.portname(channel_instance); // By
Name
2. mod_instance(channel_instance,...); // By
Position
14. Example: Video Mixer
• //FILE: Rgb2YCrCb.h
SC_MODULE(Rgb2YCrCb) {
sc_port<sc_fifo_in_if<RGB_frame> > rgb_pi;
sc_port<sc_fifo_out_if<YCRCB_frame> >
ycrcb_po;
};
Figure 11-11. Example of Port Interconnect Setup (1 of 3)
15. • //FILE: YCRCB_Mixer.h
SC_MODULE(YCRCB_Mixer) {
sc_port<sc_fifo_in_if<float> > K_pi;
sc_port<sc_fifo_in_if<YCRCB_frame> >
a_pi, b_pi;
sc_port<sc_fifo_out_if<YCRCB_frame> > y_po;
);
Figure 11-12. Example of Port Interconnect Setup (2 of 3)
16. • //FILE: VIDEO_Mixer.h
SC_MODULE(VIDEO_Mixer) {
// ports
sc_port<sc_fifo_in_if<YCRCB_frame> > dvd_pi;
sc_port<sc_fifo_out_if<YCRCB_frame> > video_po;
sc_port<sc_fifo_in_if<MIXER_ctrl> > control;
sc_port<sc_fifo_out_if<MIXER_state> > status;
// local channels
sc_fifo<float> K;
sc_fifo<RGB_frame> rgb_graphics;
sc_fifo<YCRCB_frame> ycrcb_graphics;
// constructor
SC_HAS_PROCESS(VIDEO_Mixer);
VIDEO_Mixer(sc_module_name nm);
void Mixer_thread();
};
Figure 11-13. Example of Port Interconnect Setup (3 of 3)
17. VIDEO_Mixer::VIDEO_Mixer(sc_module_name nm)
: sc_module(nm)
{
// Instantiate
Rgb2YCrCb Rgb2YCrCb_i("Rgb2YCrCb_i");
YCRCB_Mixer YCRCB_Mixer_i("YCRCB_Mixer_i");
// Connect
Rgb2YCrCb_i.rgb_pi(rgb_graphics);
Rgb2YCrCb_i.ycrcb_po(ycrcb_graphics);
YCRCB_Mixer_i.K_pi(K);
YCRCB_Mixer_I.a_pi(dvd_pi);
YCRCB_Mixer_i.b_pi(ycrcb_graphics);
YCRCB_Mixer_i.y_po(video_po);
};
Figure 11-14. Example of Port Interconnect by Name
18. VIDEO_Mixer::VIDEO_Mixer(sc_module_name nm)
: sc_module(nm)
{
// Instantiate
Rgb2YCrCb Rgb2YCrCb_i("Rgb2YCrCb_i");
YCRCB_Mixer YCRCB_Mixer_i("YCRCB_Mixer_i");
// Connect
Rgb2YCrCb_i(rgb_graphics,ycrcb_graphics);
YCRCB_Mixer_i(K,dvd_pi,ycrcb_graphics,video_po);
};
Figure 11-15. Example of Port Interconnect by Position
19. Within a Process
• A process is needed to activate some actions
on channels associated with it.
• It is also needed that the process be
connected to modules/channels.
• One can access ports from within a
process, too.
• Syntax:
– portname->method(optional_args);
20. Example: Video Mixer
void VIDEO_Mixer::Mixer_thread() {
…
switch (control->read()) {
case MOVIE: K.write(0.0f); break;
case MENU: K.write(1.0f); break;
case FADE: K.write(0.5f); break;
default: status->write(ERROR); break;
}
….
}
21. Notes of Video Mixer Example
• K: a channel using sc_fifo
• Control: port
– sc_port<sc_fifo_in_if<MIXER_ctrl> > control;
• Status: port
– sc_port<sc_fifo_out_if<MIXER_state> > status;
22. sc_fifo Interfaces
• Interfaces of sc_fifo: sc_fifo_in_if<>, and
sc_fifo_out_if<>.
• The channel sc_fifo is used to hold the data of
the fifo.
• Methods:
write, read, num_free, num_available, event,
…
23. Standard Interfaces
Interfaces were defined prior to the creation
of a channel. The channel is just the place to
implement the interfaces and provides the
request-update behavior for a signal.
24. Sc_fifo
• sc_fifo_in_if<>, and sc_fifo_out_if<>, are
provided for sc_fifo<>.
• Defined prior to the creation of the channel
• The channel is the place to implement the
interfaces and holds the data implied by a
FIFO functionality.
• The interface is templated on a class name
just like the corresponding channel
27. Sc_fifo and sc_signal
• If you simply use the read() and write()
methods in your module and do not rely on
the other methods, then your use of these
interfaces is very compatible sc_signal<>
• However, sc_fifo::read() and sc_fifo::write()
block waiting for the FIFO to empty;
whereas, sc_signal::read() and
sc_signal::write() are non-blocking
28. sc_signal interfaces
• sc_signal_in_if<>, sc_signal_out_if<>, and
sc_signal_inout_if<> are provided.
• The update portion of the behavior is provided as
a result of a call to request_update() .
• request_update() is indirectly resulted by a call
from sc_signal::write().
• The update is implemented with the protected
sc_signal::update() method call.
• sc_signal_in_if<> interface provides access to the
results through sc_signal::read().
31. More about sc_signal interfaces
• This definition lets a module read the value of an
output signal directly rather than being forced to
keep a local copy
• sc_signal_inout_if<> inherits the input behavior
from sc_signal_in_if<>. Thus, sc_signal<>
channel inherits directly from this
channel, sc_signal_inout_if<>, rather than the
other two interfaces.
• sc_signal_in_if<> interface provides access to the
results through sc_signal::read().
32. sc_mutex_if
// Definition of sc_mutex_if interface
struct sc_mutex_if: virtual public sc_interface {
virtual int lock() = 0;
virtual int trylock() = 0;
virtual int unlock() = 0;
};
// No event methods are provided for sensitivity. If
event sensitivity is required, one must implement
own channels and interfaces.
33. sc_semaphore_if
// Definition of sc_semaphore_if interface
struct sc_semaphore_if : virtual public sc_interface
{
virtual int wait() = 0;
virtual int trywait() = 0;
virtual int post() = 0;
virtual int get_value() const = 0;
};
//Same to sc_mutex_if, no event methods are provided
for sensitivity. You have to do your own if necessary.
34. Static Sensitivity when used with ports
• Sensitivity to events:
– an SC_METHOD statically sensitive to the
data_written_event.
– monitor an sc_signal for any change in the data
using the value_changed_event.
• Ports are pointers initialized during the
elaboration stage. However, they are not
defined when the sensitive method needs to
know about them.
35. sc_event_finder
• sc_event_finder allows the determination of
the actual event be deferred until after the
elaboration.
• sc_event_finder must be defined for each
event defined by the interface.
– define template specializations of port/interface
combinations to instantiate a port, and include an
sc_event_finder in the specialized class.
36. Example: A port with sensitivity to the
positive edge event of sc_signal
• sc_event_finder takes two arguments:
– a reference to the port being found (*this)
– a reference to the member function, (posedge_event()) that returns a
reference to the event of interest and can be used as sensitivity.
struct ea_port_sc_signal_in_if_bool
: public sc_port<sc_signal_in_if<bool>,1>
{
typedef sc_signal_in_if<bool> if_type;
sc_event_finder& ef_posedge_event() const {
return *new sc_event_finder_t<if_type>(
*this,
&if_type::posedge_event
);
}
};
37. Use of event finder
SC_MODULE(my_module) {
ea_port_sc_signal_in_if_bool my_p;
SC_CTOR(…) {
SC_METHOD(my_method);
sensitive << my_p.ef_posedge_event();
}
void my_method();
};
• An important concept of SystemC is its mechanism for
sensitivity to a port.
• A process is always concerned with any change on its input
port.
• An interface associated with a port provides a method called
default_event() that returns a reference to an sc_event. The
standard interfaces for sc_signal and sc_buffer provide this
method.
38. sc_port array
• Provide multi-port or port array of liked
defined.
• Syntax:
– sc_port <interface[ ,N]> portname;
– // N=0..MAX Default N=1
39. Example
//FILE: Switch.h
SC_MODULE(Switch) {
sc_port<sc_fifo_in_if<int>, 4> T1_ip;
sc_port<sc_signal_out_if<bool>,0> request_op;
};
There are four ports to provide data and 9 users to request data from
the ports. The switch thread is responsible to route the data from a left
side port to a right side user.
41. SystemC Exports
• Sc_export is similar to standard ports, but
different in its connectivity.
• It moves the channel inside a module and use
the port externally so that it looks like a
channel itself.
42. Sc_export
• It can be replaced by using normal channelinterface-port configuration, but
• It is sometimes desirable that it exports some
channels but keep others private. This is a
feature preferred by most IP provider;
• It can provides multiple interfaces at the top
level, though one can still use hierarchical
channels.
43. Other advantages
• Each sc_export contains an interface, so
connection is not required and hidden interface
can be made.
• A specific interface is hidden from IP provider, not
disclosed to the users.
• A model for profiling or exploration can be made
with such exports which can be dropped in the
later stage of development.
• Syntax:
– sc_export<interface> portname;
44. Syntax of internal channel binding
SC_MODULE(modulename) {
sc_export<interface> portname;
channel cinstance;
SC_CTOR (modulename) {
portname (cinstance);
}
};
Export portname is bound to channel cinstance.
46. Three points to be noted
• No array export is supported.
• Unlike a sc_port, It lacks the requirement of a
connection.
• Static sensitivity cannot be used here, though
one can use wait(exportname->event()) on
defined interfaces in an SC_THREAD.
47. Example: Bus Model
//CBus.h
#ifndef CBUS_H
#define CBUS_H
#include "CBus_if.h"
class North_bus; // Forward declarations
class South_bus;
class Debug_bus;
class CBus_rtl;
SC_MODULE(CBus) {
sc_export<CBus_North_if> north_p ;
sc_export<CBus_South_if> south_p;
SC_CTOR(CBus);
private:
North_bus* nbus_ci; South_bus* sbus_ci;
Debug_bus* debug_ci; CBus_rtl* rtl_i;
};
#endif
48. Example
//FILE: CBus.cpp
#include "CBus.h"
#include "North_bus.h"
#include "South_bus.h"
#include "Debug_bus.h"
#include "CBus_rtl_bus.h"
CBus::CBus(sc_module_name(nm): sc_module(nm) {
// Local instances
nbus_ci = new North_bus("nbus_ci");
sbus_ci = new South_bus("sbus_ci");
debug_ci = new Debug_bus("debug_ci");
rtl_i = new CBus_rtl("rtl_i");
// Export connectivity
north_p(nbus_ci);
south_p(sbus_ci);
// Implementation connectivity; debug bus is not provided;
}
49. Hierarchical Channel
• Module controls and processes data.
• Channel takes care of communication among modules.
• Interface allows independent implementation of
modules and channels as well as separation of
processing and communication.
• Primitive channels contains no hierarchy, ports, and so
on, so they are fast.
• Hierarchical channels are able to access ports, build
hierarchy so that they can be used to model more
complex bus architectures, such as AMBA, PCI,….
• Actually, hierarchical channels are just MODULES that
implement one or usually more than one interfaces.