Greg Tierney of Avid presented on their experiences using SystemC for design verification. SystemC provides hardware constructs and simulation capabilities in C++. Avid chose SystemC to enhance their existing C++ verification code and take advantage of its industry acceptance and built-in verification features. SystemC helped Avid solve issues like crossing language boundaries between HDL modules and testbenches, connecting ports and channels, implementing randomization, using multi-threaded processes, and defining module hierarchies. However, Avid also encountered issues with SystemC like slow compile/link times and limitations in its foreign language interface.

1. Experiences with SystemC
Design Verification Using
SystemC
Greg Tierney
Presented to
DV Club, Boston
March 5, 2007
DV Club, Boston

2. Experiences with SystemC
About Avid
Invented digital video editing
Headquartered in Tewksbury
– http://www.avid.com/company/
Products
– Film/Video Editing and
Finishing
– Audio
– Broadcast
– Animation
– Storage & Workgroups
– Digital Asset and Production
Management
Services
– Support
– Training
– Consulting
DV Club, Boston

3. Experiences with SystemC
Agenda
What is SystemC?
Why did Avid choose to use SystemC?
DV problems solved by SystemC.
Summary
DV Club, Boston

4. Experiences with SystemC
What is SystemC?
Provides hardware constructs and a simulation kernel
for C++
It is a class library
– And it is a language standard (IEEE 1666TM 2005)
It has utilities and constructs
– Data types, ports, channels, processes
Adopted by different disciplines
– Architectural Modeling (SoC, performance)
– DV (RTL simulation, HW/SW co-verification)
– Synthesis
It is open source (OSCI)
– http://www.systemc.org
DV Club, Boston

5. Experiences with SystemC
Why Avid Chose SystemC
Enhanced existing C++ DV code
– Replaced an unreliable in-house framework
• Signal encapsulation
• Thread management
• Random seed management
– Smooth transition from C++ to SystemC
Tool availability
– Single kernel multi-language simulator
Industry acceptance
Low cost
Came with built-in verification capabilities
DV Club, Boston

6. Experiences with SystemC
Agenda
What is SystemC?
Why did Avid choose to use SystemC?
DV problems solved by SystemC.
Summary
DV Club, Boston

7. Experiences with SystemC
Crossing Language Boundaries
Connect an entire HDL module to the
testbench.
– Wrap the module with a SystemC class
(sc_foreign_module).
– Provide a string mapping for each port.
Connect a foreign signal anywhere in the
hierarchy.
– Bind a sc_signal (observe_foreign_signal).
– Provide a string of hierarchical path to wire or reg.
DV Club, Boston

8. Experiences with SystemC
Code Examples
class MyDUT : public sc_foreign_module { SC_MODULE(MyVTB)
public: {
sc_in<sc_logic> reset;
public:
sc_in<sc_logic> clock;
sc_out<sc_lv<16> > AD; SC_CTOR(MyVTB) :
MyDUTInst(“MyDUTInst”, “MyDUT”),
MyDUT(sc_module_nam nm, const char* hdl_name) MyMonitorInst(“MyMonitorInst”,
: sc_foreign_module(nm, hdl_name), “MyVTB.MyDUTInst.FooInst”)
reset(“reset”),
{
clock(“clock”),
AD(“AD”){} MyDUTInst.reset(tb_reset);
}; MyDUTInst.clock(tb_clock);
MyDUTInst.AD(tb_AD);
class MyMonitor : public sc_module { }
public: private:
MyMonitor(sc_module_name, MyDUT MyDUTInst;
const string& path2DUT){ MyMonitor MyMonitorInst;
string path2sig = path2DUT + “.snoop”;
snoopSig_.observe_foreign_signal(path2sig); sc_signal<sc_logic> tb_reset;
SC_THREAD(threadT); sc_signal<sc_logic> tb_clock;
sensitive << sc_signal<sc_lv<16> > tb_AD;
snoopSig_.value_changed_event(); };
}
private:
sc_signal<sc_logic> snoopSig_;
void threadT();
};
DV Club, Boston

9. Experiences with SystemC
Issues with Binding
No clear standard for language boundary
resolution.
– Each vendor has its own implementation.
– Implementation we use doesn’t map arrays or
records (yet).
Supporting foreign interface requires two
pass compilation.
– First pass creates object files.
– Second pass builds a symbol library used in
design elaboration.
DV Club, Boston

10. Experiences with SystemC
SystemC Connections
p
start() p start()
Call a public method Connect sc_port to a
via pointer to object sc_export
outp write() read() inp
Connect sc_port to a
channel
DV Club, Boston

11. Experiences with SystemC
Code Examples
struct start_stop_if : public sc_interface SC_MODULE(MyTest){
{ public:
virtual void start()=0; sc_port<start_stop_if> bfm_port;
virtual void stop()=0; };
}; SC_MODULE(vtb){
public:
class MyBFM : SC_CTOR(vtb);
public sc_module, private:
public virtual start_stop_if sc_signal<sc_logic> Clock;
{ sc_signal<sc_logic> Request;
public: sc_signal<sc_lv<16> > AD;
sc_in<sc_logic> Clock; tlm::tlm_fifo<MyX> MyXReceiveChan;
sc_out<sc_logic> Request; MyTest MyTestInst;
sc_in<sc_lv<16> > AD; MyBFM MyBFMInst;
tlm::tlm_put_port<MyX> MyXReceivePort; };
sc_export<start_stop_if> StartStopExport;
vtb:vtb(sc_module_name) :
void start(); MyBFMInst(“MyBFMInst”), MyTestInst(“MyTestInst”)
void stop(); {
MyBFMInst.Clock(Clock);
SC_CTOR(MyBFM){ MyBFMInst.Request(Request);
StartStopExport(*this); MyBFMInst.AD(AD);
} MyBFMInst.MyXReceivePort(MyXReceiveChan);
}; MyTestInst.bfm_port(MyBFMInst.StartStopExport);
}
DV Club, Boston

12. Experiences with SystemC
Issues with Connections
Construction and binding are separate steps.
– Ports must be public.
– Ports bound after modules and channels are constructed.
Binding uses “strict type checking”.
– Compilation will fail if type mismatch in the connection.
– Splitting a vector across multiple ports is complicated.
Binding errors detected at elaboration.
– Simulation should abort at runtime if a port is not bound.
– Need to assign attributes to port (e.g. # of connections).
DV Club, Boston

13. Experiences with SystemC
Randomization
Separate library dedicated to verification
constructs (SCV).
Robust, rich feature set for
randomization.
– Simple constraints (ranges and lists).
– Complex constraint solver.
– Thread-safe seeding.
– Extendible to custom object types.
DV Club, Boston

14. Experiences with SystemC
Randomization at Avid
SCV more than we needed.
– So, we use a subset of the features.
Provide a Tcl interface to apply constraints.
– Wrap scv_smart_ptr.
– Define string representations for simple
constraints.
– Recompilation not required to change constraints.
– Reapply constraints over course of simulation.
DV Club, Boston

15. Experiences with SystemC
Processes
Hardware is inherently parallel.
DV must be multi-threaded.
SystemC solves this with processes.
– Macros: SC_THREAD and SC_METHOD.
– Events, mutexes, semaphores.
– Dynamic processes (sc_spawn).
DV Club, Boston

16. Experiences with SystemC
Hierarchy
SystemC defines an object hierarchy.
– Relates objects (parent/child).
– Familiar to HDL design.
Avid DV defines a layer hierarchy.
– Relates connections.
– Familiar to communication stacks.
Issue: SystemC is not a methodology.
DV Club, Boston

17. Experiences with SystemC
Example Hierarchy
VTOP
VTEST
Test
Translator Reference Model Scoreboard
VTB
TLM Agent
STIMGEN Analysis Agent Analysis Agent
Commander_BFM TX_BFM Snooper_BFM RX_BFM
Driver Monitor Driver Monitor Monitor Monitor
DUT
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18. Experiences with SystemC
Agenda
What is SystemC?
Why did Avid choose to use SystemC?
DV problems solved by SystemC.
Summary
DV Club, Boston

19. Experiences with SystemC
Additional Issues
Compile and link performance is disappointing.
– Overuse of C++ templates in library.
– Partially attributed to vendor implementation.
Libraries are huge.
Being a language standard has tool implications.
C++ learning curve.
– C++ code debug very different than HDL.
• Segmentation faults, stack traces, code stepping
Think like a HW engineer, code like a SW engineer.
DV Club, Boston

20. Experiences with SystemC
Avid’s Experience
Used reliably for nearly 3 years.
Runtime performance very satisfactory.
Provides opportunity to assist product
development beyond DV.
– Evaluate architectures and predict
performance.
– Create programmer’s view models for
emulation and HW/SW co-verification.
DV Club, Boston