This document provides an overview of switching theory unit 2, which covers combinational logic circuits and their design procedures. It discusses various combinational logic components like adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. It provides block diagrams, truth tables, and logic expressions for designing these components. The key topics covered include the characteristics of combinational circuits, the 4-step design procedure for any combinational circuit, implementation of full adders and subtractors, working of multiplexers and demultiplexers of different sizes, and working of encoders and decoders.

1. SWITCHING
THEORY UNIT 2
BY:SURBHI SAROHA

2. SYLLABUS
• Combinational Logic Circuits
• Design Procedure
• Adders
• Subtractors code conversion
• Multiplexers/Demultiplexers
• Encoder/decoders
• Decimal adders & amplitude comparators
• ROM as decoder
• PLA & PAL

3. Combinational Logic Circuits
• Combinational circuit is a circuit in which we combine the different
gates in the circuit, for example encoder, decoder, multiplexer and
demultiplexer. Some of the characteristics of combinational circuits are
following −
• The output of combinational circuit at any instant of time, depends only
on the levels present at input terminals.
• The combinational circuit do not use any memory. The previous state
of input does not have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number
of outputs.

4. Block diagram

5. Design Procedure
• A Combinational Circuit consist of logic gates whose outputs at any instant of time
are determined directly from the present combination of inputs without regard to
previous input.
• Examples of combinational circuits: Adder, Subtractor, Converter, and
Encoder/Decoder.
• Following are the four steps to construct and analyze any combinational circuit.
• Step-1: Identify the number of inputs and outputs of the circuit.
First of all, we have to think about the inputs and outputs of the circuit by considering
which type of logical operation we want to perform with the circuit.
For example, we have to create a circuit that can add two bits. For this, we require
two inputs (one for the first bit (A) another for the second bit (B)) and two outputs one
for sum (S) of two bits and another for carry (C).In total, we require 2 inputs and 2
outputs. So here our first step is completed.

6. Cont…..
• Step-2: Creating the Truth Table.
In this step we have to create truth table for our circuit so for this first
we will create input columns and list all the possible combinations of
inputs. In our case 2 bits can have maximum 4 combinations (00 01 10
11).
Now in output, we have two columns (Sum and Carry) as discussed
earlier. Now we have to fill output columns in such a way that for which
logical operation we are constructing circuit.In our circuit, we want
addition so we will add those input bits and write the sum of those bits
in (Sum) column and if carry is generated we will write 1 else write.
• 0 in (Carry) column.

7. Cont….

8. Cont….
• Step-3: Simplify the Boolean function for each output.
• In this step, we have to just create a simplified Boolean function
according to inputs and outputs of the truth table obtained in the
previous step.
• For Sum,
• Sum = A'B + AB' = A XOR B
• For Carry,
• Carry = AB = A AND B

9. Cont….
• Step-4: Constructing circuit using Boolean function obtained from third
step.
For sum, we have obtained (A XOR B) so we will connect A and B to
the inputs of XOR gate and take its output as a sum. For carry, we
have obtained (A AND B) so we will connect A and B to the inputs of
AND gate and take its output as a carry.

10. Full Adder in Digital Logic
• Full Adder is the adder which adds three inputs and produces two
outputs.
• The first two inputs are A and B and the third input is an input carry as
C-IN.
• The output carry is designated as C-OUT and the normal output is
designated as S which is SUM.
• A full adder logic is designed in such a manner that can take eight
inputs together to create a byte-wide adder and cascade the carry bit
from one adder to the another.

12. Full Adder Truth Table:

13. Subtractors code conversion
• A full subtractor is a combinational circuit that performs subtraction of
two bits, one is minuend and other is subtrahend, taking into account
borrow of the previous adjacent lower minuend bit.
• This circuit has three inputs and two outputs.
• The three inputs A, B and Bin, denote the minuend, subtrahend, and
previous borrow, respectively.
• The two outputs, D and Bout represent the difference and output
borrow, respectively.

15. Truth Table

16. Cont….
• From above table we can draw the K-Map as shown for “difference”
and “borrow”.

17. Cont…..

18. Multiplexers/Demultiplexers
• A multiplexer is a combinational circuit that has 2n input lines and a
single output line. Simply, the multiplexer is a multi-input and single-
output combinational circuit. The binary information is received from
the input lines and directed to the output line. On the basis of the
values of the selection lines, one of these data inputs will be connected
to the output.
• Unlike encoder and decoder, there are n selection lines and 2n input
lines. So, there is a total of 2N possible combinations of inputs. A
multiplexer is also treated as Mux.
• There are various types of the multiplexer which are as follows:

19. Cont….
• 2×1 Multiplexer:
• In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection
line, i.e., S0 and single outputs, i.e., Y. On the basis of the combination
of inputs which are present at the selection line S0, one of these 2
inputs will be connected to the output. The block diagram and the truth
table of the 2×1 multiplexer are given below.
• Block Diagram:

20. Truth Table:

21. Cont….
• The logical expression of the term Y is as follows:
• Y=S0'.A0+S0.A1
• Logical circuit of the above expression is given below:
•

22. 4×1 Multiplexer:
• In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and
A3, 2 selection lines, i.e., S0 and S1 and single output, i.e., Y. On the
basis of the combination of inputs that are present at the selection lines
S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.

23. Truth Table:

24. Cont….
• The logical expression of the term Y is as follows:
• Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
• Logical circuit of the above expression is given below:

25. 8 to 1 Multiplexer
• In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3,
A4, A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output,
i.e., Y.
• On the basis of the combination of inputs that are present at the
selection lines S0, S1, and S2, one of these 8 inputs are connected to
the output.
• The block diagram and the truth table of the 8×1 multiplexer are given
below.

26. Block Diagram:

27. Truth Table:

28. The logical expression of the term Y is
as follows:
• Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+
S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7

29. De-multiplexer
• A De-multiplexer is a combinational circuit that has only 1 input line and 2N output
lines.
• Simply, the multiplexer is a single-input and multi-output combinational circuit.
• The information is received from the single input lines and directed to the output line.
• On the basis of the values of the selection lines, the input will be connected to one of
these outputs. De-multiplexer is opposite to the multiplexer.
• Unlike encoder and decoder, there are n selection lines and 2n outputs.
• So, there is a total of 2n possible combinations of inputs. De-multiplexer is also
treated as De-mux.

30. 1×2 De-multiplexer:
• In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1,
1 selection lines, i.e., S0, and single input, i.e., A.
• On the basis of the selection value, the input will be connected to one
of the outputs. The block diagram and the truth table of the 1×2
multiplexer are given below.

31. Truth Table:

32. The logical expression of the term Y is
as follows:
• Y0=S0'.A
Y1=S0.A
• Logical circuit of the above expressions is given below:

33. 1×4 De-multiplexer:
• In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2,
and Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A. On the
basis of the combination of inputs which are present at the selection
lines S0 and S1, the input be connected to one of the outputs.
• The block diagram and the truth table of the 1×4 multiplexer are given
below.

34. Truth Table:

35. The logical expression of the term Y is
as follows:
• Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

36. 1×8 De-multiplexer
• In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2,
Y3, Y4, Y5, Y6, and Y7, 3 selection lines, i.e., S0, S1and S2 and single
input, i.e., A.
• On the basis of the combination of inputs which are present at the
selection lines S0, S1 and S2, the input will be connected to one of
these outputs.
• The block diagram and the truth table of the 1×8 de-multiplexer are
given below.

37. Block Diagram

38. Truth Table:

39. The logical expression of the term Y is
as follows:
• Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

40. Logical circuit of the above expressions
is given below:

41. Encoder
• An encoder is a combinational circuit that converts binary information
in the form of a 2N input lines into N output lines, which represent N bit
code for the input.
• For simple encoders, it is assumed that only one input line is active at
a time.
• As an example, let’s consider Octal to Binary encoder.
• As shown in the following figure, an octal-to-binary encoder takes 8
input lines and generates 3 output lines.

42. Encoders

43. Truth Table
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

44. Implementation –
• From the truth table, the output line Z is active when the input octal
digit is 1, 3, 5 or 7. Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7
and X is 1 for input octal digits 4, 5, 6 or 7. Hence, the Boolean
functions would be:
• X = D4 + D5 + D6 + D7
• Y = D2 +D3 + D6 + D7
• Z = D1 + D3 + D5 + D7

45. Hence, the encoder can be realised
with OR gates as follows:

46. Decoders –
• A decoder does the opposite job of an encoder. It is a combinational
circuit that converts n lines of input into 2n lines of output.
• Let’s take an example of 3-to-8 line decoder.

47. Truth Table
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

48. Implementation –
• D0 is high when X = 0, Y = 0 and Z = 0. Hence,
• D0 = X’ Y’ Z’
• Similarly,
• D1 = X’ Y’ Z
• D2 = X’ Y Z’
• D3 = X’ Y Z
• D4 = X Y’ Z’
• D5 = X Y’ Z
• D6 = X Y Z’
• D7 = X Y Z

49. Hence, the Decoders can be realised
as follows:

50. Decimal adders & amplitude
comparators
• The BCD-Adder is used in the computers and the calculators that
perform arithmetic operation directly in the decimal number system.
• The BCD-Adder accepts the binary-coded form of decimal numbers.
• The Decimal-Adder requires a minimum of nine inputs and five
outputs.

52. Amplitude comparators
• Amplitude comparator compares the amplitudes of two (or more) input quantities.
• The phase angle between the quantities under comparison (inputs) is not recognized or
noticed by the amplitude comparator.
• The function is represented by a circle in the complex plane with its centre at the origin.
This defines the boundary of the marginal operation.
• The main purpose of amplitude comparators is to provide direction and distance
protection.
• Mainly there are three types of amplitude comparators viz.:
• 1. Integrating Comparators,
• 2. Instantaneous Comparators, and
• 3. Sampling Comparators.

53. ROM as decoder
• It consists of k input lines and n output lines .
• The k input lines is used to take the input address from where we want
to access the content of the ROM .
• Since each of the k input lines can be either 0 or 1, so there are 2^k
total addresses which can be referred to by these input lines and each
of these addresses contain n bit information, which is given out as the
output of the ROM.
• Such a ROM is specified as 2^k x n ROM .

54. Structure of ROM

55. PLA & PAL
• PLA
• It stands for Programmable Logic Array.
• Its speed is lesser in comparison to PAL.
• It is highly complex.
• It is expensive.
• It is not available easily.
• It is used less in comparison to PAL.

56. PAL
• It stands for Programmable Array Logic.
• It has a higher speed in comparison to PLA.
• It is less complex.
• It is inexpensive.
• It is more readily available in comparison to PLA.
• It is used more in comparison to PLA.

57. Difference between PAL and PLA:
• PAL stands for programmable array logic, while PLA stands for a programmable logic array.
• The construction of PAL can be done using a programmable collection of AND & OR gates. The
construction of PLA can be done using the programmable collection of AND & fixed collection of
using OR gates.
• The flexibility of PAL programming is more, while PLA is less flexible.
• The availability of PAL is less prolific, The availability of PLA is more.
• The cost of a PAL is expensive, while the cost of PLA is a middle range.
• The number of functions implemented is PAL is large, The number of functions implemented is
limited.
• PAL more used than PLA, PLA is less used than PAL.
• The speed of PAL is too slow, but the speed of PLA is high.
• PAL complexity is high, The complexity of PLA is high.

58. Thank you